ichwd.h revision 218140
10Sduke/*- 23261Sohair * Copyright (c) 2004 Texas A&M University 30Sduke * All rights reserved. 40Sduke * 50Sduke * Developer: Wm. Daryl Hawkins 60Sduke * 70Sduke * Redistribution and use in source and binary forms, with or without 80Sduke * modification, are permitted provided that the following conditions 90Sduke * are met: 100Sduke * 1. Redistributions of source code must retain the above copyright 110Sduke * notice, this list of conditions and the following disclaimer. 120Sduke * 2. Redistributions in binary form must reproduce the above copyright 130Sduke * notice, this list of conditions and the following disclaimer in the 140Sduke * documentation and/or other materials provided with the distribution. 150Sduke * 160Sduke * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 170Sduke * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 180Sduke * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 192362Sohair * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 202362Sohair * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 212362Sohair * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 220Sduke * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 230Sduke * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 240Sduke * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 250Sduke * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 262578Schegar * SUCH DAMAGE. 270Sduke * 280Sduke * $FreeBSD: head/sys/dev/ichwd/ichwd.h 218140 2011-01-31 18:41:52Z jfv $ 290Sduke */ 300Sduke 310Sduke#ifndef _ICHWD_H_ 320Sduke#define _ICHWD_H_ 330Sduke 340Sdukestruct ichwd_device { 350Sduke uint16_t device; 360Sduke char *desc; 370Sduke unsigned int version; 380Sduke}; 390Sduke 400Sdukestruct ichwd_softc { 410Sduke device_t device; 420Sduke device_t ich; 430Sduke int ich_version; 440Sduke 450Sduke int active; 460Sduke unsigned int timeout; 470Sduke 480Sduke int smi_rid; 490Sduke struct resource *smi_res; 500Sduke bus_space_tag_t smi_bst; 510Sduke bus_space_handle_t smi_bsh; 520Sduke 530Sduke int tco_rid; 542578Schegar struct resource *tco_res; 550Sduke bus_space_tag_t tco_bst; 560Sduke bus_space_handle_t tco_bsh; 570Sduke 580Sduke int gcs_rid; 590Sduke struct resource *gcs_res; 600Sduke bus_space_tag_t gcs_bst; 610Sduke bus_space_handle_t gcs_bsh; 620Sduke 630Sduke eventhandler_tag ev_tag; 640Sduke}; 650Sduke 660Sduke#define VENDORID_INTEL 0x8086 670Sduke#define DEVICEID_CPT0 0x1c40 680Sduke#define DEVICEID_CPT1 0x1c41 690Sduke#define DEVICEID_CPT2 0x1c42 700Sduke#define DEVICEID_CPT3 0x1c43 710Sduke#define DEVICEID_CPT4 0x1c44 720Sduke#define DEVICEID_CPT5 0x1c45 730Sduke#define DEVICEID_CPT6 0x1c46 740Sduke#define DEVICEID_CPT7 0x1c47 750Sduke#define DEVICEID_CPT8 0x1c48 760Sduke#define DEVICEID_CPT9 0x1c49 77#define DEVICEID_CPT10 0x1c4a 78#define DEVICEID_CPT11 0x1c4b 79#define DEVICEID_CPT12 0x1c4c 80#define DEVICEID_CPT13 0x1c4d 81#define DEVICEID_CPT14 0x1c4e 82#define DEVICEID_CPT15 0x1c4f 83#define DEVICEID_CPT16 0x1c50 84#define DEVICEID_CPT17 0x1c51 85#define DEVICEID_CPT18 0x1c52 86#define DEVICEID_CPT19 0x1c53 87#define DEVICEID_CPT20 0x1c54 88#define DEVICEID_CPT21 0x1c55 89#define DEVICEID_CPT22 0x1c56 90#define DEVICEID_CPT23 0x1c57 91#define DEVICEID_CPT24 0x1c58 92#define DEVICEID_CPT25 0x1c59 93#define DEVICEID_CPT26 0x1c5a 94#define DEVICEID_CPT27 0x1c5b 95#define DEVICEID_CPT28 0x1c5c 96#define DEVICEID_CPT29 0x1c5d 97#define DEVICEID_CPT30 0x1c5e 98#define DEVICEID_CPT31 0x1c5f 99#define DEVICEID_DH89XXCC_LPC 0x2310 100#define DEVICEID_82801AA 0x2410 101#define DEVICEID_82801AB 0x2420 102#define DEVICEID_82801BA 0x2440 103#define DEVICEID_82801BAM 0x244c 104#define DEVICEID_82801CA 0x2480 105#define DEVICEID_82801CAM 0x248c 106#define DEVICEID_82801DB 0x24c0 107#define DEVICEID_82801DBM 0x24cc 108#define DEVICEID_82801E 0x2450 109#define DEVICEID_82801EB 0x24dc 110#define DEVICEID_82801EBR 0x24d0 111#define DEVICEID_6300ESB 0x25a1 112#define DEVICEID_82801FBR 0x2640 113#define DEVICEID_ICH6M 0x2641 114#define DEVICEID_ICH6W 0x2642 115#define DEVICEID_63XXESB 0x2670 116#define DEVICEID_ICH7 0x27b8 117#define DEVICEID_ICH7DH 0x27b0 118#define DEVICEID_ICH7M 0x27b9 119#define DEVICEID_NM10 0x27bc 120#define DEVICEID_ICH7MDH 0x27bd 121#define DEVICEID_ICH8 0x2810 122#define DEVICEID_ICH8DH 0x2812 123#define DEVICEID_ICH8DO 0x2814 124#define DEVICEID_ICH8M 0x2815 125#define DEVICEID_ICH8ME 0x2811 126#define DEVICEID_ICH9 0x2918 127#define DEVICEID_ICH9DH 0x2912 128#define DEVICEID_ICH9DO 0x2914 129#define DEVICEID_ICH9M 0x2919 130#define DEVICEID_ICH9ME 0x2917 131#define DEVICEID_ICH9R 0x2916 132#define DEVICEID_ICH10 0x3a18 133#define DEVICEID_ICH10D 0x3a1a 134#define DEVICEID_ICH10DO 0x3a14 135#define DEVICEID_ICH10R 0x3a16 136#define DEVICEID_PCH 0x3b00 137#define DEVICEID_PCHM 0x3b01 138#define DEVICEID_P55 0x3b02 139#define DEVICEID_PM55 0x3b03 140#define DEVICEID_H55 0x3b06 141#define DEVICEID_QM57 0x3b07 142#define DEVICEID_H57 0x3b08 143#define DEVICEID_HM55 0x3b09 144#define DEVICEID_Q57 0x3b0a 145#define DEVICEID_HM57 0x3b0b 146#define DEVICEID_PCHMSFF 0x3b0d 147#define DEVICEID_QS57 0x3b0f 148#define DEVICEID_3400 0x3b12 149#define DEVICEID_3420 0x3b14 150#define DEVICEID_3450 0x3b16 151 152/* ICH LPC Interface Bridge Registers (ICH5 and older) */ 153#define ICH_GEN_STA 0xd4 154#define ICH_GEN_STA_NO_REBOOT 0x02 155#define ICH_PMBASE 0x40 /* ACPI base address register */ 156#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 157 158/* ICH Chipset Configuration Registers (ICH6 and newer) */ 159#define ICH_RCBA 0xf0 160#define ICH_GCS_OFFSET 0x3410 161#define ICH_GCS_SIZE 0x4 162#define ICH_GCS_NO_REBOOT 0x20 163 164/* register names and locations (relative to PMBASE) */ 165#define SMI_BASE 0x30 /* base address for SMI registers */ 166#define SMI_LEN 0x08 167#define SMI_EN 0x00 /* SMI Control and Enable Register */ 168#define SMI_STS 0x04 /* SMI Status Register */ 169#define TCO_BASE 0x60 /* base address for TCO registers */ 170#define TCO_LEN 0x20 171#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 172#define TCO_TMR1 0x01 /* TCO Timer Initial Value 173 (ICH5 and older, 8 bits) */ 174#define TCO_TMR2 0x12 /* TCO Timer Initial Value 175 (ICH6 and newer, 16 bits) */ 176#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 177#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 178#define TCO1_STS 0x04 /* TCO Status 1 */ 179#define TCO2_STS 0x06 /* TCO Status 2 */ 180#define TCO1_CNT 0x08 /* TCO Control 1 */ 181#define TCO2_CNT 0x08 /* TCO Control 2 */ 182 183/* bit definitions for SMI_EN and SMI_STS */ 184#define SMI_TCO_EN 0x2000 185#define SMI_TCO_STS 0x2000 186 187/* timer value mask for TCO_RLD and TCO_TMR */ 188#define TCO_TIMER_MASK 0x1f 189 190/* status bits for TCO1_STS */ 191#define TCO_TIMEOUT 0x08 /* timed out */ 192#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 193#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 194 195/* status bits for TCO2_STS */ 196#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 197#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 198 199/* control bits for TCO1_CNT */ 200#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 201#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 202 203/* 204 * Masks for the TCO timer value field in TCO_RLD. 205 * If the datasheets are to be believed, the minimum value actually varies 206 * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 207 * I suspect this is a bug in the ICH5 datasheet and that the minimum is 208 * uniformly 2, but I'd rather err on the side of caution. 209 */ 210#define TCO_RLD_TMR_MIN 0x0004 211#define TCO_RLD1_TMR_MAX 0x003f 212#define TCO_RLD2_TMR_MAX 0x03ff 213 214/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */ 215#define ICHWD_TICK 600000000 216 217#endif 218