ichwd.h revision 155785
1139749Simp/*- 2129124Sdes * Copyright (c) 2004 Texas A&M University 3129124Sdes * All rights reserved. 4129124Sdes * 5129124Sdes * Developer: Wm. Daryl Hawkins 6129124Sdes * 7129124Sdes * Redistribution and use in source and binary forms, with or without 8129124Sdes * modification, are permitted provided that the following conditions 9129124Sdes * are met: 10129124Sdes * 1. Redistributions of source code must retain the above copyright 11129124Sdes * notice, this list of conditions and the following disclaimer. 12129124Sdes * 2. Redistributions in binary form must reproduce the above copyright 13129124Sdes * notice, this list of conditions and the following disclaimer in the 14129124Sdes * documentation and/or other materials provided with the distribution. 15129124Sdes * 16129124Sdes * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17129124Sdes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18129124Sdes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19129124Sdes * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20129124Sdes * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21129124Sdes * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22129124Sdes * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23129124Sdes * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24129124Sdes * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25129124Sdes * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26129124Sdes * SUCH DAMAGE. 27129124Sdes * 28129124Sdes * $FreeBSD: head/sys/dev/ichwd/ichwd.h 155785 2006-02-17 18:46:18Z ambrisko $ 29129124Sdes */ 30129124Sdes 31129124Sdes#ifndef _ICHWD_H_ 32129124Sdes#define _ICHWD_H_ 33129124Sdes 34129124Sdesstruct ichwd_device { 35129124Sdes uint16_t vendor; 36129124Sdes uint16_t device; 37129124Sdes char *desc; 38129124Sdes}; 39129124Sdes 40129124Sdesstruct ichwd_softc { 41129124Sdes device_t device; 42129124Sdes 43129124Sdes int active; 44129124Sdes unsigned int timeout; 45129124Sdes 46129124Sdes int smi_rid; 47129124Sdes struct resource *smi_res; 48129124Sdes bus_space_tag_t smi_bst; 49129124Sdes bus_space_handle_t smi_bsh; 50129124Sdes 51129124Sdes int tco_rid; 52129124Sdes struct resource *tco_res; 53129124Sdes bus_space_tag_t tco_bst; 54129124Sdes bus_space_handle_t tco_bsh; 55129124Sdes 56129124Sdes eventhandler_tag ev_tag; 57129124Sdes}; 58129124Sdes 59129124Sdes#define VENDORID_INTEL 0x8086 60129124Sdes#define DEVICEID_82801AA 0x2410 61129124Sdes#define DEVICEID_82801AB 0x2420 62129124Sdes#define DEVICEID_82801BA 0x2440 63129124Sdes#define DEVICEID_82801BAM 0x244c 64129124Sdes#define DEVICEID_82801CA 0x2480 65129124Sdes#define DEVICEID_82801CAM 0x248c 66129124Sdes#define DEVICEID_82801DB 0x24c0 67129124Sdes#define DEVICEID_82801DBM 0x24cc 68129124Sdes#define DEVICEID_82801E 0x2450 69129124Sdes#define DEVICEID_82801EBR 0x24d0 70155785Sambrisko#define DEVICEID_6300ESB 0x25a1 71155785Sambrisko#define DEVICEID_82801FBR 0x2640 72155785Sambrisko#define DEVICEID_ICH5 0x27b8 73129124Sdes 74129124Sdes/* ICH LPC Interface Bridge Registers */ 75129124Sdes#define ICH_GEN_STA 0xd4 76129124Sdes#define ICH_GEN_STA_NO_REBOOT 0x02 77129124Sdes#define ICH_PMBASE 0x40 /* ACPI base address register */ 78129124Sdes#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 79129124Sdes 80129124Sdes/* register names and locations (relative to PMBASE) */ 81129124Sdes#define SMI_BASE 0x30 /* base address for SMI registers */ 82129124Sdes#define SMI_LEN 0x08 83129124Sdes#define SMI_EN 0x00 /* SMI Control and Enable Register */ 84129124Sdes#define SMI_STS 0x04 /* SMI Status Register */ 85129124Sdes#define TCO_BASE 0x60 /* base address for TCO registers */ 86129124Sdes#define TCO_LEN 0x0a 87129124Sdes#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 88129124Sdes#define TCO_TMR 0x01 /* TCO Timer Initial Value */ 89129124Sdes#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 90129124Sdes#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 91129124Sdes#define TCO1_STS 0x04 /* TCO Status 1 */ 92129124Sdes#define TCO2_STS 0x06 /* TCO Status 2 */ 93129124Sdes#define TCO1_CNT 0x08 /* TCO Control 1 */ 94129124Sdes 95129124Sdes/* bit definitions for SMI_EN and SMI_STS */ 96129124Sdes#define SMI_TCO_EN 0x2000 97129124Sdes#define SMI_TCO_STS 0x2000 98129124Sdes 99129124Sdes/* timer value mask for TCO_RLD and TCO_TMR */ 100129124Sdes#define TCO_TIMER_MASK 0x1f 101129124Sdes 102129124Sdes/* status bits for TCO1_STS */ 103129124Sdes#define TCO_TIMEOUT 0x08 /* timed out */ 104129124Sdes#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 105129124Sdes#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 106129124Sdes 107129124Sdes/* status bits for TCO2_STS */ 108129124Sdes#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 109129124Sdes#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 110129124Sdes 111129124Sdes/* control bits for TCO1_CNT */ 112129124Sdes#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 113129124Sdes#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 114129124Sdes 115129124Sdes/* approximate length in nanoseconds of one WDT tick */ 116155785Sambrisko#define ICHWD_TICK 1800000000 117129124Sdes 118129124Sdes/* minimum / maximum timeout in WDT ticks */ 119129124Sdes#define ICHWD_MIN_TIMEOUT 2 120129124Sdes#define ICHWD_MAX_TIMEOUT 63 121129124Sdes 122129124Sdes#endif 123