ichwd.h revision 155785
137904Sjlemon/*- 237904Sjlemon * Copyright (c) 2004 Texas A&M University 337904Sjlemon * All rights reserved. 437904Sjlemon * 537904Sjlemon * Developer: Wm. Daryl Hawkins 637904Sjlemon * 737904Sjlemon * Redistribution and use in source and binary forms, with or without 837904Sjlemon * modification, are permitted provided that the following conditions 937904Sjlemon * are met: 1037904Sjlemon * 1. Redistributions of source code must retain the above copyright 1137904Sjlemon * notice, this list of conditions and the following disclaimer. 1237904Sjlemon * 2. Redistributions in binary form must reproduce the above copyright 1337904Sjlemon * notice, this list of conditions and the following disclaimer in the 1437904Sjlemon * documentation and/or other materials provided with the distribution. 1537904Sjlemon * 1637904Sjlemon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1737904Sjlemon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1837904Sjlemon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1937904Sjlemon * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2037904Sjlemon * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2137904Sjlemon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2237904Sjlemon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2337904Sjlemon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2437904Sjlemon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2537904Sjlemon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2637904Sjlemon * SUCH DAMAGE. 2792986Sobrien * 2892986Sobrien * $FreeBSD: head/sys/dev/ichwd/ichwd.h 155785 2006-02-17 18:46:18Z ambrisko $ 2937904Sjlemon */ 3037904Sjlemon 3137904Sjlemon#ifndef _ICHWD_H_ 3237904Sjlemon#define _ICHWD_H_ 3337904Sjlemon 3437904Sjlemonstruct ichwd_device { 3550817Sluoqi uint16_t vendor; 3637904Sjlemon uint16_t device; 3737904Sjlemon char *desc; 3850817Sluoqi}; 3937904Sjlemon 40124296Snectarstruct ichwd_softc { 4137904Sjlemon device_t device; 42 43 int active; 44 unsigned int timeout; 45 46 int smi_rid; 47 struct resource *smi_res; 48 bus_space_tag_t smi_bst; 49 bus_space_handle_t smi_bsh; 50 51 int tco_rid; 52 struct resource *tco_res; 53 bus_space_tag_t tco_bst; 54 bus_space_handle_t tco_bsh; 55 56 eventhandler_tag ev_tag; 57}; 58 59#define VENDORID_INTEL 0x8086 60#define DEVICEID_82801AA 0x2410 61#define DEVICEID_82801AB 0x2420 62#define DEVICEID_82801BA 0x2440 63#define DEVICEID_82801BAM 0x244c 64#define DEVICEID_82801CA 0x2480 65#define DEVICEID_82801CAM 0x248c 66#define DEVICEID_82801DB 0x24c0 67#define DEVICEID_82801DBM 0x24cc 68#define DEVICEID_82801E 0x2450 69#define DEVICEID_82801EBR 0x24d0 70#define DEVICEID_6300ESB 0x25a1 71#define DEVICEID_82801FBR 0x2640 72#define DEVICEID_ICH5 0x27b8 73 74/* ICH LPC Interface Bridge Registers */ 75#define ICH_GEN_STA 0xd4 76#define ICH_GEN_STA_NO_REBOOT 0x02 77#define ICH_PMBASE 0x40 /* ACPI base address register */ 78#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 79 80/* register names and locations (relative to PMBASE) */ 81#define SMI_BASE 0x30 /* base address for SMI registers */ 82#define SMI_LEN 0x08 83#define SMI_EN 0x00 /* SMI Control and Enable Register */ 84#define SMI_STS 0x04 /* SMI Status Register */ 85#define TCO_BASE 0x60 /* base address for TCO registers */ 86#define TCO_LEN 0x0a 87#define TCO_RLD 0x00 /* TCO Reload and Current Value */ 88#define TCO_TMR 0x01 /* TCO Timer Initial Value */ 89#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 90#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 91#define TCO1_STS 0x04 /* TCO Status 1 */ 92#define TCO2_STS 0x06 /* TCO Status 2 */ 93#define TCO1_CNT 0x08 /* TCO Control 1 */ 94 95/* bit definitions for SMI_EN and SMI_STS */ 96#define SMI_TCO_EN 0x2000 97#define SMI_TCO_STS 0x2000 98 99/* timer value mask for TCO_RLD and TCO_TMR */ 100#define TCO_TIMER_MASK 0x1f 101 102/* status bits for TCO1_STS */ 103#define TCO_TIMEOUT 0x08 /* timed out */ 104#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */ 105#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */ 106 107/* status bits for TCO2_STS */ 108#define TCO_BOOT_STS 0x04 /* failed to come out of reset */ 109#define TCO_SECOND_TO_STS 0x02 /* ran down twice */ 110 111/* control bits for TCO1_CNT */ 112#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 113#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */ 114 115/* approximate length in nanoseconds of one WDT tick */ 116#define ICHWD_TICK 1800000000 117 118/* minimum / maximum timeout in WDT ticks */ 119#define ICHWD_MIN_TIMEOUT 2 120#define ICHWD_MAX_TIMEOUT 63 121 122#endif 123