1177867Sjfv/****************************************************************************** 2177867Sjfv 3218530Sjfv Copyright (c) 2001-2010, Intel Corporation 4177867Sjfv All rights reserved. 5177867Sjfv 6177867Sjfv Redistribution and use in source and binary forms, with or without 7177867Sjfv modification, are permitted provided that the following conditions are met: 8177867Sjfv 9177867Sjfv 1. Redistributions of source code must retain the above copyright notice, 10177867Sjfv this list of conditions and the following disclaimer. 11177867Sjfv 12177867Sjfv 2. Redistributions in binary form must reproduce the above copyright 13177867Sjfv notice, this list of conditions and the following disclaimer in the 14177867Sjfv documentation and/or other materials provided with the distribution. 15177867Sjfv 16177867Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17177867Sjfv contributors may be used to endorse or promote products derived from 18177867Sjfv this software without specific prior written permission. 19177867Sjfv 20177867Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21177867Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22177867Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23177867Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24177867Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25177867Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26177867Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27177867Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28177867Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29177867Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30177867Sjfv POSSIBILITY OF SUCH DAMAGE. 31177867Sjfv 32177867Sjfv******************************************************************************/ 33177867Sjfv/*$FreeBSD: releng/10.2/sys/dev/e1000/e1000_osdep.c 219902 2011-03-23 13:10:15Z jhb $*/ 34177867Sjfv 35177867Sjfv#include "e1000_api.h" 36177867Sjfv 37177867Sjfv/* 38177867Sjfv * NOTE: the following routines using the e1000 39177867Sjfv * naming style are provided to the shared 40177867Sjfv * code but are OS specific 41177867Sjfv */ 42177867Sjfv 43177867Sjfvvoid 44194865Sjfve1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 45177867Sjfv{ 46177867Sjfv pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2); 47177867Sjfv} 48177867Sjfv 49177867Sjfvvoid 50194865Sjfve1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) 51177867Sjfv{ 52177867Sjfv *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2); 53177867Sjfv} 54177867Sjfv 55177867Sjfvvoid 56177867Sjfve1000_pci_set_mwi(struct e1000_hw *hw) 57177867Sjfv{ 58177867Sjfv pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 59177867Sjfv (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 60177867Sjfv} 61177867Sjfv 62177867Sjfvvoid 63177867Sjfve1000_pci_clear_mwi(struct e1000_hw *hw) 64177867Sjfv{ 65177867Sjfv pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 66177867Sjfv (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 67177867Sjfv} 68177867Sjfv 69177867Sjfv/* 70177867Sjfv * Read the PCI Express capabilities 71177867Sjfv */ 72177867Sjfvint32_t 73194865Sjfve1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 74177867Sjfv{ 75194865Sjfv device_t dev = ((struct e1000_osdep *)hw->back)->dev; 76194865Sjfv u32 offset; 77177867Sjfv 78219902Sjhb pci_find_cap(dev, PCIY_EXPRESS, &offset); 79194865Sjfv *value = pci_read_config(dev, offset + reg, 2); 80177867Sjfv return (E1000_SUCCESS); 81177867Sjfv} 82194865Sjfv 83194865Sjfv/* 84194865Sjfv * Write the PCI Express capabilities 85194865Sjfv */ 86194865Sjfvint32_t 87194865Sjfve1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 88194865Sjfv{ 89194865Sjfv device_t dev = ((struct e1000_osdep *)hw->back)->dev; 90194865Sjfv u32 offset; 91194865Sjfv 92219902Sjhb pci_find_cap(dev, PCIY_EXPRESS, &offset); 93194865Sjfv pci_write_config(dev, offset + reg, *value, 2); 94194865Sjfv return (E1000_SUCCESS); 95194865Sjfv} 96