1/*- 2 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.2/sys/dev/ata/ata-all.h 280276 2015-03-20 08:28:11Z mav $ 27 */ 28 29#if 0 30#define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 31 * some modern devices */ 32#endif 33 34/* ATA register defines */ 35#define ATA_DATA 0 /* (RW) data */ 36 37#define ATA_FEATURE 1 /* (W) feature */ 38#define ATA_F_DMA 0x01 /* enable DMA */ 39#define ATA_F_OVL 0x02 /* enable overlap */ 40 41#define ATA_COUNT 2 /* (W) sector count */ 42 43#define ATA_SECTOR 3 /* (RW) sector # */ 44#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 45#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 46#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 47#define ATA_D_LBA 0x40 /* use LBA addressing */ 48#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 49 50#define ATA_COMMAND 7 /* (W) command */ 51 52#define ATA_ERROR 8 /* (R) error */ 53#define ATA_E_ILI 0x01 /* illegal length */ 54#define ATA_E_NM 0x02 /* no media */ 55#define ATA_E_ABORT 0x04 /* command aborted */ 56#define ATA_E_MCR 0x08 /* media change request */ 57#define ATA_E_IDNF 0x10 /* ID not found */ 58#define ATA_E_MC 0x20 /* media changed */ 59#define ATA_E_UNC 0x40 /* uncorrectable data */ 60#define ATA_E_ICRC 0x80 /* UDMA crc error */ 61#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 62 63#define ATA_IREASON 9 /* (R) interrupt reason */ 64#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 65#define ATA_I_IN 0x02 /* read (1) | write (0) */ 66#define ATA_I_RELEASE 0x04 /* released bus (1) */ 67#define ATA_I_TAGMASK 0xf8 /* tag mask */ 68 69#define ATA_STATUS 10 /* (R) status */ 70#define ATA_ALTSTAT 11 /* (R) alternate status */ 71#define ATA_S_ERROR 0x01 /* error */ 72#define ATA_S_INDEX 0x02 /* index */ 73#define ATA_S_CORR 0x04 /* data corrected */ 74#define ATA_S_DRQ 0x08 /* data request */ 75#define ATA_S_DSC 0x10 /* drive seek completed */ 76#define ATA_S_SERVICE 0x10 /* drive needs service */ 77#define ATA_S_DWF 0x20 /* drive write fault */ 78#define ATA_S_DMA 0x20 /* DMA ready */ 79#define ATA_S_READY 0x40 /* drive ready */ 80#define ATA_S_BUSY 0x80 /* busy */ 81 82#define ATA_CONTROL 12 /* (W) control */ 83 84#define ATA_CTLOFFSET 0x206 /* control register offset */ 85#define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 86#define ATA_PC98_CTLOFFSET 0x10c /* do for PC98 devices */ 87#define ATA_A_IDS 0x02 /* disable interrupts */ 88#define ATA_A_RESET 0x04 /* RESET controller */ 89#ifdef ATA_LEGACY_SUPPORT 90#define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 91#else 92#define ATA_A_4BIT 0x00 93#endif 94#define ATA_A_HOB 0x80 /* High Order Byte enable */ 95 96/* SATA register defines */ 97#define ATA_SSTATUS 13 98#define ATA_SS_DET_MASK 0x0000000f 99#define ATA_SS_DET_NO_DEVICE 0x00000000 100#define ATA_SS_DET_DEV_PRESENT 0x00000001 101#define ATA_SS_DET_PHY_ONLINE 0x00000003 102#define ATA_SS_DET_PHY_OFFLINE 0x00000004 103 104#define ATA_SS_SPD_MASK 0x000000f0 105#define ATA_SS_SPD_NO_SPEED 0x00000000 106#define ATA_SS_SPD_GEN1 0x00000010 107#define ATA_SS_SPD_GEN2 0x00000020 108#define ATA_SS_SPD_GEN3 0x00000030 109 110#define ATA_SS_IPM_MASK 0x00000f00 111#define ATA_SS_IPM_NO_DEVICE 0x00000000 112#define ATA_SS_IPM_ACTIVE 0x00000100 113#define ATA_SS_IPM_PARTIAL 0x00000200 114#define ATA_SS_IPM_SLUMBER 0x00000600 115 116#define ATA_SERROR 14 117#define ATA_SE_DATA_CORRECTED 0x00000001 118#define ATA_SE_COMM_CORRECTED 0x00000002 119#define ATA_SE_DATA_ERR 0x00000100 120#define ATA_SE_COMM_ERR 0x00000200 121#define ATA_SE_PROT_ERR 0x00000400 122#define ATA_SE_HOST_ERR 0x00000800 123#define ATA_SE_PHY_CHANGED 0x00010000 124#define ATA_SE_PHY_IERROR 0x00020000 125#define ATA_SE_COMM_WAKE 0x00040000 126#define ATA_SE_DECODE_ERR 0x00080000 127#define ATA_SE_PARITY_ERR 0x00100000 128#define ATA_SE_CRC_ERR 0x00200000 129#define ATA_SE_HANDSHAKE_ERR 0x00400000 130#define ATA_SE_LINKSEQ_ERR 0x00800000 131#define ATA_SE_TRANSPORT_ERR 0x01000000 132#define ATA_SE_UNKNOWN_FIS 0x02000000 133 134#define ATA_SCONTROL 15 135#define ATA_SC_DET_MASK 0x0000000f 136#define ATA_SC_DET_IDLE 0x00000000 137#define ATA_SC_DET_RESET 0x00000001 138#define ATA_SC_DET_DISABLE 0x00000004 139 140#define ATA_SC_SPD_MASK 0x000000f0 141#define ATA_SC_SPD_NO_SPEED 0x00000000 142#define ATA_SC_SPD_SPEED_GEN1 0x00000010 143#define ATA_SC_SPD_SPEED_GEN2 0x00000020 144#define ATA_SC_SPD_SPEED_GEN3 0x00000030 145 146#define ATA_SC_IPM_MASK 0x00000f00 147#define ATA_SC_IPM_NONE 0x00000000 148#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 149#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 150 151#define ATA_SACTIVE 16 152 153/* SATA AHCI v1.0 register defines */ 154#define ATA_AHCI_CAP 0x00 155#define ATA_AHCI_CAP_NPMASK 0x0000001f 156#define ATA_AHCI_CAP_SXS 0x00000020 157#define ATA_AHCI_CAP_EMS 0x00000040 158#define ATA_AHCI_CAP_CCCS 0x00000080 159#define ATA_AHCI_CAP_NCS 0x00001F00 160#define ATA_AHCI_CAP_NCS_SHIFT 8 161#define ATA_AHCI_CAP_PSC 0x00002000 162#define ATA_AHCI_CAP_SSC 0x00004000 163#define ATA_AHCI_CAP_PMD 0x00008000 164#define ATA_AHCI_CAP_FBSS 0x00010000 165#define ATA_AHCI_CAP_SPM 0x00020000 166#define ATA_AHCI_CAP_SAM 0x00080000 167#define ATA_AHCI_CAP_ISS 0x00F00000 168#define ATA_AHCI_CAP_ISS_SHIFT 20 169#define ATA_AHCI_CAP_SCLO 0x01000000 170#define ATA_AHCI_CAP_SAL 0x02000000 171#define ATA_AHCI_CAP_SALP 0x04000000 172#define ATA_AHCI_CAP_SSS 0x08000000 173#define ATA_AHCI_CAP_SMPS 0x10000000 174#define ATA_AHCI_CAP_SSNTF 0x20000000 175#define ATA_AHCI_CAP_SNCQ 0x40000000 176#define ATA_AHCI_CAP_64BIT 0x80000000 177 178#define ATA_AHCI_GHC 0x04 179#define ATA_AHCI_GHC_AE 0x80000000 180#define ATA_AHCI_GHC_IE 0x00000002 181#define ATA_AHCI_GHC_HR 0x00000001 182 183#define ATA_AHCI_IS 0x08 184#define ATA_AHCI_PI 0x0c 185#define ATA_AHCI_VS 0x10 186 187#define ATA_AHCI_OFFSET 0x80 188 189#define ATA_AHCI_P_CLB 0x100 190#define ATA_AHCI_P_CLBU 0x104 191#define ATA_AHCI_P_FB 0x108 192#define ATA_AHCI_P_FBU 0x10c 193#define ATA_AHCI_P_IS 0x110 194#define ATA_AHCI_P_IE 0x114 195#define ATA_AHCI_P_IX_DHR 0x00000001 196#define ATA_AHCI_P_IX_PS 0x00000002 197#define ATA_AHCI_P_IX_DS 0x00000004 198#define ATA_AHCI_P_IX_SDB 0x00000008 199#define ATA_AHCI_P_IX_UF 0x00000010 200#define ATA_AHCI_P_IX_DP 0x00000020 201#define ATA_AHCI_P_IX_PC 0x00000040 202#define ATA_AHCI_P_IX_DI 0x00000080 203 204#define ATA_AHCI_P_IX_PRC 0x00400000 205#define ATA_AHCI_P_IX_IPM 0x00800000 206#define ATA_AHCI_P_IX_OF 0x01000000 207#define ATA_AHCI_P_IX_INF 0x04000000 208#define ATA_AHCI_P_IX_IF 0x08000000 209#define ATA_AHCI_P_IX_HBD 0x10000000 210#define ATA_AHCI_P_IX_HBF 0x20000000 211#define ATA_AHCI_P_IX_TFE 0x40000000 212#define ATA_AHCI_P_IX_CPD 0x80000000 213 214#define ATA_AHCI_P_CMD 0x118 215#define ATA_AHCI_P_CMD_ST 0x00000001 216#define ATA_AHCI_P_CMD_SUD 0x00000002 217#define ATA_AHCI_P_CMD_POD 0x00000004 218#define ATA_AHCI_P_CMD_CLO 0x00000008 219#define ATA_AHCI_P_CMD_FRE 0x00000010 220#define ATA_AHCI_P_CMD_CCS_MASK 0x00001f00 221#define ATA_AHCI_P_CMD_ISS 0x00002000 222#define ATA_AHCI_P_CMD_FR 0x00004000 223#define ATA_AHCI_P_CMD_CR 0x00008000 224#define ATA_AHCI_P_CMD_CPS 0x00010000 225#define ATA_AHCI_P_CMD_PMA 0x00020000 226#define ATA_AHCI_P_CMD_HPCP 0x00040000 227#define ATA_AHCI_P_CMD_ISP 0x00080000 228#define ATA_AHCI_P_CMD_CPD 0x00100000 229#define ATA_AHCI_P_CMD_ATAPI 0x01000000 230#define ATA_AHCI_P_CMD_DLAE 0x02000000 231#define ATA_AHCI_P_CMD_ALPE 0x04000000 232#define ATA_AHCI_P_CMD_ASP 0x08000000 233#define ATA_AHCI_P_CMD_ICC_MASK 0xf0000000 234#define ATA_AHCI_P_CMD_NOOP 0x00000000 235#define ATA_AHCI_P_CMD_ACTIVE 0x10000000 236#define ATA_AHCI_P_CMD_PARTIAL 0x20000000 237#define ATA_AHCI_P_CMD_SLUMBER 0x60000000 238 239#define ATA_AHCI_P_TFD 0x120 240#define ATA_AHCI_P_SIG 0x124 241#define ATA_AHCI_P_SSTS 0x128 242#define ATA_AHCI_P_SCTL 0x12c 243#define ATA_AHCI_P_SERR 0x130 244#define ATA_AHCI_P_SACT 0x134 245#define ATA_AHCI_P_CI 0x138 246#define ATA_AHCI_P_SNTF 0x13C 247#define ATA_AHCI_P_FBS 0x140 248 249#define ATA_AHCI_CL_SIZE 32 250#define ATA_AHCI_CL_OFFSET 0 251#define ATA_AHCI_FB_OFFSET (ATA_AHCI_CL_SIZE * 32) 252#define ATA_AHCI_CT_OFFSET (ATA_AHCI_FB_OFFSET + 4096) 253#define ATA_AHCI_CT_SIZE (2176 + 128) 254 255struct ata_ahci_dma_prd { 256 u_int64_t dba; 257 u_int32_t reserved; 258 u_int32_t dbc; /* 0 based */ 259#define ATA_AHCI_PRD_MASK 0x003fffff /* max 4MB */ 260#define ATA_AHCI_PRD_IPC (1<<31) 261} __packed; 262 263struct ata_ahci_cmd_tab { 264 u_int8_t cfis[64]; 265 u_int8_t acmd[32]; 266 u_int8_t reserved[32]; 267#define ATA_AHCI_DMA_ENTRIES 129 268 struct ata_ahci_dma_prd prd_tab[ATA_AHCI_DMA_ENTRIES]; 269} __packed; 270 271struct ata_ahci_cmd_list { 272 u_int16_t cmd_flags; 273#define ATA_AHCI_CMD_ATAPI 0x0020 274#define ATA_AHCI_CMD_WRITE 0x0040 275#define ATA_AHCI_CMD_PREFETCH 0x0080 276#define ATA_AHCI_CMD_RESET 0x0100 277#define ATA_AHCI_CMD_BIST 0x0200 278#define ATA_AHCI_CMD_CLR_BUSY 0x0400 279 280 u_int16_t prd_length; /* PRD entries */ 281 u_int32_t bytecount; 282 u_int64_t cmd_table_phys; /* 128byte aligned */ 283} __packed; 284 285 286/* DMA register defines */ 287#define ATA_DMA_ENTRIES 256 288#define ATA_DMA_EOT 0x80000000 289 290#define ATA_BMCMD_PORT 17 291#define ATA_BMCMD_START_STOP 0x01 292#define ATA_BMCMD_WRITE_READ 0x08 293 294#define ATA_BMDEVSPEC_0 18 295#define ATA_BMSTAT_PORT 19 296#define ATA_BMSTAT_ACTIVE 0x01 297#define ATA_BMSTAT_ERROR 0x02 298#define ATA_BMSTAT_INTERRUPT 0x04 299#define ATA_BMSTAT_MASK 0x07 300#define ATA_BMSTAT_DMA_MASTER 0x20 301#define ATA_BMSTAT_DMA_SLAVE 0x40 302#define ATA_BMSTAT_DMA_SIMPLEX 0x80 303 304#define ATA_BMDEVSPEC_1 20 305#define ATA_BMDTP_PORT 21 306 307#define ATA_IDX_ADDR 22 308#define ATA_IDX_DATA 23 309#define ATA_MAX_RES 24 310 311/* misc defines */ 312#define ATA_PRIMARY 0x1f0 313#define ATA_SECONDARY 0x170 314#define ATA_PC98_BANK 0x432 315#define ATA_IOSIZE 0x08 316#define ATA_PC98_IOSIZE 0x10 317#define ATA_CTLIOSIZE 0x01 318#define ATA_BMIOSIZE 0x08 319#define ATA_PC98_BANKIOSIZE 0x01 320#define ATA_IOADDR_RID 0 321#define ATA_CTLADDR_RID 1 322#define ATA_BMADDR_RID 0x20 323#define ATA_PC98_CTLADDR_RID 8 324#define ATA_PC98_BANKADDR_RID 9 325#define ATA_IRQ_RID 0 326#define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 327#define ATA_CFA_MAGIC1 0x844A 328#define ATA_CFA_MAGIC2 0x848A 329#define ATA_CFA_MAGIC3 0x8400 330#define ATAPI_MAGIC_LSB 0x14 331#define ATAPI_MAGIC_MSB 0xeb 332#define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 333#define ATAPI_P_WRITE (ATA_S_DRQ) 334#define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 335#define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 336#define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 337#define ATAPI_P_ABORT 0 338#define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 339#define ATA_OP_CONTINUES 0 340#define ATA_OP_FINISHED 1 341#define ATA_MAX_28BIT_LBA 268435455UL 342 343#ifndef ATA_REQUEST_TIMEOUT 344#define ATA_REQUEST_TIMEOUT 10 345#endif 346 347/* structure used for composite atomic operations */ 348#define MAX_COMPOSITES 32 /* u_int32_t bits */ 349struct ata_composite { 350 struct mtx lock; /* control lock */ 351 u_int32_t rd_needed; /* needed read subdisks */ 352 u_int32_t rd_done; /* done read subdisks */ 353 u_int32_t wr_needed; /* needed write subdisks */ 354 u_int32_t wr_depend; /* write depends on subdisks */ 355 u_int32_t wr_done; /* done write subdisks */ 356 struct ata_request *request[MAX_COMPOSITES]; 357 u_int32_t residual; /* bytes still to transfer */ 358 caddr_t data_1; 359 caddr_t data_2; 360}; 361 362/* structure used to queue an ATA/ATAPI request */ 363struct ata_request { 364 device_t dev; /* device handle */ 365 device_t parent; /* channel handle */ 366 int unit; /* physical unit */ 367 union { 368 struct { 369 u_int8_t command; /* command reg */ 370 u_int16_t feature; /* feature reg */ 371 u_int16_t count; /* count reg */ 372 u_int64_t lba; /* lba reg */ 373 } ata; 374 struct { 375 u_int8_t ccb[16]; /* ATAPI command block */ 376 struct atapi_sense sense; /* ATAPI request sense data */ 377 u_int8_t saved_cmd; /* ATAPI saved command */ 378 } atapi; 379 } u; 380 u_int32_t bytecount; /* bytes to transfer */ 381 u_int32_t transfersize; /* bytes pr transfer */ 382 caddr_t data; /* pointer to data buf */ 383 u_int32_t tag; /* HW tag of this request */ 384 int flags; 385#define ATA_R_CONTROL 0x00000001 386#define ATA_R_READ 0x00000002 387#define ATA_R_WRITE 0x00000004 388#define ATA_R_ATAPI 0x00000008 389#define ATA_R_DMA 0x00000010 390#define ATA_R_QUIET 0x00000020 391#define ATA_R_TIMEOUT 0x00000040 392#define ATA_R_48BIT 0x00000080 393 394#define ATA_R_ORDERED 0x00000100 395#define ATA_R_AT_HEAD 0x00000200 396#define ATA_R_REQUEUE 0x00000400 397#define ATA_R_THREAD 0x00000800 398#define ATA_R_DIRECT 0x00001000 399#define ATA_R_NEEDRESULT 0x00002000 400#define ATA_R_DATA_IN_CCB 0x00004000 401 402#define ATA_R_ATAPI16 0x00010000 403#define ATA_R_ATAPI_INTR 0x00020000 404 405#define ATA_R_DEBUG 0x10000000 406#define ATA_R_DANGER1 0x20000000 407#define ATA_R_DANGER2 0x40000000 408 409 struct ata_dmaslot *dma; /* DMA slot of this request */ 410 u_int8_t status; /* ATA status */ 411 u_int8_t error; /* ATA error */ 412 u_int32_t donecount; /* bytes transferred */ 413 int result; /* result error code */ 414 void (*callback)(struct ata_request *request); 415 struct sema done; /* request done sema */ 416 int retries; /* retry count */ 417 int timeout; /* timeout for this cmd */ 418 struct callout callout; /* callout management */ 419 struct task task; /* task management */ 420 struct bio *bio; /* bio for this request */ 421 int this; /* this request ID */ 422 struct ata_composite *composite; /* for composite atomic ops */ 423 void *driver; /* driver specific */ 424 TAILQ_ENTRY(ata_request) chain; /* list management */ 425 union ccb *ccb; 426}; 427 428/* define this for debugging request processing */ 429#if 0 430#define ATA_DEBUG_RQ(request, string) \ 431 { \ 432 if (request->flags & ATA_R_DEBUG) \ 433 device_printf(request->parent, "req=%p %s " string "\n", \ 434 request, ata_cmd2str(request)); \ 435 } 436#else 437#define ATA_DEBUG_RQ(request, string) 438#endif 439 440 441/* structure describing an ATA/ATAPI device */ 442struct ata_device { 443 device_t dev; /* device handle */ 444 int unit; /* physical unit */ 445#define ATA_MASTER 0x00 446#define ATA_SLAVE 0x01 447#define ATA_PM 0x0f 448 449 struct ata_params param; /* ata param structure */ 450 int mode; /* current transfermode */ 451 u_int32_t max_iosize; /* max IO size */ 452 int spindown; /* idle spindown timeout */ 453 struct callout spindown_timer; 454 int spindown_state; 455 int flags; 456#define ATA_D_USE_CHS 0x0001 457#define ATA_D_MEDIA_CHANGED 0x0002 458#define ATA_D_ENC_PRESENT 0x0004 459}; 460 461/* structure for holding DMA Physical Region Descriptors (PRD) entries */ 462struct ata_dma_prdentry { 463 u_int32_t addr; 464 u_int32_t count; 465}; 466 467/* structure used by the setprd function */ 468struct ata_dmasetprd_args { 469 void *dmatab; 470 int nsegs; 471 int error; 472}; 473 474struct ata_dmaslot { 475 u_int8_t status; /* DMA status */ 476 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 477 bus_dmamap_t sg_map; /* SG list DMA map */ 478 void *sg; /* DMA transfer table */ 479 bus_addr_t sg_bus; /* bus address of dmatab */ 480 bus_dma_tag_t data_tag; /* data DMA tag */ 481 bus_dmamap_t data_map; /* data DMA map */ 482}; 483 484/* structure holding DMA related information */ 485struct ata_dma { 486 bus_dma_tag_t dmatag; /* parent DMA tag */ 487 bus_dma_tag_t work_tag; /* workspace DMA tag */ 488 bus_dmamap_t work_map; /* workspace DMA map */ 489 u_int8_t *work; /* workspace */ 490 bus_addr_t work_bus; /* bus address of dmatab */ 491 492#define ATA_DMA_SLOTS 1 493 int dma_slots; /* DMA slots allocated */ 494 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 495 u_int32_t alignment; /* DMA SG list alignment */ 496 u_int32_t boundary; /* DMA SG list boundary */ 497 u_int32_t segsize; /* DMA SG list segment size */ 498 u_int32_t max_iosize; /* DMA data max IO size */ 499 u_int64_t max_address; /* highest DMA'able address */ 500 int flags; 501#define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 502 503 void (*alloc)(device_t dev); 504 void (*free)(device_t dev); 505 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 506 int (*load)(struct ata_request *request, void *addr, int *nsegs); 507 int (*unload)(struct ata_request *request); 508 int (*start)(struct ata_request *request); 509 int (*stop)(struct ata_request *request); 510 void (*reset)(device_t dev); 511}; 512 513/* structure holding lowlevel functions */ 514struct ata_lowlevel { 515 u_int32_t (*softreset)(device_t dev, int pmport); 516 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 517 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 518 int (*status)(device_t dev); 519 int (*begin_transaction)(struct ata_request *request); 520 int (*end_transaction)(struct ata_request *request); 521 int (*command)(struct ata_request *request); 522 void (*tf_read)(struct ata_request *request); 523 void (*tf_write)(struct ata_request *request); 524}; 525 526/* structure holding resources for an ATA channel */ 527struct ata_resource { 528 struct resource *res; 529 int offset; 530}; 531 532struct ata_cam_device { 533 u_int revision; 534 int mode; 535 u_int bytecount; 536 u_int atapi; 537 u_int caps; 538}; 539 540/* structure describing an ATA channel */ 541struct ata_channel { 542 device_t dev; /* device handle */ 543 int unit; /* physical channel */ 544 int attached; /* channel is attached */ 545 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 546 struct resource *r_irq; /* interrupt of this channel */ 547 void *ih; /* interrupt handle */ 548 struct ata_lowlevel hw; /* lowlevel HW functions */ 549 struct ata_dma dma; /* DMA data / functions */ 550 int flags; /* channel flags */ 551#define ATA_NO_SLAVE 0x01 552#define ATA_USE_16BIT 0x02 553#define ATA_ATAPI_DMA_RO 0x04 554#define ATA_NO_48BIT_DMA 0x08 555#define ATA_ALWAYS_DMASTAT 0x10 556#define ATA_CHECKS_CABLE 0x20 557#define ATA_NO_ATAPI_DMA 0x40 558#define ATA_SATA 0x80 559#define ATA_DMA_BEFORE_CMD 0x100 560#define ATA_KNOWN_PRESENCE 0x200 561#define ATA_STATUS_IS_LONG 0x400 562#define ATA_PERIODIC_POLL 0x800 563 564 int pm_level; /* power management level */ 565 int devices; /* what is present */ 566#define ATA_ATA_MASTER 0x00000001 567#define ATA_ATA_SLAVE 0x00000002 568#define ATA_PORTMULTIPLIER 0x00008000 569#define ATA_ATAPI_MASTER 0x00010000 570#define ATA_ATAPI_SLAVE 0x00020000 571 572 struct mtx state_mtx; /* state lock */ 573 int state; /* ATA channel state */ 574#define ATA_IDLE 0x0000 575#define ATA_ACTIVE 0x0001 576#define ATA_STALL_QUEUE 0x0002 577 578 struct ata_request *running; /* currently running request */ 579 struct task conntask; /* PHY events handling task */ 580 struct cam_sim *sim; 581 struct cam_path *path; 582 struct ata_cam_device user[16]; /* User-specified settings */ 583 struct ata_cam_device curr[16]; /* Current settings */ 584 int requestsense; /* CCB waiting for SENSE. */ 585 struct callout poll_callout; /* Periodic status poll. */ 586}; 587 588/* disk bay/enclosure related */ 589#define ATA_LED_OFF 0x00 590#define ATA_LED_RED 0x01 591#define ATA_LED_GREEN 0x02 592#define ATA_LED_ORANGE 0x03 593#define ATA_LED_MASK 0x03 594 595/* externs */ 596extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 597extern struct intr_config_hook *ata_delayed_attach; 598extern devclass_t ata_devclass; 599extern int ata_wc; 600extern int ata_setmax; 601extern int ata_dma_check_80pin; 602 603/* public prototypes */ 604/* ata-all.c: */ 605int ata_probe(device_t dev); 606int ata_attach(device_t dev); 607int ata_detach(device_t dev); 608int ata_reinit(device_t dev); 609int ata_suspend(device_t dev); 610int ata_resume(device_t dev); 611void ata_interrupt(void *data); 612int ata_getparam(struct ata_device *atadev, int init); 613void ata_default_registers(device_t dev); 614void ata_udelay(int interval); 615const char *ata_cmd2str(struct ata_request *request); 616const char *ata_mode2str(int mode); 617void ata_setmode(device_t dev); 618void ata_print_cable(device_t dev, u_int8_t *who); 619int ata_atapi(device_t dev, int target); 620void ata_timeout(struct ata_request *); 621 622/* ata-lowlevel.c: */ 623void ata_generic_hw(device_t dev); 624int ata_begin_transaction(struct ata_request *); 625int ata_end_transaction(struct ata_request *); 626void ata_generic_reset(device_t dev); 627int ata_generic_command(struct ata_request *request); 628 629/* ata-dma.c: */ 630void ata_dmainit(device_t); 631void ata_dmafini(device_t dev); 632 633/* ata-sata.c: */ 634void ata_sata_phy_check_events(device_t dev, int port); 635int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 636int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 637int ata_sata_phy_reset(device_t dev, int port, int quick); 638int ata_sata_setmode(device_t dev, int target, int mode); 639int ata_sata_getrev(device_t dev, int target); 640int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 641void ata_pm_identify(device_t dev); 642 643/* macros for alloc/free of struct ata_request */ 644extern uma_zone_t ata_request_zone; 645#define ata_alloc_request() uma_zalloc(ata_request_zone, M_NOWAIT | M_ZERO) 646#define ata_free_request(request) { \ 647 if (!(request->flags & ATA_R_DANGER2)) \ 648 uma_zfree(ata_request_zone, request); \ 649 } 650 651MALLOC_DECLARE(M_ATA); 652 653/* misc newbus defines */ 654#define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 655 656/* macros to hide busspace uglyness */ 657#define ATA_INB(res, offset) \ 658 bus_read_1((res), (offset)) 659 660#define ATA_INW(res, offset) \ 661 bus_read_2((res), (offset)) 662#define ATA_INW_STRM(res, offset) \ 663 bus_read_stream_2((res), (offset)) 664#define ATA_INL(res, offset) \ 665 bus_read_4((res), (offset)) 666#define ATA_INSW(res, offset, addr, count) \ 667 bus_read_multi_2((res), (offset), (addr), (count)) 668#define ATA_INSW_STRM(res, offset, addr, count) \ 669 bus_read_multi_stream_2((res), (offset), (addr), (count)) 670#define ATA_INSL(res, offset, addr, count) \ 671 bus_read_multi_4((res), (offset), (addr), (count)) 672#define ATA_INSL_STRM(res, offset, addr, count) \ 673 bus_read_multi_stream_4((res), (offset), (addr), (count)) 674#define ATA_OUTB(res, offset, value) \ 675 bus_write_1((res), (offset), (value)) 676#define ATA_OUTW(res, offset, value) \ 677 bus_write_2((res), (offset), (value)) 678#define ATA_OUTW_STRM(res, offset, value) \ 679 bus_write_stream_2((res), (offset), (value)) 680#define ATA_OUTL(res, offset, value) \ 681 bus_write_4((res), (offset), (value)) 682#define ATA_OUTSW(res, offset, addr, count) \ 683 bus_write_multi_2((res), (offset), (addr), (count)) 684#define ATA_OUTSW_STRM(res, offset, addr, count) \ 685 bus_write_multi_stream_2((res), (offset), (addr), (count)) 686#define ATA_OUTSL(res, offset, addr, count) \ 687 bus_write_multi_4((res), (offset), (addr), (count)) 688#define ATA_OUTSL_STRM(res, offset, addr, count) \ 689 bus_write_multi_stream_4((res), (offset), (addr), (count)) 690 691#define ATA_IDX_INB(ch, idx) \ 692 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 693 694#define ATA_IDX_INW(ch, idx) \ 695 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 696 697#define ATA_IDX_INW_STRM(ch, idx) \ 698 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset) 699 700#define ATA_IDX_INL(ch, idx) \ 701 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 702 703#define ATA_IDX_INSW(ch, idx, addr, count) \ 704 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 705 706#define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 707 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 708 709#define ATA_IDX_INSL(ch, idx, addr, count) \ 710 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 711 712#define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 713 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 714 715#define ATA_IDX_OUTB(ch, idx, value) \ 716 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 717 718#define ATA_IDX_OUTW(ch, idx, value) \ 719 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 720 721#define ATA_IDX_OUTW_STRM(ch, idx, value) \ 722 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value) 723 724#define ATA_IDX_OUTL(ch, idx, value) \ 725 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 726 727#define ATA_IDX_OUTSW(ch, idx, addr, count) \ 728 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 729 730#define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 731 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 732 733#define ATA_IDX_OUTSL(ch, idx, addr, count) \ 734 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 735 736#define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 737 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 738