1/*- 2 * Copyright (c) 2012 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: releng/10.2/sys/boot/fdt/dts/arm/zedboard.dts 273645 2014-10-25 20:34:10Z ian $ 27 */ 28 29/dts-v1/; 30 31/ { 32 model = "zedboard"; 33 compatible = "digilent,zedboard"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 interrupt-parent = <&GIC>; 37 38 // cpus { 39 // #address-cells = <1>; 40 // #size-cells = <0>; 41 // cpu@0 { 42 // device-type = "cpu"; 43 // model = "ARM Cortex-A9"; 44 // }; 45 // }; 46 47 memory { 48 // First megabyte isn't accessible by all interconnect masters. 49 device_type = "memory"; 50 reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */ 51 }; 52 53 // Zynq PS System registers. 54 // 55 ps7sys@f8000000 { 56 device_type = "soc"; 57 compatible = "simple-bus"; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges = <0x0 0xf8000000 0xf10000>; 61 62 // SLCR block 63 slcr: slcr@7000 { 64 compatible = "xlnx,zy7_slcr"; 65 reg = <0x0 0x1000>; 66 clock-frequency = <33333333>; // 33Mhz PS_CLK 67 }; 68 69 // Interrupt controller 70 GIC: gic { 71 compatible = "arm,gic"; 72 interrupt-controller; 73 #address-cells = <0>; 74 #interrupt-cells = <1>; 75 reg = <0xf01000 0x1000>, // distributer registers 76 <0xf00100 0x0100>; // CPU if registers 77 }; 78 79 // L2 cache controller 80 pl310@f02000 { 81 compatible = "arm,pl310"; 82 reg = <0xf02000 0x1000>; 83 interrupts = <34>; 84 interrupt-parent = <&GIC>; 85 }; 86 87 // Device Config 88 devcfg: devcfg@7000 { 89 compatible = "xlnx,zy7_devcfg"; 90 reg = <0x7000 0x1000>; 91 interrupts = <40>; 92 interrupt-parent = <&GIC>; 93 }; 94 95 // triple timer counters0,1 96 ttc0: ttc@1000 { 97 compatible = "xlnx,ttc"; 98 reg = <0x1000 0x1000>; 99 }; 100 ttc1: ttc@2000 { 101 compatible = "xlnx,ttc"; 102 reg = <0x2000 0x1000>; 103 }; 104 105 // ARM Cortex A9 TWD Timer 106 timer@f00600 { 107 compatible = "arm,mpcore-timers"; 108 clock-frequency = <333333333>; // 333Mhz 109 #address-cells = <1>; 110 #size-cells = <0>; 111 reg = <0xf00200 0x100>, // Global Timer Regs 112 <0xf00600 0x20>; // Private Timer Regs 113 interrupts = < 27 29 >; 114 interrupt-parent = <&GIC>; 115 }; 116 117 // system watch-dog timer 118 swdt@5000 { 119 device_type = "watchdog"; 120 compatible = "xlnx,zy7_wdt"; 121 reg = <0x5000 0x1000>; 122 interrupts = <41>; 123 interrupt-parent = <&GIC>; 124 }; 125 126 scuwdt@f00620 { 127 device_type = "watchdog"; 128 compatible = "arm,mpcore_wdt"; 129 reg = <0xf00620 0x20>; 130 interrupts = <30>; 131 interrupt-parent = <&GIC>; 132 reset = <1>; 133 }; 134 }; // pssys@f8000000 135 136 // Zynq PS I/O Peripheral registers. 137 // 138 ps7io@e0000000 { 139 device_type = "soc"; 140 compatible = "simple-bus"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0x0 0xe0000000 0x300000>; 144 145 // uart0: uart@0000 { 146 // device_type = "serial"; 147 // compatible = "cadence,uart"; 148 // reg = <0x0000 0x1000>; 149 // interrupts = <59>; 150 // interrupt-parent = <&GIC>; 151 // clock-frequency = <50000000>; 152 // }; 153 154 uart1: uart@1000 { 155 device_type = "serial"; 156 compatible = "cadence,uart"; 157 reg = <0x1000 0x1000>; 158 interrupts = <82>; 159 interrupt-parent = <&GIC>; 160 clock-frequency = <50000000>; 161 current-speed = <115200>; 162 }; 163 164 gpio: gpio@a000 { 165 compatible = "xlnx,zy7_gpio"; 166 reg = <0xa000 0x1000>; 167 interrupts = <52>; 168 interrupt-parent = <&GIC>; 169 }; 170 171 // GigE 172 eth0: eth@b000 { 173 // device_type = "network"; 174 175 compatible = "cadence,gem"; 176 reg = <0xb000 0x1000>; 177 interrupts = <54 55>; 178 interrupt-parent = <&GIC>; 179 ref-clock-num = <0>; 180 }; 181 182 // SDIO 183 sdhci0: sdhci@100000 { 184 compatible = "xlnx,zy7_sdhci"; 185 reg = <0x100000 0x1000>; 186 interrupts = <56>; 187 interrupt-parent = <&GIC>; 188 max-frequency = <50000000>; 189 }; 190 191 // QSPI 192 qspi0: qspi@d000 { 193 compatible = "xlnx,zy7_qspi"; 194 reg = <0xd000 0x1000>; 195 interrupts = <51>; 196 interrupt-parent = <&GIC>; 197 spi-clock = <50000000>; 198 ref-clock = <190476000>; 199 }; 200 201 // USB 202 ehci0: ehci@2000 { 203 compatible = "xlnx,zy7_ehci"; 204 reg = <0x2000 0x1000>; 205 interrupts = <53>; 206 interrupt-parent = <&GIC>; 207 phy_vbus_ext; 208 }; 209 210 }; // ps7io@e0000000 211 212 chosen { 213 stdin = &uart1; 214 stdout = &uart1; 215 }; 216}; 217 218