fpu_explode.c revision 91174
191174Stmm/* 291174Stmm * Copyright (c) 1992, 1993 391174Stmm * The Regents of the University of California. All rights reserved. 491174Stmm * 591174Stmm * This software was developed by the Computer Systems Engineering group 691174Stmm * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 791174Stmm * contributed to Berkeley. 891174Stmm * 991174Stmm * All advertising materials mentioning features or use of this software 1091174Stmm * must display the following acknowledgement: 1191174Stmm * This product includes software developed by the University of 1291174Stmm * California, Lawrence Berkeley Laboratory. 1391174Stmm * 1491174Stmm * Redistribution and use in source and binary forms, with or without 1591174Stmm * modification, are permitted provided that the following conditions 1691174Stmm * are met: 1791174Stmm * 1. Redistributions of source code must retain the above copyright 1891174Stmm * notice, this list of conditions and the following disclaimer. 1991174Stmm * 2. Redistributions in binary form must reproduce the above copyright 2091174Stmm * notice, this list of conditions and the following disclaimer in the 2191174Stmm * documentation and/or other materials provided with the distribution. 2291174Stmm * 3. All advertising materials mentioning features or use of this software 2391174Stmm * must display the following acknowledgement: 2491174Stmm * This product includes software developed by the University of 2591174Stmm * California, Berkeley and its contributors. 2691174Stmm * 4. Neither the name of the University nor the names of its contributors 2791174Stmm * may be used to endorse or promote products derived from this software 2891174Stmm * without specific prior written permission. 2991174Stmm * 3091174Stmm * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 3191174Stmm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 3291174Stmm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 3391174Stmm * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 3491174Stmm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 3591174Stmm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 3691174Stmm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3791174Stmm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3891174Stmm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3991174Stmm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 4091174Stmm * SUCH DAMAGE. 4191174Stmm * 4291174Stmm * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 4391174Stmm * from: NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp 4491174Stmm * 4591174Stmm * $FreeBSD: head/lib/libc/sparc64/fpu/fpu_explode.c 91174 2002-02-23 21:37:18Z tmm $ 4691174Stmm */ 4791174Stmm 4891174Stmm/* 4991174Stmm * FPU subroutines: `explode' the machine's `packed binary' format numbers 5091174Stmm * into our internal format. 5191174Stmm */ 5291174Stmm 5391174Stmm#include <sys/param.h> 5491174Stmm 5591174Stmm#include <machine/frame.h> 5691174Stmm#include <machine/fp.h> 5791174Stmm#include <machine/fsr.h> 5891174Stmm#include <machine/ieee.h> 5991174Stmm#include <machine/instr.h> 6091174Stmm 6191174Stmm#include "fpu_arith.h" 6291174Stmm#include "fpu_emu.h" 6391174Stmm#include "fpu_extern.h" 6491174Stmm 6591174Stmm/* 6691174Stmm * N.B.: in all of the following, we assume the FP format is 6791174Stmm * 6891174Stmm * --------------------------- 6991174Stmm * | s | exponent | fraction | 7091174Stmm * --------------------------- 7191174Stmm * 7291174Stmm * (which represents -1**s * 1.fraction * 2**exponent), so that the 7391174Stmm * sign bit is way at the top (bit 31), the exponent is next, and 7491174Stmm * then the remaining bits mark the fraction. A zero exponent means 7591174Stmm * zero or denormalized (0.fraction rather than 1.fraction), and the 7691174Stmm * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 7791174Stmm * 7891174Stmm * Since the sign bit is always the topmost bit---this holds even for 7991174Stmm * integers---we set that outside all the *tof functions. Each function 8091174Stmm * returns the class code for the new number (but note that we use 8191174Stmm * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 8291174Stmm */ 8391174Stmm 8491174Stmm/* 8591174Stmm * int -> fpn. 8691174Stmm */ 8791174Stmmint 8891174Stmm__fpu_itof(fp, i) 8991174Stmm register struct fpn *fp; 9091174Stmm register u_int i; 9191174Stmm{ 9291174Stmm 9391174Stmm if (i == 0) 9491174Stmm return (FPC_ZERO); 9591174Stmm /* 9691174Stmm * The value FP_1 represents 2^FP_LG, so set the exponent 9791174Stmm * there and let normalization fix it up. Convert negative 9891174Stmm * numbers to sign-and-magnitude. Note that this relies on 9991174Stmm * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 10091174Stmm */ 10191174Stmm fp->fp_exp = FP_LG; 10291174Stmm fp->fp_mant[0] = (int)i < 0 ? -i : i; 10391174Stmm fp->fp_mant[1] = 0; 10491174Stmm fp->fp_mant[2] = 0; 10591174Stmm fp->fp_mant[3] = 0; 10691174Stmm __fpu_norm(fp); 10791174Stmm return (FPC_NUM); 10891174Stmm} 10991174Stmm 11091174Stmm/* 11191174Stmm * 64-bit int -> fpn. 11291174Stmm */ 11391174Stmmint 11491174Stmm__fpu_xtof(fp, i) 11591174Stmm register struct fpn *fp; 11691174Stmm register u_int64_t i; 11791174Stmm{ 11891174Stmm 11991174Stmm if (i == 0) 12091174Stmm return (FPC_ZERO); 12191174Stmm /* 12291174Stmm * The value FP_1 represents 2^FP_LG, so set the exponent 12391174Stmm * there and let normalization fix it up. Convert negative 12491174Stmm * numbers to sign-and-magnitude. Note that this relies on 12591174Stmm * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 12691174Stmm */ 12791174Stmm fp->fp_exp = FP_LG2; 12891174Stmm *((int64_t*)fp->fp_mant) = (int64_t)i < 0 ? -i : i; 12991174Stmm fp->fp_mant[2] = 0; 13091174Stmm fp->fp_mant[3] = 0; 13191174Stmm __fpu_norm(fp); 13291174Stmm return (FPC_NUM); 13391174Stmm} 13491174Stmm 13591174Stmm#define mask(nbits) ((1L << (nbits)) - 1) 13691174Stmm 13791174Stmm/* 13891174Stmm * All external floating formats convert to internal in the same manner, 13991174Stmm * as defined here. Note that only normals get an implied 1.0 inserted. 14091174Stmm */ 14191174Stmm#define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 14291174Stmm if (exp == 0) { \ 14391174Stmm if (allfrac == 0) \ 14491174Stmm return (FPC_ZERO); \ 14591174Stmm fp->fp_exp = 1 - expbias; \ 14691174Stmm fp->fp_mant[0] = f0; \ 14791174Stmm fp->fp_mant[1] = f1; \ 14891174Stmm fp->fp_mant[2] = f2; \ 14991174Stmm fp->fp_mant[3] = f3; \ 15091174Stmm __fpu_norm(fp); \ 15191174Stmm return (FPC_NUM); \ 15291174Stmm } \ 15391174Stmm if (exp == (2 * expbias + 1)) { \ 15491174Stmm if (allfrac == 0) \ 15591174Stmm return (FPC_INF); \ 15691174Stmm fp->fp_mant[0] = f0; \ 15791174Stmm fp->fp_mant[1] = f1; \ 15891174Stmm fp->fp_mant[2] = f2; \ 15991174Stmm fp->fp_mant[3] = f3; \ 16091174Stmm return (FPC_QNAN); \ 16191174Stmm } \ 16291174Stmm fp->fp_exp = exp - expbias; \ 16391174Stmm fp->fp_mant[0] = FP_1 | f0; \ 16491174Stmm fp->fp_mant[1] = f1; \ 16591174Stmm fp->fp_mant[2] = f2; \ 16691174Stmm fp->fp_mant[3] = f3; \ 16791174Stmm return (FPC_NUM) 16891174Stmm 16991174Stmm/* 17091174Stmm * 32-bit single precision -> fpn. 17191174Stmm * We assume a single occupies at most (64-FP_LG) bits in the internal 17291174Stmm * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 17391174Stmm */ 17491174Stmmint 17591174Stmm__fpu_stof(fp, i) 17691174Stmm register struct fpn *fp; 17791174Stmm register u_int i; 17891174Stmm{ 17991174Stmm register int exp; 18091174Stmm register u_int frac, f0, f1; 18191174Stmm#define SNG_SHIFT (SNG_FRACBITS - FP_LG) 18291174Stmm 18391174Stmm exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 18491174Stmm frac = i & mask(SNG_FRACBITS); 18591174Stmm f0 = frac >> SNG_SHIFT; 18691174Stmm f1 = frac << (32 - SNG_SHIFT); 18791174Stmm FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 18891174Stmm} 18991174Stmm 19091174Stmm/* 19191174Stmm * 64-bit double -> fpn. 19291174Stmm * We assume this uses at most (96-FP_LG) bits. 19391174Stmm */ 19491174Stmmint 19591174Stmm__fpu_dtof(fp, i, j) 19691174Stmm register struct fpn *fp; 19791174Stmm register u_int i, j; 19891174Stmm{ 19991174Stmm register int exp; 20091174Stmm register u_int frac, f0, f1, f2; 20191174Stmm#define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 20291174Stmm 20391174Stmm exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 20491174Stmm frac = i & mask(DBL_FRACBITS - 32); 20591174Stmm f0 = frac >> DBL_SHIFT; 20691174Stmm f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 20791174Stmm f2 = j << (32 - DBL_SHIFT); 20891174Stmm frac |= j; 20991174Stmm FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 21091174Stmm} 21191174Stmm 21291174Stmm/* 21391174Stmm * 128-bit extended -> fpn. 21491174Stmm */ 21591174Stmmint 21691174Stmm__fpu_qtof(fp, i, j, k, l) 21791174Stmm register struct fpn *fp; 21891174Stmm register u_int i, j, k, l; 21991174Stmm{ 22091174Stmm register int exp; 22191174Stmm register u_int frac, f0, f1, f2, f3; 22291174Stmm#define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 22391174Stmm 22491174Stmm /* 22591174Stmm * Note that ext and fpn `line up', hence no shifting needed. 22691174Stmm */ 22791174Stmm exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 22891174Stmm frac = i & mask(EXT_FRACBITS - 3 * 32); 22991174Stmm f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 23091174Stmm f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 23191174Stmm f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 23291174Stmm f3 = l << EXT_SHIFT; 23391174Stmm frac |= j | k | l; 23491174Stmm FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 23591174Stmm} 23691174Stmm 23791174Stmm/* 23891174Stmm * Explode the contents of a register / regpair / regquad. 23991174Stmm * If the input is a signalling NaN, an NV (invalid) exception 24091174Stmm * will be set. (Note that nothing but NV can occur until ALU 24191174Stmm * operations are performed.) 24291174Stmm */ 24391174Stmmvoid 24491174Stmm__fpu_explode(fe, fp, type, reg) 24591174Stmm struct fpemu *fe; 24691174Stmm struct fpn *fp; 24791174Stmm int type, reg; 24891174Stmm{ 24991174Stmm u_int s; 25091174Stmm u_int64_t l; 25191174Stmm 25291174Stmm l = __fpu_getreg64(reg & ~1); 25391174Stmm s = __fpu_getreg(reg); 25491174Stmm fp->fp_sign = s >> 31; 25591174Stmm fp->fp_sticky = 0; 25691174Stmm switch (type) { 25791174Stmm case FTYPE_LNG: 25891174Stmm s = __fpu_xtof(fp, l); 25991174Stmm break; 26091174Stmm 26191174Stmm case FTYPE_INT: 26291174Stmm s = __fpu_itof(fp, s); 26391174Stmm break; 26491174Stmm 26591174Stmm case FTYPE_SNG: 26691174Stmm s = __fpu_stof(fp, s); 26791174Stmm break; 26891174Stmm 26991174Stmm case FTYPE_DBL: 27091174Stmm s = __fpu_dtof(fp, s, __fpu_getreg(reg + 1)); 27191174Stmm break; 27291174Stmm 27391174Stmm case FTYPE_EXT: 27491174Stmm s = __fpu_qtof(fp, s, __fpu_getreg(reg + 1), 27591174Stmm __fpu_getreg(reg + 2), 27691174Stmm __fpu_getreg(reg + 3)); 27791174Stmm break; 27891174Stmm 27991174Stmm default: 28091174Stmm __fpu_panic("fpu_explode"); 28191174Stmm } 28291174Stmm 28391174Stmm if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 28491174Stmm /* 28591174Stmm * Input is a signalling NaN. All operations that return 28691174Stmm * an input NaN operand put it through a ``NaN conversion'', 28791174Stmm * which basically just means ``turn on the quiet bit''. 28891174Stmm * We do this here so that all NaNs internally look quiet 28991174Stmm * (we can tell signalling ones by their class). 29091174Stmm */ 29191174Stmm fp->fp_mant[0] |= FP_QUIETBIT; 29291174Stmm fe->fe_cx = FSR_NV; /* assert invalid operand */ 29391174Stmm s = FPC_SNAN; 29491174Stmm } 29591174Stmm fp->fp_class = s; 29691174Stmm DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 29791174Stmm ((type == FTYPE_INT) ? 'i' : 29891174Stmm ((type == FTYPE_SNG) ? 's' : 29991174Stmm ((type == FTYPE_DBL) ? 'd' : 30091174Stmm ((type == FTYPE_EXT) ? 'q' : '?')))), 30191174Stmm reg)); 30291174Stmm DUMPFPN(FPE_REG, fp); 30391174Stmm DPRINTF(FPE_REG, ("\n")); 30491174Stmm} 305