1263320SdimPull in r200963 from upstream llvm trunk (by Venkatraman Govindaraju): 2263320Sdim 3263320Sdim [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding. 4263320Sdim 5269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 6263320Sdim 7263320SdimIndex: test/MC/Sparc/sparc-atomic-instructions.s 8263320Sdim=================================================================== 9263320Sdim--- test/MC/Sparc/sparc-atomic-instructions.s 10263320Sdim+++ test/MC/Sparc/sparc-atomic-instructions.s 11263320Sdim@@ -0,0 +1,19 @@ 12263320Sdim+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s 13263320Sdim+ 14263320Sdim+ ! CHECK: membar 15 ! encoding: [0x81,0x43,0xe0,0x0f] 15263320Sdim+ membar 15 16263320Sdim+ 17263320Sdim+ ! CHECK: stbar ! encoding: [0x81,0x43,0xc0,0x00] 18263320Sdim+ stbar 19263320Sdim+ 20263320Sdim+ ! CHECK: swap [%i0+%l6], %o2 ! encoding: [0xd4,0x7e,0x00,0x16] 21263320Sdim+ swap [%i0+%l6], %o2 22263320Sdim+ 23263320Sdim+ ! CHECK: swap [%i0+32], %o2 ! encoding: [0xd4,0x7e,0x20,0x20] 24263320Sdim+ swap [%i0+32], %o2 25263320Sdim+ 26263320Sdim+ ! CHECK: cas [%i0], %l6, %o2 ! encoding: [0xd5,0xe6,0x10,0x16] 27263320Sdim+ cas [%i0], %l6, %o2 28263320Sdim+ 29263320Sdim+ ! CHECK: casx [%i0], %l6, %o2 ! encoding: [0xd5,0xf6,0x10,0x16] 30263320Sdim+ casx [%i0], %l6, %o2 31263320SdimIndex: lib/Target/Sparc/SparcInstrInfo.td 32263320Sdim=================================================================== 33263320Sdim--- lib/Target/Sparc/SparcInstrInfo.td 34263320Sdim+++ lib/Target/Sparc/SparcInstrInfo.td 35263320Sdim@@ -935,19 +935,19 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 36263320Sdim def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13), 37263320Sdim "membar $simm13", []>; 38263320Sdim 39263320Sdim-let Constraints = "$val = $rd" in { 40263320Sdim+let Constraints = "$val = $dst" in { 41263320Sdim def SWAPrr : F3_1<3, 0b001111, 42263320Sdim- (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr), 43263320Sdim- "swap [$addr], $rd", 44263320Sdim- [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>; 45263320Sdim+ (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val), 46263320Sdim+ "swap [$addr], $dst", 47263320Sdim+ [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>; 48263320Sdim def SWAPri : F3_2<3, 0b001111, 49263320Sdim- (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr), 50263320Sdim- "swap [$addr], $rd", 51263320Sdim- [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; 52263320Sdim+ (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val), 53263320Sdim+ "swap [$addr], $dst", 54263320Sdim+ [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; 55263320Sdim } 56263320Sdim 57263320Sdim let Predicates = [HasV9], Constraints = "$swap = $rd" in 58263320Sdim- def CASrr: F3_1<3, 0b111100, 59263320Sdim+ def CASrr: F3_1_asi<3, 0b111100, 0b10000000, 60263320Sdim (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 61263320Sdim IntRegs:$swap), 62263320Sdim "cas [$rs1], $rs2, $rd", 63263320SdimIndex: lib/Target/Sparc/SparcInstrFormats.td 64263320Sdim=================================================================== 65263320Sdim--- lib/Target/Sparc/SparcInstrFormats.td 66263320Sdim+++ lib/Target/Sparc/SparcInstrFormats.td 67263320Sdim@@ -100,9 +100,8 @@ class F3<dag outs, dag ins, string asmstr, list<da 68263320Sdim 69263320Sdim // Specific F3 classes: SparcV8 manual, page 44 70263320Sdim // 71263320Sdim-class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 72263320Sdim+class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins, 73263320Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 74263320Sdim- bits<8> asi = 0; // asi not currently used 75263320Sdim bits<5> rs2; 76263320Sdim 77263320Sdim let op = opVal; 78263320Sdim@@ -113,6 +112,10 @@ class F3<dag outs, dag ins, string asmstr, list<da 79263320Sdim let Inst{4-0} = rs2; 80263320Sdim } 81263320Sdim 82263320Sdim+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 83263320Sdim+ list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins, 84263320Sdim+ asmstr, pattern>; 85263320Sdim+ 86263320Sdim class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 87263320Sdim string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { 88263320Sdim bits<13> simm13; 89263320SdimIndex: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 90263320Sdim=================================================================== 91263320Sdim--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 92263320Sdim+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 93263320Sdim@@ -546,7 +546,24 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*> 94263320Sdim Parser.getTok().getLoc())); 95263320Sdim Parser.Lex(); // Eat the [ 96263320Sdim 97263320Sdim- ResTy = parseMEMOperand(Operands); 98263320Sdim+ if (Mnemonic == "cas" || Mnemonic == "casx") { 99263320Sdim+ SMLoc S = Parser.getTok().getLoc(); 100263320Sdim+ if (getLexer().getKind() != AsmToken::Percent) 101263320Sdim+ return MatchOperand_NoMatch; 102263320Sdim+ Parser.Lex(); // eat % 103263320Sdim+ 104263320Sdim+ unsigned RegNo, RegKind; 105263320Sdim+ if (!matchRegisterName(Parser.getTok(), RegNo, RegKind)) 106263320Sdim+ return MatchOperand_NoMatch; 107263320Sdim+ 108263320Sdim+ Parser.Lex(); // Eat the identifier token. 109263320Sdim+ SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1); 110263320Sdim+ Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); 111263320Sdim+ ResTy = MatchOperand_Success; 112263320Sdim+ } else { 113263320Sdim+ ResTy = parseMEMOperand(Operands); 114263320Sdim+ } 115263320Sdim+ 116263320Sdim if (ResTy != MatchOperand_Success) 117263320Sdim return ResTy; 118263320Sdim 119263320SdimIndex: lib/Target/Sparc/SparcInstr64Bit.td 120263320Sdim=================================================================== 121263320Sdim--- lib/Target/Sparc/SparcInstr64Bit.td 122263320Sdim+++ lib/Target/Sparc/SparcInstr64Bit.td 123263320Sdim@@ -415,7 +415,7 @@ def SETHIXi : F2_1<0b100, 124263320Sdim 125263320Sdim // ATOMICS. 126263320Sdim let Predicates = [Is64Bit], Constraints = "$swap = $rd" in { 127263320Sdim- def CASXrr: F3_1<3, 0b111110, 128263320Sdim+ def CASXrr: F3_1_asi<3, 0b111110, 0b10000000, 129263320Sdim (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 130263320Sdim I64Regs:$swap), 131263320Sdim "casx [$rs1], $rs2, $rd", 132