1Pull in r200963 from upstream llvm trunk (by Venkatraman Govindaraju):
2
3  [Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.
4
5Introduced here: http://svnweb.freebsd.org/changeset/base/262261
6
7Index: test/MC/Sparc/sparc-atomic-instructions.s
8===================================================================
9--- test/MC/Sparc/sparc-atomic-instructions.s
10+++ test/MC/Sparc/sparc-atomic-instructions.s
11@@ -0,0 +1,19 @@
12+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
13+
14+        ! CHECK: membar 15             ! encoding: [0x81,0x43,0xe0,0x0f]
15+        membar 15
16+
17+        ! CHECK: stbar                 ! encoding: [0x81,0x43,0xc0,0x00]
18+        stbar
19+
20+        ! CHECK: swap [%i0+%l6], %o2   ! encoding: [0xd4,0x7e,0x00,0x16]
21+        swap [%i0+%l6], %o2
22+
23+        ! CHECK: swap [%i0+32], %o2    ! encoding: [0xd4,0x7e,0x20,0x20]
24+        swap [%i0+32], %o2
25+
26+        ! CHECK: cas [%i0], %l6, %o2   ! encoding: [0xd5,0xe6,0x10,0x16]
27+        cas [%i0], %l6, %o2
28+
29+        ! CHECK: casx [%i0], %l6, %o2  ! encoding: [0xd5,0xf6,0x10,0x16]
30+        casx [%i0], %l6, %o2
31Index: lib/Target/Sparc/SparcInstrInfo.td
32===================================================================
33--- lib/Target/Sparc/SparcInstrInfo.td
34+++ lib/Target/Sparc/SparcInstrInfo.td
35@@ -935,19 +935,19 @@ let Predicates = [HasV9], hasSideEffects = 1, rd =
36  def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
37                     "membar $simm13", []>;
38 
39-let Constraints = "$val = $rd" in {
40+let Constraints = "$val = $dst" in {
41   def SWAPrr : F3_1<3, 0b001111,
42-                 (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr),
43-                 "swap [$addr], $rd",
44-                 [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
45+                 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
46+                 "swap [$addr], $dst",
47+                 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
48   def SWAPri : F3_2<3, 0b001111,
49-                 (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr),
50-                 "swap [$addr], $rd",
51-                 [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
52+                 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
53+                 "swap [$addr], $dst",
54+                 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
55 }
56 
57 let Predicates = [HasV9], Constraints = "$swap = $rd" in
58-  def CASrr: F3_1<3, 0b111100,
59+  def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
60                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
61                                      IntRegs:$swap),
62                  "cas [$rs1], $rs2, $rd",
63Index: lib/Target/Sparc/SparcInstrFormats.td
64===================================================================
65--- lib/Target/Sparc/SparcInstrFormats.td
66+++ lib/Target/Sparc/SparcInstrFormats.td
67@@ -100,9 +100,8 @@ class F3<dag outs, dag ins, string asmstr, list<da
68 
69 // Specific F3 classes: SparcV8 manual, page 44
70 //
71-class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
72+class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins,
73            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
74-  bits<8> asi = 0; // asi not currently used
75   bits<5> rs2;
76 
77   let op         = opVal;
78@@ -113,6 +112,10 @@ class F3<dag outs, dag ins, string asmstr, list<da
79   let Inst{4-0}  = rs2;
80 }
81 
82+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr,
83+       list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins,
84+                                                     asmstr, pattern>;
85+
86 class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
87            string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
88   bits<13> simm13;
89Index: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
90===================================================================
91--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
92+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
93@@ -546,7 +546,24 @@ parseOperand(SmallVectorImpl<MCParsedAsmOperand*>
94                                                  Parser.getTok().getLoc()));
95     Parser.Lex(); // Eat the [
96 
97-    ResTy = parseMEMOperand(Operands);
98+    if (Mnemonic == "cas" || Mnemonic == "casx") {
99+      SMLoc S = Parser.getTok().getLoc();
100+      if (getLexer().getKind() != AsmToken::Percent)
101+        return MatchOperand_NoMatch;
102+      Parser.Lex(); // eat %
103+
104+      unsigned RegNo, RegKind;
105+      if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
106+        return MatchOperand_NoMatch;
107+
108+      Parser.Lex(); // Eat the identifier token.
109+      SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
110+      Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
111+      ResTy = MatchOperand_Success;
112+    } else {
113+      ResTy = parseMEMOperand(Operands);
114+    }
115+
116     if (ResTy != MatchOperand_Success)
117       return ResTy;
118 
119Index: lib/Target/Sparc/SparcInstr64Bit.td
120===================================================================
121--- lib/Target/Sparc/SparcInstr64Bit.td
122+++ lib/Target/Sparc/SparcInstr64Bit.td
123@@ -415,7 +415,7 @@ def SETHIXi : F2_1<0b100,
124 
125 // ATOMICS.
126 let Predicates = [Is64Bit], Constraints = "$swap = $rd" in {
127-  def CASXrr: F3_1<3, 0b111110,
128+  def CASXrr: F3_1_asi<3, 0b111110, 0b10000000,
129                 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
130                                      I64Regs:$swap),
131                  "casx [$rs1], $rs2, $rd",
132