1Pull in r198591 from upstream llvm trunk (by Venkatraman Govindaraju): 2 3 [Sparc] Add initial implementation of disassembler for sparc 4 5Introduced here: http://svnweb.freebsd.org/changeset/base/262261 6 7Index: lib/Target/Sparc/SparcInstrFormats.td 8=================================================================== 9--- lib/Target/Sparc/SparcInstrFormats.td 10+++ lib/Target/Sparc/SparcInstrFormats.td 11@@ -12,6 +12,7 @@ class InstSP<dag outs, dag ins, string asmstr, lis 12 field bits<32> Inst; 13 14 let Namespace = "SP"; 15+ let Size = 4; 16 17 bits<2> op; 18 let Inst{31-30} = op; // Top two bits are the 'op' field 19@@ -20,6 +21,9 @@ class InstSP<dag outs, dag ins, string asmstr, lis 20 dag InOperandList = ins; 21 let AsmString = asmstr; 22 let Pattern = pattern; 23+ 24+ let DecoderNamespace = "Sparc"; 25+ field bits<32> SoftFail = 0; 26 } 27 28 //===----------------------------------------------------------------------===// 29@@ -58,6 +62,27 @@ class F2_2<bits<3> op2Val, dag outs, dag ins, stri 30 let Inst{28-25} = cond; 31 } 32 33+class F2_3<bits<3> op2Val, bits<2> ccVal, dag outs, dag ins, string asmstr, 34+ list<dag> pattern> 35+ : InstSP<outs, ins, asmstr, pattern> { 36+ bit annul; 37+ bits<4> cond; 38+ bit pred; 39+ bits<19> imm19; 40+ 41+ let op = 0; // op = 0 42+ 43+ bit annul = 0; // currently unused 44+ let pred = 1; // default is predict taken 45+ 46+ let Inst{29} = annul; 47+ let Inst{28-25} = cond; 48+ let Inst{24-22} = op2Val; 49+ let Inst{21-20} = ccVal; 50+ let Inst{19} = pred; 51+ let Inst{18-0} = imm19; 52+} 53+ 54 //===----------------------------------------------------------------------===// 55 // Format #3 instruction classes in the Sparc 56 //===----------------------------------------------------------------------===// 57Index: lib/Target/Sparc/LLVMBuild.txt 58=================================================================== 59--- lib/Target/Sparc/LLVMBuild.txt 60+++ lib/Target/Sparc/LLVMBuild.txt 61@@ -16,13 +16,15 @@ 62 ;===------------------------------------------------------------------------===; 63 64 [common] 65-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo 66+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo 67 68 [component_0] 69 type = TargetGroup 70 name = Sparc 71 parent = Target 72+has_asmparser = 1 73 has_asmprinter = 1 74+has_disassembler = 1 75 has_jit = 1 76 77 [component_1] 78Index: lib/Target/Sparc/SparcInstrInfo.td 79=================================================================== 80--- lib/Target/Sparc/SparcInstrInfo.td 81+++ lib/Target/Sparc/SparcInstrInfo.td 82@@ -230,13 +230,13 @@ def FCC_O : FCC_VAL<29>; // Ordered 83 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, 84 RegisterClass RC, ValueType Ty, Operand immOp> { 85 def rr : F3_1<2, Op3Val, 86- (outs RC:$dst), (ins RC:$b, RC:$c), 87- !strconcat(OpcStr, " $b, $c, $dst"), 88- [(set Ty:$dst, (OpNode Ty:$b, Ty:$c))]>; 89+ (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 90+ !strconcat(OpcStr, " $rs1, $rs2, $rd"), 91+ [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>; 92 def ri : F3_2<2, Op3Val, 93- (outs RC:$dst), (ins RC:$b, immOp:$c), 94- !strconcat(OpcStr, " $b, $c, $dst"), 95- [(set Ty:$dst, (OpNode Ty:$b, (Ty simm13:$c)))]>; 96+ (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 97+ !strconcat(OpcStr, " $rs1, $simm13, $rd"), 98+ [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>; 99 } 100 101 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 102@@ -243,11 +243,11 @@ multiclass F3_12<string OpcStr, bits<6> Op3Val, SD 103 /// pattern. 104 multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 105 def rr : F3_1<2, Op3Val, 106- (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 107- !strconcat(OpcStr, " $b, $c, $dst"), []>; 108+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 109+ !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>; 110 def ri : F3_2<2, Op3Val, 111- (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 112- !strconcat(OpcStr, " $b, $c, $dst"), []>; 113+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 114+ !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>; 115 } 116 117 //===----------------------------------------------------------------------===// 118@@ -488,31 +488,31 @@ let rd = 0, imm22 = 0 in 119 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>; 120 121 def ANDNrr : F3_1<2, 0b000101, 122- (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 123- "andn $b, $c, $dst", 124- [(set i32:$dst, (and i32:$b, (not i32:$c)))]>; 125+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 126+ "andn $rs1, $rs2, $rd", 127+ [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>; 128 def ANDNri : F3_2<2, 0b000101, 129- (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 130- "andn $b, $c, $dst", []>; 131+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 132+ "andn $rs1, $simm13, $rd", []>; 133 134 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>; 135 136 def ORNrr : F3_1<2, 0b000110, 137- (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 138- "orn $b, $c, $dst", 139- [(set i32:$dst, (or i32:$b, (not i32:$c)))]>; 140+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 141+ "orn $rs1, $rs2, $rd", 142+ [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>; 143 def ORNri : F3_2<2, 0b000110, 144- (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 145- "orn $b, $c, $dst", []>; 146+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 147+ "orn $rs1, $simm13, $rd", []>; 148 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>; 149 150 def XNORrr : F3_1<2, 0b000111, 151- (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 152- "xnor $b, $c, $dst", 153- [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>; 154+ (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 155+ "xnor $rs1, $rs2, $rd", 156+ [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>; 157 def XNORri : F3_2<2, 0b000111, 158- (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 159- "xnor $b, $c, $dst", []>; 160+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13), 161+ "xnor $rs1, $simm13, $rd", []>; 162 163 // Section B.12 - Shift Instructions, p. 107 164 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>; 165@@ -545,21 +545,15 @@ let Defs = [ICC] in 166 167 let Defs = [ICC], rd = 0 in { 168 def CMPrr : F3_1<2, 0b010100, 169- (outs), (ins IntRegs:$b, IntRegs:$c), 170- "cmp $b, $c", 171- [(SPcmpicc i32:$b, i32:$c)]>; 172+ (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 173+ "cmp $rs1, $rs2", 174+ [(SPcmpicc i32:$rs1, i32:$rs2)]>; 175 def CMPri : F3_2<2, 0b010100, 176- (outs), (ins IntRegs:$b, i32imm:$c), 177- "cmp $b, $c", 178- [(SPcmpicc i32:$b, (i32 simm13:$c))]>; 179+ (outs), (ins IntRegs:$rs1, i32imm:$simm13), 180+ "cmp $rs1, $simm13", 181+ [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>; 182 } 183 184-let Uses = [ICC], Defs = [ICC] in 185- def SUBXCCrr: F3_1<2, 0b011100, 186- (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 187- "subxcc $b, $c, $dst", []>; 188- 189- 190 // Section B.18 - Multiply Instructions, p. 113 191 let Defs = [Y] in { 192 defm UMUL : F3_12np<"umul", 0b001010>; 193@@ -858,7 +852,7 @@ let Defs = [FCC] in { 194 //===----------------------------------------------------------------------===// 195 // Instructions for Thread Local Storage(TLS). 196 //===----------------------------------------------------------------------===// 197- 198+let isCodeGenOnly = 1, isAsmParserOnly = 1 in { 199 def TLS_ADDrr : F3_1<2, 0b000000, 200 (outs IntRegs:$rd), 201 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 202@@ -882,6 +876,7 @@ let Uses = [O6], isCall = 1, hasDelaySlot = 1 in 203 let op = 1; 204 let Inst{29-0} = disp; 205 } 206+} 207 208 //===----------------------------------------------------------------------===// 209 // V9 Instructions 210Index: lib/Target/Sparc/CMakeLists.txt 211=================================================================== 212--- lib/Target/Sparc/CMakeLists.txt 213+++ lib/Target/Sparc/CMakeLists.txt 214@@ -3,6 +3,7 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) 215 tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info) 216 tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info) 217 tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter) 218+tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler) 219 tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter -mc-emitter) 220 tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer) 221 tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher) 222@@ -34,3 +35,4 @@ add_subdirectory(TargetInfo) 223 add_subdirectory(MCTargetDesc) 224 add_subdirectory(InstPrinter) 225 add_subdirectory(AsmParser) 226+add_subdirectory(Disassembler) 227Index: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 228=================================================================== 229--- lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 230+++ lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 231@@ -0,0 +1,228 @@ 232+//===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===// 233+// 234+// The LLVM Compiler Infrastructure 235+// 236+// This file is distributed under the University of Illinois Open Source 237+// License. See LICENSE.TXT for details. 238+// 239+//===----------------------------------------------------------------------===// 240+// 241+// This file is part of the Sparc Disassembler. 242+// 243+//===----------------------------------------------------------------------===// 244+ 245+#define DEBUG_TYPE "sparc-disassembler" 246+ 247+#include "Sparc.h" 248+#include "SparcRegisterInfo.h" 249+#include "SparcSubtarget.h" 250+#include "llvm/MC/MCDisassembler.h" 251+#include "llvm/MC/MCFixedLenDisassembler.h" 252+#include "llvm/Support/MemoryObject.h" 253+#include "llvm/Support/TargetRegistry.h" 254+ 255+using namespace llvm; 256+ 257+typedef MCDisassembler::DecodeStatus DecodeStatus; 258+ 259+namespace { 260+ 261+/// SparcDisassembler - a disassembler class for Sparc. 262+class SparcDisassembler : public MCDisassembler { 263+public: 264+ /// Constructor - Initializes the disassembler. 265+ /// 266+ SparcDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) : 267+ MCDisassembler(STI), RegInfo(Info) 268+ {} 269+ virtual ~SparcDisassembler() {} 270+ 271+ const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); } 272+ 273+ /// getInstruction - See MCDisassembler. 274+ virtual DecodeStatus getInstruction(MCInst &instr, 275+ uint64_t &size, 276+ const MemoryObject ®ion, 277+ uint64_t address, 278+ raw_ostream &vStream, 279+ raw_ostream &cStream) const; 280+private: 281+ OwningPtr<const MCRegisterInfo> RegInfo; 282+}; 283+ 284+} 285+ 286+namespace llvm { 287+ extern Target TheSparcTarget, TheSparcV9Target; 288+} 289+ 290+static MCDisassembler *createSparcDisassembler( 291+ const Target &T, 292+ const MCSubtargetInfo &STI) { 293+ return new SparcDisassembler(STI, T.createMCRegInfo("")); 294+} 295+ 296+ 297+extern "C" void LLVMInitializeSparcDisassembler() { 298+ // Register the disassembler. 299+ TargetRegistry::RegisterMCDisassembler(TheSparcTarget, 300+ createSparcDisassembler); 301+ TargetRegistry::RegisterMCDisassembler(TheSparcV9Target, 302+ createSparcDisassembler); 303+} 304+ 305+ 306+ 307+static const unsigned IntRegDecoderTable[] = { 308+ SP::G0, SP::G1, SP::G2, SP::G3, 309+ SP::G4, SP::G5, SP::G6, SP::G7, 310+ SP::O0, SP::O1, SP::O2, SP::O3, 311+ SP::O4, SP::O5, SP::O6, SP::O7, 312+ SP::L0, SP::L1, SP::L2, SP::L3, 313+ SP::L4, SP::L5, SP::L6, SP::L7, 314+ SP::I0, SP::I1, SP::I2, SP::I3, 315+ SP::I4, SP::I5, SP::I6, SP::I7 }; 316+ 317+static const unsigned FPRegDecoderTable[] = { 318+ SP::F0, SP::F1, SP::F2, SP::F3, 319+ SP::F4, SP::F5, SP::F6, SP::F7, 320+ SP::F8, SP::F9, SP::F10, SP::F11, 321+ SP::F12, SP::F13, SP::F14, SP::F15, 322+ SP::F16, SP::F17, SP::F18, SP::F19, 323+ SP::F20, SP::F21, SP::F22, SP::F23, 324+ SP::F24, SP::F25, SP::F26, SP::F27, 325+ SP::F28, SP::F29, SP::F30, SP::F31 }; 326+ 327+static const unsigned DFPRegDecoderTable[] = { 328+ SP::D0, SP::D16, SP::D1, SP::D17, 329+ SP::D2, SP::D18, SP::D3, SP::D19, 330+ SP::D4, SP::D20, SP::D5, SP::D21, 331+ SP::D6, SP::D22, SP::D7, SP::D23, 332+ SP::D8, SP::D24, SP::D9, SP::D25, 333+ SP::D10, SP::D26, SP::D11, SP::D27, 334+ SP::D12, SP::D28, SP::D13, SP::D29, 335+ SP::D14, SP::D30, SP::D15, SP::D31 }; 336+ 337+static const unsigned QFPRegDecoderTable[] = { 338+ SP::Q0, SP::Q8, -1, -1, 339+ SP::Q1, SP::Q9, -1, -1, 340+ SP::Q2, SP::Q10, -1, -1, 341+ SP::Q3, SP::Q11, -1, -1, 342+ SP::Q4, SP::Q12, -1, -1, 343+ SP::Q5, SP::Q13, -1, -1, 344+ SP::Q6, SP::Q14, -1, -1, 345+ SP::Q7, SP::Q15, -1, -1 } ; 346+ 347+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, 348+ unsigned RegNo, 349+ uint64_t Address, 350+ const void *Decoder) { 351+ if (RegNo > 31) 352+ return MCDisassembler::Fail; 353+ unsigned Reg = IntRegDecoderTable[RegNo]; 354+ Inst.addOperand(MCOperand::CreateReg(Reg)); 355+ return MCDisassembler::Success; 356+} 357+ 358+static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, 359+ unsigned RegNo, 360+ uint64_t Address, 361+ const void *Decoder) { 362+ if (RegNo > 31) 363+ return MCDisassembler::Fail; 364+ unsigned Reg = IntRegDecoderTable[RegNo]; 365+ Inst.addOperand(MCOperand::CreateReg(Reg)); 366+ return MCDisassembler::Success; 367+} 368+ 369+ 370+static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, 371+ unsigned RegNo, 372+ uint64_t Address, 373+ const void *Decoder) { 374+ if (RegNo > 31) 375+ return MCDisassembler::Fail; 376+ unsigned Reg = FPRegDecoderTable[RegNo]; 377+ Inst.addOperand(MCOperand::CreateReg(Reg)); 378+ return MCDisassembler::Success; 379+} 380+ 381+ 382+static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, 383+ unsigned RegNo, 384+ uint64_t Address, 385+ const void *Decoder) { 386+ if (RegNo > 31) 387+ return MCDisassembler::Fail; 388+ unsigned Reg = DFPRegDecoderTable[RegNo]; 389+ Inst.addOperand(MCOperand::CreateReg(Reg)); 390+ return MCDisassembler::Success; 391+} 392+ 393+ 394+static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, 395+ unsigned RegNo, 396+ uint64_t Address, 397+ const void *Decoder) { 398+ if (RegNo > 31) 399+ return MCDisassembler::Fail; 400+ 401+ unsigned Reg = QFPRegDecoderTable[RegNo]; 402+ if (Reg == (unsigned)-1) 403+ return MCDisassembler::Fail; 404+ Inst.addOperand(MCOperand::CreateReg(Reg)); 405+ return MCDisassembler::Success; 406+} 407+ 408+ 409+#include "SparcGenDisassemblerTables.inc" 410+ 411+/// readInstruction - read four bytes from the MemoryObject 412+/// and return 32 bit word. 413+static DecodeStatus readInstruction32(const MemoryObject ®ion, 414+ uint64_t address, 415+ uint64_t &size, 416+ uint32_t &insn) { 417+ uint8_t Bytes[4]; 418+ 419+ // We want to read exactly 4 Bytes of data. 420+ if (region.readBytes(address, 4, Bytes) == -1) { 421+ size = 0; 422+ return MCDisassembler::Fail; 423+ } 424+ 425+ // Encoded as a big-endian 32-bit word in the stream. 426+ insn = (Bytes[3] << 0) | 427+ (Bytes[2] << 8) | 428+ (Bytes[1] << 16) | 429+ (Bytes[0] << 24); 430+ 431+ return MCDisassembler::Success; 432+} 433+ 434+ 435+DecodeStatus 436+SparcDisassembler::getInstruction(MCInst &instr, 437+ uint64_t &Size, 438+ const MemoryObject &Region, 439+ uint64_t Address, 440+ raw_ostream &vStream, 441+ raw_ostream &cStream) const { 442+ uint32_t Insn; 443+ 444+ DecodeStatus Result = readInstruction32(Region, Address, Size, Insn); 445+ if (Result == MCDisassembler::Fail) 446+ return MCDisassembler::Fail; 447+ 448+ 449+ // Calling the auto-generated decoder function. 450+ Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address, 451+ this, STI); 452+ 453+ if (Result != MCDisassembler::Fail) { 454+ Size = 4; 455+ return Result; 456+ } 457+ 458+ return MCDisassembler::Fail; 459+} 460Index: lib/Target/Sparc/Disassembler/LLVMBuild.txt 461=================================================================== 462--- lib/Target/Sparc/Disassembler/LLVMBuild.txt 463+++ lib/Target/Sparc/Disassembler/LLVMBuild.txt 464@@ -0,0 +1,23 @@ 465+;===- ./lib/Target/Sparc/Disassembler/LLVMBuild.txt ------------*- Conf -*--===; 466+; 467+; The LLVM Compiler Infrastructure 468+; 469+; This file is distributed under the University of Illinois Open Source 470+; License. See LICENSE.TXT for details. 471+; 472+;===------------------------------------------------------------------------===; 473+; 474+; This is an LLVMBuild description file for the components in this subdirectory. 475+; 476+; For more information on the LLVMBuild system, please see: 477+; 478+; http://llvm.org/docs/LLVMBuild.html 479+; 480+;===------------------------------------------------------------------------===; 481+ 482+[component_0] 483+type = Library 484+name = SparcDisassembler 485+parent = Sparc 486+required_libraries = MC Support SparcInfo 487+add_to_library_groups = Sparc 488Index: lib/Target/Sparc/Disassembler/CMakeLists.txt 489=================================================================== 490--- lib/Target/Sparc/Disassembler/CMakeLists.txt 491+++ lib/Target/Sparc/Disassembler/CMakeLists.txt 492@@ -0,0 +1,12 @@ 493+add_llvm_library(LLVMSparcDisassembler 494+ SparcDisassembler.cpp 495+ ) 496+ 497+# workaround for hanging compilation on MSVC9 and 10 498+if( MSVC_VERSION EQUAL 1400 OR MSVC_VERSION EQUAL 1500 499+ OR MSVC_VERSION EQUAL 1600 ) 500+set_property( 501+ SOURCE SparcDisassembler.cpp 502+ PROPERTY COMPILE_FLAGS "/Od" 503+ ) 504+endif() 505Index: lib/Target/Sparc/Disassembler/Makefile 506=================================================================== 507--- lib/Target/Sparc/Disassembler/Makefile 508+++ lib/Target/Sparc/Disassembler/Makefile 509@@ -0,0 +1,16 @@ 510+##===- lib/Target/Sparc/Disassembler/Makefile --------------*- Makefile -*-===## 511+# 512+# The LLVM Compiler Infrastructure 513+# 514+# This file is distributed under the University of Illinois Open Source 515+# License. See LICENSE.TXT for details. 516+# 517+##===----------------------------------------------------------------------===## 518+ 519+LEVEL = ../../../.. 520+LIBRARYNAME = LLVMSparcDisassembler 521+ 522+# Hack: we need to include 'main' Sparc target directory to grab private headers 523+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. 524+ 525+include $(LEVEL)/Makefile.common 526Index: lib/Target/Sparc/Makefile 527=================================================================== 528--- lib/Target/Sparc/Makefile 529+++ lib/Target/Sparc/Makefile 530@@ -14,11 +14,11 @@ TARGET = Sparc 531 # Make sure that tblgen is run, first thing. 532 BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \ 533 SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \ 534- SparcGenDAGISel.inc \ 535+ SparcGenDAGISel.inc SparcGenDisassemblerTables.inc \ 536 SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \ 537 SparcGenCodeEmitter.inc SparcGenMCCodeEmitter.inc 538 539-DIRS = InstPrinter AsmParser TargetInfo MCTargetDesc 540+DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc 541 542 include $(LEVEL)/Makefile.common 543 544Index: lib/Target/Sparc/SparcInstr64Bit.td 545=================================================================== 546--- lib/Target/Sparc/SparcInstr64Bit.td 547+++ lib/Target/Sparc/SparcInstr64Bit.td 548@@ -141,6 +141,7 @@ def : Pat<(i64 imm:$val), 549 let Predicates = [Is64Bit] in { 550 551 // Register-register instructions. 552+let isCodeGenOnly = 1 in { 553 defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>; 554 defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>; 555 defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>; 556@@ -161,8 +162,6 @@ def XNORXrr : F3_1<2, 0b000111, 557 defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>; 558 defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>; 559 560-def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 561- 562 def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd), 563 (ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym), 564 "add $rs1, $rs2, $rd, $sym", 565@@ -169,18 +168,17 @@ def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$ 566 [(set i64:$rd, 567 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 568 569-// Register-immediate instructions. 570- 571-def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 572- 573-def : Pat<(ctpop i64:$src), (POPCrr $src)>; 574- 575 // "LEA" form of add 576-let isCodeGenOnly = 1 in 577 def LEAX_ADDri : F3_2<2, 0b000000, 578 (outs I64Regs:$dst), (ins MEMri:$addr), 579 "add ${addr:arith}, $dst", 580 [(set iPTR:$dst, ADDRri:$addr)]>; 581+} 582+ 583+def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 584+def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 585+def : Pat<(ctpop i64:$src), (POPCrr $src)>; 586+ 587 } // Predicates = [Is64Bit] 588 589 590@@ -245,7 +243,7 @@ def LDXri : F3_2<3, 0b001011, 591 (outs I64Regs:$dst), (ins MEMri:$addr), 592 "ldx [$addr], $dst", 593 [(set i64:$dst, (load ADDRri:$addr))]>; 594-let mayLoad = 1 in 595+let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in 596 def TLS_LDXrr : F3_1<3, 0b001011, 597 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 598 "ldx [$addr], $dst, $sym", 599@@ -278,11 +276,11 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr 600 def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 601 602 // Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 603-def LDSWrr : F3_1<3, 0b001011, 604+def LDSWrr : F3_1<3, 0b001000, 605 (outs I64Regs:$dst), (ins MEMrr:$addr), 606 "ldsw [$addr], $dst", 607 [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>; 608-def LDSWri : F3_2<3, 0b001011, 609+def LDSWri : F3_2<3, 0b001000, 610 (outs I64Regs:$dst), (ins MEMri:$addr), 611 "ldsw [$addr], $dst", 612 [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>; 613@@ -289,13 +287,13 @@ def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri 614 615 // 64-bit stores. 616 def STXrr : F3_1<3, 0b001110, 617- (outs), (ins MEMrr:$addr, I64Regs:$src), 618- "stx $src, [$addr]", 619- [(store i64:$src, ADDRrr:$addr)]>; 620+ (outs), (ins MEMrr:$addr, I64Regs:$rd), 621+ "stx $rd, [$addr]", 622+ [(store i64:$rd, ADDRrr:$addr)]>; 623 def STXri : F3_2<3, 0b001110, 624- (outs), (ins MEMri:$addr, I64Regs:$src), 625- "stx $src, [$addr]", 626- [(store i64:$src, ADDRri:$addr)]>; 627+ (outs), (ins MEMri:$addr, I64Regs:$rd), 628+ "stx $rd, [$addr]", 629+ [(store i64:$rd, ADDRri:$addr)]>; 630 631 // Truncating stores from i64 are identical to the i32 stores. 632 def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 633@@ -315,6 +313,15 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADD 634 //===----------------------------------------------------------------------===// 635 // 64-bit Conditionals. 636 //===----------------------------------------------------------------------===// 637+ 638+// Conditional branch class on %xcc: 639+class XBranchSP<dag ins, string asmstr, list<dag> pattern> 640+ : F2_3<0b001, 0b10, (outs), ins, asmstr, pattern> { 641+ let isBranch = 1; 642+ let isTerminator = 1; 643+ let hasDelaySlot = 1; 644+} 645+ 646 // 647 // Flag-setting instructions like subcc and addcc set both icc and xcc flags. 648 // The icc flags correspond to the 32-bit result, and the xcc are for the 649@@ -326,7 +333,7 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADD 650 let Predicates = [Is64Bit] in { 651 652 let Uses = [ICC] in 653-def BPXCC : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 654+def BPXCC : XBranchSP<(ins brtarget:$imm22, CCOp:$cond), 655 "b$cond %xcc, $imm22", 656 [(SPbrxcc bb:$imm22, imm:$cond)]>; 657 658@@ -409,7 +416,7 @@ def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, im 659 660 661 // 64 bit SETHI 662-let Predicates = [Is64Bit] in { 663+let Predicates = [Is64Bit], isCodeGenOnly = 1 in { 664 def SETHIXi : F2_1<0b100, 665 (outs IntRegs:$rd), (ins i64imm:$imm22), 666 "sethi $imm22, $rd", 667Index: test/MC/Disassembler/Sparc/lit.local.cfg 668=================================================================== 669--- test/MC/Disassembler/Sparc/lit.local.cfg 670+++ test/MC/Disassembler/Sparc/lit.local.cfg 671@@ -0,0 +1,4 @@ 672+targets = set(config.root.targets_to_build.split()) 673+if not 'Sparc' in targets: 674+ config.unsupported = True 675+ 676Index: test/MC/Disassembler/Sparc/sparc.txt 677=================================================================== 678--- test/MC/Disassembler/Sparc/sparc.txt 679+++ test/MC/Disassembler/Sparc/sparc.txt 680@@ -0,0 +1,82 @@ 681+# RUN: llvm-mc --disassemble %s -triple=sparc-unknown-linux | FileCheck %s 682+ 683+# CHECK: add %g0, %g0, %g0 684+0x80 0x00 0x00 0x00 685+ 686+# CHECK: add %g1, %g2, %g3 687+0x86 0x00 0x40 0x02 688+ 689+# CHECK: add %o0, %o1, %l0 690+0xa0 0x02 0x00 0x09 691+ 692+# CHECK: add %o0, 10, %l0 693+0xa0 0x02 0x20 0x0a 694+ 695+# CHECK: addcc %g1, %g2, %g3 696+0x86 0x80 0x40 0x02 697+ 698+# CHECK: addxcc %g1, %g2, %g3 699+0x86 0xc0 0x40 0x02 700+ 701+# CHECK: udiv %g1, %g2, %g3 702+0x86 0x70 0x40 0x02 703+ 704+# CHECK: sdiv %g1, %g2, %g3 705+0x86 0x78 0x40 0x02 706+ 707+# CHECK: and %g1, %g2, %g3 708+0x86 0x08 0x40 0x02 709+ 710+# CHECK: andn %g1, %g2, %g3 711+0x86 0x28 0x40 0x02 712+ 713+# CHECK: or %g1, %g2, %g3 714+0x86 0x10 0x40 0x02 715+ 716+# CHECK: orn %g1, %g2, %g3 717+0x86 0x30 0x40 0x02 718+ 719+# CHECK: xor %g1, %g2, %g3 720+0x86 0x18 0x40 0x02 721+ 722+# CHECK: xnor %g1, %g2, %g3 723+0x86 0x38 0x40 0x02 724+ 725+# CHECK: umul %g1, %g2, %g3 726+0x86 0x50 0x40 0x02 727+ 728+# CHECK: smul %g1, %g2, %g3 729+0x86 0x58 0x40 0x02 730+ 731+# CHECK: nop 732+0x01 0x00 0x00 0x00 733+ 734+# CHECK: sethi 10, %l0 735+0x21 0x00 0x00 0x0a 736+ 737+# CHECK: sll %g1, %g2, %g3 738+0x87 0x28 0x40 0x02 739+ 740+# CHECK: sll %g1, 31, %g3 741+0x87 0x28 0x60 0x1f 742+ 743+# CHECK: srl %g1, %g2, %g3 744+0x87 0x30 0x40 0x02 745+ 746+# CHECK: srl %g1, 31, %g3 747+0x87 0x30 0x60 0x1f 748+ 749+# CHECK: sra %g1, %g2, %g3 750+0x87 0x38 0x40 0x02 751+ 752+# CHECK: sra %g1, 31, %g3 753+0x87 0x38 0x60 0x1f 754+ 755+# CHECK: sub %g1, %g2, %g3 756+0x86 0x20 0x40 0x02 757+ 758+# CHECK: subcc %g1, %g2, %g3 759+0x86 0xa0 0x40 0x02 760+ 761+# CHECK: subxcc %g1, %g2, %g3 762+0x86 0xe0 0x40 0x02 763