1249259Sdim//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file defines the machine model for Sandy Bridge to support instruction 11249259Sdim// scheduling and other instruction cost heuristics. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdimdef SandyBridgeModel : SchedMachineModel { 16249259Sdim // All x86 instructions are modeled as a single micro-op, and SB can decode 4 17249259Sdim // instructions per cycle. 18249259Sdim // FIXME: Identify instructions that aren't a single fused micro-op. 19249259Sdim let IssueWidth = 4; 20263508Sdim let MicroOpBufferSize = 168; // Based on the reorder buffer. 21249259Sdim let LoadLatency = 4; 22249259Sdim let MispredictPenalty = 16; 23263508Sdim 24263508Sdim // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow 25263508Sdim // the scheduler to assign a default model to unrecognized opcodes. 26263508Sdim let CompleteModel = 0; 27249259Sdim} 28249259Sdim 29249259Sdimlet SchedModel = SandyBridgeModel in { 30249259Sdim 31249259Sdim// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 32249259Sdim 33249259Sdim// Ports 0, 1, and 5 handle all computation. 34249259Sdimdef SBPort0 : ProcResource<1>; 35249259Sdimdef SBPort1 : ProcResource<1>; 36249259Sdimdef SBPort5 : ProcResource<1>; 37249259Sdim 38249259Sdim// Ports 2 and 3 are identical. They handle loads and the address half of 39249259Sdim// stores. 40249259Sdimdef SBPort23 : ProcResource<2>; 41249259Sdim 42249259Sdim// Port 4 gets the data half of stores. Store data can be available later than 43249259Sdim// the store address, but since we don't model the latency of stores, we can 44249259Sdim// ignore that. 45249259Sdimdef SBPort4 : ProcResource<1>; 46249259Sdim 47249259Sdim// Many micro-ops are capable of issuing on multiple ports. 48249259Sdimdef SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 49249259Sdimdef SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 50249259Sdimdef SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 51249259Sdim 52263508Sdim// 54 Entry Unified Scheduler 53263508Sdimdef SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 54263508Sdim let BufferSize=54; 55263508Sdim} 56263508Sdim 57249259Sdim// Integer division issued on port 0. 58249259Sdimdef SBDivider : ProcResource<1>; 59249259Sdim 60249259Sdim// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 61249259Sdim// cycles after the memory operand. 62249259Sdimdef : ReadAdvance<ReadAfterLd, 4>; 63249259Sdim 64249259Sdim// Many SchedWrites are defined in pairs with and without a folded load. 65249259Sdim// Instructions with folded loads are usually micro-fused, so they only appear 66249259Sdim// as two micro-ops when queued in the reservation station. 67249259Sdim// This multiclass defines the resource usage for variants with and without 68249259Sdim// folded loads. 69249259Sdimmulticlass SBWriteResPair<X86FoldableSchedWrite SchedRW, 70249259Sdim ProcResourceKind ExePort, 71249259Sdim int Lat> { 72249259Sdim // Register variant is using a single cycle on ExePort. 73249259Sdim def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 74249259Sdim 75249259Sdim // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 76249259Sdim // latency. 77249259Sdim def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> { 78249259Sdim let Latency = !add(Lat, 4); 79249259Sdim } 80249259Sdim} 81249259Sdim 82249259Sdim// A folded store needs a cycle on port 4 for the store data, but it does not 83249259Sdim// need an extra port 2/3 cycle to recompute the address. 84249259Sdimdef : WriteRes<WriteRMW, [SBPort4]>; 85249259Sdim 86249259Sdimdef : WriteRes<WriteStore, [SBPort23, SBPort4]>; 87249259Sdimdef : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; } 88249259Sdimdef : WriteRes<WriteMove, [SBPort015]>; 89249259Sdimdef : WriteRes<WriteZero, []>; 90249259Sdim 91249259Sdimdefm : SBWriteResPair<WriteALU, SBPort015, 1>; 92249259Sdimdefm : SBWriteResPair<WriteIMul, SBPort1, 3>; 93263508Sdimdef : WriteRes<WriteIMulH, []> { let Latency = 3; } 94249259Sdimdefm : SBWriteResPair<WriteShift, SBPort05, 1>; 95249259Sdimdefm : SBWriteResPair<WriteJump, SBPort5, 1>; 96249259Sdim 97249259Sdim// This is for simple LEAs with one or two input operands. 98249259Sdim// The complex ones can only execute on port 1, and they require two cycles on 99249259Sdim// the port to read all inputs. We don't model that. 100249259Sdimdef : WriteRes<WriteLEA, [SBPort15]>; 101249259Sdim 102249259Sdim// This is quite rough, latency depends on the dividend. 103249259Sdimdef : WriteRes<WriteIDiv, [SBPort0, SBDivider]> { 104249259Sdim let Latency = 25; 105249259Sdim let ResourceCycles = [1, 10]; 106249259Sdim} 107249259Sdimdef : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> { 108249259Sdim let Latency = 29; 109249259Sdim let ResourceCycles = [1, 1, 10]; 110249259Sdim} 111249259Sdim 112249259Sdim// Scalar and vector floating point. 113249259Sdimdefm : SBWriteResPair<WriteFAdd, SBPort1, 3>; 114249259Sdimdefm : SBWriteResPair<WriteFMul, SBPort0, 5>; 115249259Sdimdefm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles. 116249259Sdimdefm : SBWriteResPair<WriteFRcp, SBPort0, 5>; 117249259Sdimdefm : SBWriteResPair<WriteFSqrt, SBPort0, 15>; 118249259Sdimdefm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>; 119249259Sdimdefm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>; 120249259Sdimdefm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>; 121249259Sdim 122249259Sdim// Vector integer operations. 123249259Sdimdefm : SBWriteResPair<WriteVecShift, SBPort05, 1>; 124249259Sdimdefm : SBWriteResPair<WriteVecLogic, SBPort015, 1>; 125249259Sdimdefm : SBWriteResPair<WriteVecALU, SBPort15, 1>; 126249259Sdimdefm : SBWriteResPair<WriteVecIMul, SBPort0, 5>; 127249259Sdimdefm : SBWriteResPair<WriteShuffle, SBPort15, 1>; 128249259Sdim 129249259Sdimdef : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 130249259Sdimdef : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 131249259Sdim} // SchedModel 132