1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the machine model for Sandy Bridge to support instruction 11// scheduling and other instruction cost heuristics. 12// 13//===----------------------------------------------------------------------===// 14 15def SandyBridgeModel : SchedMachineModel { 16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 17 // instructions per cycle. 18 // FIXME: Identify instructions that aren't a single fused micro-op. 19 let IssueWidth = 4; 20 let MicroOpBufferSize = 168; // Based on the reorder buffer. 21 let LoadLatency = 4; 22 let MispredictPenalty = 16; 23 24 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow 25 // the scheduler to assign a default model to unrecognized opcodes. 26 let CompleteModel = 0; 27} 28 29let SchedModel = SandyBridgeModel in { 30 31// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 32 33// Ports 0, 1, and 5 handle all computation. 34def SBPort0 : ProcResource<1>; 35def SBPort1 : ProcResource<1>; 36def SBPort5 : ProcResource<1>; 37 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. 40def SBPort23 : ProcResource<2>; 41 42// Port 4 gets the data half of stores. Store data can be available later than 43// the store address, but since we don't model the latency of stores, we can 44// ignore that. 45def SBPort4 : ProcResource<1>; 46 47// Many micro-ops are capable of issuing on multiple ports. 48def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 49def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 50def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 51 52// 54 Entry Unified Scheduler 53def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 54 let BufferSize=54; 55} 56 57// Integer division issued on port 0. 58def SBDivider : ProcResource<1>; 59 60// Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 61// cycles after the memory operand. 62def : ReadAdvance<ReadAfterLd, 4>; 63 64// Many SchedWrites are defined in pairs with and without a folded load. 65// Instructions with folded loads are usually micro-fused, so they only appear 66// as two micro-ops when queued in the reservation station. 67// This multiclass defines the resource usage for variants with and without 68// folded loads. 69multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 70 ProcResourceKind ExePort, 71 int Lat> { 72 // Register variant is using a single cycle on ExePort. 73 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; } 74 75 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the 76 // latency. 77 def : WriteRes<SchedRW.Folded, [SBPort23, ExePort]> { 78 let Latency = !add(Lat, 4); 79 } 80} 81 82// A folded store needs a cycle on port 4 for the store data, but it does not 83// need an extra port 2/3 cycle to recompute the address. 84def : WriteRes<WriteRMW, [SBPort4]>; 85 86def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 87def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 4; } 88def : WriteRes<WriteMove, [SBPort015]>; 89def : WriteRes<WriteZero, []>; 90 91defm : SBWriteResPair<WriteALU, SBPort015, 1>; 92defm : SBWriteResPair<WriteIMul, SBPort1, 3>; 93def : WriteRes<WriteIMulH, []> { let Latency = 3; } 94defm : SBWriteResPair<WriteShift, SBPort05, 1>; 95defm : SBWriteResPair<WriteJump, SBPort5, 1>; 96 97// This is for simple LEAs with one or two input operands. 98// The complex ones can only execute on port 1, and they require two cycles on 99// the port to read all inputs. We don't model that. 100def : WriteRes<WriteLEA, [SBPort15]>; 101 102// This is quite rough, latency depends on the dividend. 103def : WriteRes<WriteIDiv, [SBPort0, SBDivider]> { 104 let Latency = 25; 105 let ResourceCycles = [1, 10]; 106} 107def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> { 108 let Latency = 29; 109 let ResourceCycles = [1, 1, 10]; 110} 111 112// Scalar and vector floating point. 113defm : SBWriteResPair<WriteFAdd, SBPort1, 3>; 114defm : SBWriteResPair<WriteFMul, SBPort0, 5>; 115defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles. 116defm : SBWriteResPair<WriteFRcp, SBPort0, 5>; 117defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>; 118defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>; 119defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>; 120defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>; 121 122// Vector integer operations. 123defm : SBWriteResPair<WriteVecShift, SBPort05, 1>; 124defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>; 125defm : SBWriteResPair<WriteVecALU, SBPort15, 1>; 126defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>; 127defm : SBWriteResPair<WriteShuffle, SBPort15, 1>; 128 129def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 130def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 131} // SchedModel 132