X86.td revision 201360
1193323Sed//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This is a target description file for the Intel i386 architecture, refered to 11193323Sed// here as the "X86" architecture. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed// Get the target-independent interfaces which we are implementing... 16193323Sed// 17193323Sedinclude "llvm/Target/Target.td" 18193323Sed 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// X86 Subtarget features. 21193323Sed//===----------------------------------------------------------------------===// 22198090Srdivacky 23198090Srdivackydef FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 24198090Srdivacky "Enable conditional move instructions">; 25198090Srdivacky 26193323Seddef FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 27193323Sed "Enable MMX instructions">; 28193323Seddef FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 29193323Sed "Enable SSE instructions", 30198090Srdivacky // SSE codegen depends on cmovs, and all 31198090Srdivacky // SSE1+ processors support them. 32198090Srdivacky [FeatureMMX, FeatureCMOV]>; 33193323Seddef FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 34193323Sed "Enable SSE2 instructions", 35193323Sed [FeatureSSE1]>; 36193323Seddef FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 37193323Sed "Enable SSE3 instructions", 38193323Sed [FeatureSSE2]>; 39193323Seddef FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 40193323Sed "Enable SSSE3 instructions", 41193323Sed [FeatureSSE3]>; 42193323Seddef FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", 43193323Sed "Enable SSE 4.1 instructions", 44193323Sed [FeatureSSSE3]>; 45193323Seddef FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", 46193323Sed "Enable SSE 4.2 instructions", 47193323Sed [FeatureSSE41]>; 48193323Seddef Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 49193323Sed "Enable 3DNow! instructions">; 50193323Seddef Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 51193323Sed "Enable 3DNow! Athlon instructions", 52193323Sed [Feature3DNow]>; 53193323Sed// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 54193323Sed// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 55193323Sed// without disabling 64-bit mode. 56193323Seddef Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 57193323Sed "Support 64-bit instructions">; 58193323Seddef FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 59193323Sed "Bit testing of memory is slow">; 60193323Seddef FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 61193323Sed "Support SSE 4a instructions">; 62193323Sed 63195098Seddef FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true", 64195098Sed "Enable AVX instructions">; 65195098Seddef FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", 66201360Srdivacky "Enable three-operand fused multiple-add">; 67195098Seddef FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 68195098Sed "Enable four-operand fused multiple-add">; 69195098Sed 70193323Sed//===----------------------------------------------------------------------===// 71193323Sed// X86 processors supported. 72193323Sed//===----------------------------------------------------------------------===// 73193323Sed 74193323Sedclass Proc<string Name, list<SubtargetFeature> Features> 75193323Sed : Processor<Name, NoItineraries, Features>; 76193323Sed 77193323Seddef : Proc<"generic", []>; 78193323Seddef : Proc<"i386", []>; 79193323Seddef : Proc<"i486", []>; 80193323Seddef : Proc<"i586", []>; 81193323Seddef : Proc<"pentium", []>; 82193323Seddef : Proc<"pentium-mmx", [FeatureMMX]>; 83193323Seddef : Proc<"i686", []>; 84198090Srdivackydef : Proc<"pentiumpro", [FeatureCMOV]>; 85198090Srdivackydef : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 86193323Seddef : Proc<"pentium3", [FeatureSSE1]>; 87193323Seddef : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 88193323Seddef : Proc<"pentium4", [FeatureSSE2]>; 89193323Seddef : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; 90193323Seddef : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; 91193323Seddef : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 92193323Seddef : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 93193323Seddef : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>; 94193323Seddef : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>; 95193323Seddef : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 96193323Seddef : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; 97195098Seddef : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; 98195098Sed// Sandy Bridge does not have FMA 99195098Seddef : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>; 100193323Sed 101193323Seddef : Proc<"k6", [FeatureMMX]>; 102193323Seddef : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; 103193323Seddef : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; 104193323Seddef : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; 105193323Seddef : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; 106193323Seddef : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 107193323Seddef : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 108193323Seddef : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 109193323Seddef : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 110193323Sed FeatureSlowBTMem]>; 111193323Seddef : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 112193323Sed FeatureSlowBTMem]>; 113193323Seddef : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 114193323Sed FeatureSlowBTMem]>; 115193323Seddef : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 116193323Sed FeatureSlowBTMem]>; 117193323Seddef : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 118193323Sed FeatureSlowBTMem]>; 119193323Seddef : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 120193323Sed FeatureSlowBTMem]>; 121193323Seddef : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 122193323Sed FeatureSlowBTMem]>; 123193323Seddef : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A, 124193323Sed Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 125193323Seddef : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A, 126193323Sed Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 127195340Seddef : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 128195340Sed Feature3DNowA]>; 129195340Seddef : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 130195340Sed Feature3DNowA]>; 131193323Sed 132193323Seddef : Proc<"winchip-c6", [FeatureMMX]>; 133193323Seddef : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; 134193323Seddef : Proc<"c3", [FeatureMMX, Feature3DNow]>; 135193323Seddef : Proc<"c3-2", [FeatureSSE1]>; 136193323Sed 137193323Sed//===----------------------------------------------------------------------===// 138193323Sed// Register File Description 139193323Sed//===----------------------------------------------------------------------===// 140193323Sed 141193323Sedinclude "X86RegisterInfo.td" 142193323Sed 143193323Sed//===----------------------------------------------------------------------===// 144193323Sed// Instruction Descriptions 145193323Sed//===----------------------------------------------------------------------===// 146193323Sed 147193323Sedinclude "X86InstrInfo.td" 148193323Sed 149193323Seddef X86InstrInfo : InstrInfo { 150193323Sed 151193323Sed // Define how we want to layout our TargetSpecific information field... This 152193323Sed // should be kept up-to-date with the fields in the X86InstrInfo.h file. 153193323Sed let TSFlagsFields = ["FormBits", 154193323Sed "hasOpSizePrefix", 155193323Sed "hasAdSizePrefix", 156193323Sed "Prefix", 157193323Sed "hasREX_WPrefix", 158193323Sed "ImmTypeBits", 159193323Sed "FPFormBits", 160193323Sed "hasLockPrefix", 161193323Sed "SegOvrBits", 162193323Sed "Opcode"]; 163193323Sed let TSFlagsShifts = [0, 164193323Sed 6, 165193323Sed 7, 166193323Sed 8, 167193323Sed 12, 168193323Sed 13, 169193323Sed 16, 170193323Sed 19, 171193323Sed 20, 172193323Sed 24]; 173193323Sed} 174193323Sed 175193323Sed//===----------------------------------------------------------------------===// 176193323Sed// Calling Conventions 177193323Sed//===----------------------------------------------------------------------===// 178193323Sed 179193323Sedinclude "X86CallingConv.td" 180193323Sed 181193323Sed 182193323Sed//===----------------------------------------------------------------------===// 183193323Sed// Assembly Printers 184193323Sed//===----------------------------------------------------------------------===// 185193323Sed 186198090Srdivacky// Currently the X86 assembly parser only supports ATT syntax. 187198090Srdivackydef ATTAsmParser : AsmParser { 188198090Srdivacky string AsmParserClassName = "ATTAsmParser"; 189198090Srdivacky int Variant = 0; 190198090Srdivacky 191198090Srdivacky // Discard comments in assembly strings. 192198090Srdivacky string CommentDelimiter = "#"; 193198090Srdivacky 194198090Srdivacky // Recognize hard coded registers. 195198090Srdivacky string RegisterPrefix = "%"; 196198090Srdivacky} 197198090Srdivacky 198193323Sed// The X86 target supports two different syntaxes for emitting machine code. 199193323Sed// This is controlled by the -x86-asm-syntax={att|intel} 200193323Seddef ATTAsmWriter : AsmWriter { 201198090Srdivacky string AsmWriterClassName = "ATTInstPrinter"; 202193323Sed int Variant = 0; 203193323Sed} 204193323Seddef IntelAsmWriter : AsmWriter { 205198090Srdivacky string AsmWriterClassName = "IntelInstPrinter"; 206193323Sed int Variant = 1; 207193323Sed} 208193323Sed 209193323Seddef X86 : Target { 210193323Sed // Information about the instructions... 211193323Sed let InstructionSet = X86InstrInfo; 212193323Sed 213198090Srdivacky let AssemblyParsers = [ATTAsmParser]; 214198090Srdivacky 215193323Sed let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 216193323Sed} 217