X86.td revision 201360 
1//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, refered to
11// here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget features.
21//===----------------------------------------------------------------------===//
22
23def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
24                                      "Enable conditional move instructions">;
25
26def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
27                                      "Enable MMX instructions">;
28def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
29                                      "Enable SSE instructions",
30                                      // SSE codegen depends on cmovs, and all
31                                      // SSE1+ processors support them. 
32                                      [FeatureMMX, FeatureCMOV]>;
33def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
34                                      "Enable SSE2 instructions",
35                                      [FeatureSSE1]>;
36def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
37                                      "Enable SSE3 instructions",
38                                      [FeatureSSE2]>;
39def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
40                                      "Enable SSSE3 instructions",
41                                      [FeatureSSE3]>;
42def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
43                                      "Enable SSE 4.1 instructions",
44                                      [FeatureSSSE3]>;
45def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
46                                      "Enable SSE 4.2 instructions",
47                                      [FeatureSSE41]>;
48def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
49                                      "Enable 3DNow! instructions">;
50def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
51                                      "Enable 3DNow! Athlon instructions",
52                                      [Feature3DNow]>;
53// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
54// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
55// without disabling 64-bit mode.
56def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
57                                      "Support 64-bit instructions">;
58def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
59                                       "Bit testing of memory is slow">;
60def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
61                                      "Support SSE 4a instructions">;
62
63def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
64                                      "Enable AVX instructions">;
65def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
66                                     "Enable three-operand fused multiple-add">;
67def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
68                                      "Enable four-operand fused multiple-add">;
69
70//===----------------------------------------------------------------------===//
71// X86 processors supported.
72//===----------------------------------------------------------------------===//
73
74class Proc<string Name, list<SubtargetFeature> Features>
75 : Processor<Name, NoItineraries, Features>;
76
77def : Proc<"generic",         []>;
78def : Proc<"i386",            []>;
79def : Proc<"i486",            []>;
80def : Proc<"i586",            []>;
81def : Proc<"pentium",         []>;
82def : Proc<"pentium-mmx",     [FeatureMMX]>;
83def : Proc<"i686",            []>;
84def : Proc<"pentiumpro",      [FeatureCMOV]>;
85def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
86def : Proc<"pentium3",        [FeatureSSE1]>;
87def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
88def : Proc<"pentium4",        [FeatureSSE2]>;
89def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
90def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
91def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
92def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
93def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
94def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
95def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
96def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
97def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem]>;
98// Sandy Bridge does not have FMA
99def : Proc<"sandybridge",     [FeatureSSE42,  FeatureAVX,   Feature64Bit]>;
100
101def : Proc<"k6",              [FeatureMMX]>;
102def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
103def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
104def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
105def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
106def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
107def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
108def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
109def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
110                               FeatureSlowBTMem]>;
111def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
112                               FeatureSlowBTMem]>;
113def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
114                               FeatureSlowBTMem]>;
115def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
116                               FeatureSlowBTMem]>;
117def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
118                               FeatureSlowBTMem]>;
119def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
120                               FeatureSlowBTMem]>;
121def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
122                               FeatureSlowBTMem]>;
123def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
124                               Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
125def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
126                               Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
127def : Proc<"istanbul",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
128                               Feature3DNowA]>;
129def : Proc<"shanghai",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
130                               Feature3DNowA]>;
131
132def : Proc<"winchip-c6",      [FeatureMMX]>;
133def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
134def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
135def : Proc<"c3-2",            [FeatureSSE1]>;
136
137//===----------------------------------------------------------------------===//
138// Register File Description
139//===----------------------------------------------------------------------===//
140
141include "X86RegisterInfo.td"
142
143//===----------------------------------------------------------------------===//
144// Instruction Descriptions
145//===----------------------------------------------------------------------===//
146
147include "X86InstrInfo.td"
148
149def X86InstrInfo : InstrInfo {
150
151  // Define how we want to layout our TargetSpecific information field... This
152  // should be kept up-to-date with the fields in the X86InstrInfo.h file.
153  let TSFlagsFields = ["FormBits",
154                       "hasOpSizePrefix",
155                       "hasAdSizePrefix",
156                       "Prefix",
157                       "hasREX_WPrefix",
158                       "ImmTypeBits",
159                       "FPFormBits",
160                       "hasLockPrefix",
161                       "SegOvrBits",
162                       "Opcode"];
163  let TSFlagsShifts = [0,
164                       6,
165                       7,
166                       8,
167                       12,
168                       13,
169                       16,
170                       19,
171                       20,
172                       24];
173}
174
175//===----------------------------------------------------------------------===//
176// Calling Conventions
177//===----------------------------------------------------------------------===//
178
179include "X86CallingConv.td"
180
181
182//===----------------------------------------------------------------------===//
183// Assembly Printers
184//===----------------------------------------------------------------------===//
185
186// Currently the X86 assembly parser only supports ATT syntax.
187def ATTAsmParser : AsmParser {
188  string AsmParserClassName  = "ATTAsmParser";
189  int Variant = 0;
190
191  // Discard comments in assembly strings.
192  string CommentDelimiter = "#";
193
194  // Recognize hard coded registers.
195  string RegisterPrefix = "%";
196}
197
198// The X86 target supports two different syntaxes for emitting machine code.
199// This is controlled by the -x86-asm-syntax={att|intel}
200def ATTAsmWriter : AsmWriter {
201  string AsmWriterClassName  = "ATTInstPrinter";
202  int Variant = 0;
203}
204def IntelAsmWriter : AsmWriter {
205  string AsmWriterClassName  = "IntelInstPrinter";
206  int Variant = 1;
207}
208
209def X86 : Target {
210  // Information about the instructions...
211  let InstructionSet = X86InstrInfo;
212
213  let AssemblyParsers = [ATTAsmParser];
214
215  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
216}
217