1//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains instruction defs that are common to all hw codegen 11// targets. 12// 13//===----------------------------------------------------------------------===// 14 15class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction { 16 field bit isRegisterLoad = 0; 17 field bit isRegisterStore = 0; 18 19 let Namespace = "AMDGPU"; 20 let OutOperandList = outs; 21 let InOperandList = ins; 22 let AsmString = asm; 23 let Pattern = pattern; 24 let Itinerary = NullALU; 25 26 let TSFlags{63} = isRegisterLoad; 27 let TSFlags{62} = isRegisterStore; 28} 29 30class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern> 31 : AMDGPUInst<outs, ins, asm, pattern> { 32 33 field bits<32> Inst = 0xffffffff; 34 35} 36 37def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>; 38def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>; 39 40//===----------------------------------------------------------------------===// 41// PatLeafs for floating-point comparisons 42//===----------------------------------------------------------------------===// 43 44def COND_OEQ : PatLeaf < 45 (cond), 46 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}] 47>; 48 49def COND_OGT : PatLeaf < 50 (cond), 51 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}] 52>; 53 54def COND_OGE : PatLeaf < 55 (cond), 56 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}] 57>; 58 59def COND_OLT : PatLeaf < 60 (cond), 61 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}] 62>; 63 64def COND_OLE : PatLeaf < 65 (cond), 66 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}] 67>; 68 69def COND_UNE : PatLeaf < 70 (cond), 71 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}] 72>; 73 74def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>; 75def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>; 76 77//===----------------------------------------------------------------------===// 78// PatLeafs for unsigned comparisons 79//===----------------------------------------------------------------------===// 80 81def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>; 82def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>; 83def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>; 84def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>; 85 86//===----------------------------------------------------------------------===// 87// PatLeafs for signed comparisons 88//===----------------------------------------------------------------------===// 89 90def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>; 91def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>; 92def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>; 93def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>; 94 95//===----------------------------------------------------------------------===// 96// PatLeafs for integer equality 97//===----------------------------------------------------------------------===// 98 99def COND_EQ : PatLeaf < 100 (cond), 101 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}] 102>; 103 104def COND_NE : PatLeaf < 105 (cond), 106 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}] 107>; 108 109def COND_NULL : PatLeaf < 110 (cond), 111 [{return false;}] 112>; 113 114//===----------------------------------------------------------------------===// 115// Load/Store Pattern Fragments 116//===----------------------------------------------------------------------===// 117 118def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 119 LoadSDNode *L = cast<LoadSDNode>(N); 120 return L->getExtensionType() == ISD::ZEXTLOAD || 121 L->getExtensionType() == ISD::EXTLOAD; 122}]>; 123 124def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 125 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 126}]>; 127 128def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{ 129 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 130}]>; 131 132def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{ 133 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 134}]>; 135 136def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{ 137 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 138}]>; 139 140def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{ 141 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 142}]>; 143 144def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{ 145 return isLocalLoad(dyn_cast<LoadSDNode>(N)); 146}]>; 147 148def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{ 149 return isLocalLoad(dyn_cast<LoadSDNode>(N)); 150}]>; 151 152def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 153 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 154}]>; 155 156def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{ 157 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 158}]>; 159 160def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{ 161 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 162}]>; 163 164def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{ 165 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 166}]>; 167 168def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{ 169 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 170}]>; 171 172def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{ 173 return isLocalLoad(dyn_cast<LoadSDNode>(N)); 174}]>; 175 176def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{ 177 return isLocalLoad(dyn_cast<LoadSDNode>(N)); 178}]>; 179 180def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{ 181 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 182}]>; 183 184def az_extloadi32_global : PatFrag<(ops node:$ptr), 185 (az_extloadi32 node:$ptr), [{ 186 return isGlobalLoad(dyn_cast<LoadSDNode>(N)); 187}]>; 188 189def az_extloadi32_constant : PatFrag<(ops node:$ptr), 190 (az_extloadi32 node:$ptr), [{ 191 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1); 192}]>; 193 194def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr), 195 (truncstorei8 node:$val, node:$ptr), [{ 196 return isGlobalStore(dyn_cast<StoreSDNode>(N)); 197}]>; 198 199def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr), 200 (truncstorei16 node:$val, node:$ptr), [{ 201 return isGlobalStore(dyn_cast<StoreSDNode>(N)); 202}]>; 203 204def local_store : PatFrag<(ops node:$val, node:$ptr), 205 (store node:$val, node:$ptr), [{ 206 return isLocalStore(dyn_cast<StoreSDNode>(N)); 207}]>; 208 209def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr), 210 (truncstorei8 node:$val, node:$ptr), [{ 211 return isLocalStore(dyn_cast<StoreSDNode>(N)); 212}]>; 213 214def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr), 215 (truncstorei16 node:$val, node:$ptr), [{ 216 return isLocalStore(dyn_cast<StoreSDNode>(N)); 217}]>; 218 219def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 220 return isLocalLoad(dyn_cast<LoadSDNode>(N)); 221}]>; 222 223def atomic_load_add_local : PatFrag<(ops node:$ptr, node:$value), 224 (atomic_load_add node:$ptr, node:$value), [{ 225 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS; 226}]>; 227 228def atomic_load_sub_local : PatFrag<(ops node:$ptr, node:$value), 229 (atomic_load_sub node:$ptr, node:$value), [{ 230 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS; 231}]>; 232 233def mskor_global : PatFrag<(ops node:$val, node:$ptr), 234 (AMDGPUstore_mskor node:$val, node:$ptr), [{ 235 return dyn_cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS; 236}]>; 237 238class Constants { 239int TWO_PI = 0x40c90fdb; 240int PI = 0x40490fdb; 241int TWO_PI_INV = 0x3e22f983; 242int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding 243} 244def CONST : Constants; 245 246def FP_ZERO : PatLeaf < 247 (fpimm), 248 [{return N->getValueAPF().isZero();}] 249>; 250 251def FP_ONE : PatLeaf < 252 (fpimm), 253 [{return N->isExactlyValue(1.0);}] 254>; 255 256def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>; 257def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>; 258 259let isCodeGenOnly = 1, isPseudo = 1 in { 260 261let usesCustomInserter = 1 in { 262 263class CLAMP <RegisterClass rc> : AMDGPUShaderInst < 264 (outs rc:$dst), 265 (ins rc:$src0), 266 "CLAMP $dst, $src0", 267 [(set f32:$dst, (int_AMDIL_clamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))] 268>; 269 270class FABS <RegisterClass rc> : AMDGPUShaderInst < 271 (outs rc:$dst), 272 (ins rc:$src0), 273 "FABS $dst, $src0", 274 [(set f32:$dst, (fabs f32:$src0))] 275>; 276 277class FNEG <RegisterClass rc> : AMDGPUShaderInst < 278 (outs rc:$dst), 279 (ins rc:$src0), 280 "FNEG $dst, $src0", 281 [(set f32:$dst, (fneg f32:$src0))] 282>; 283 284} // usesCustomInserter = 1 285 286multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass, 287 ComplexPattern addrPat> { 288let UseNamedOperandTable = 1 in { 289 290 def RegisterLoad : AMDGPUShaderInst < 291 (outs dstClass:$dst), 292 (ins addrClass:$addr, i32imm:$chan), 293 "RegisterLoad $dst, $addr", 294 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))] 295 > { 296 let isRegisterLoad = 1; 297 } 298 299 def RegisterStore : AMDGPUShaderInst < 300 (outs), 301 (ins dstClass:$val, addrClass:$addr, i32imm:$chan), 302 "RegisterStore $val, $addr", 303 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))] 304 > { 305 let isRegisterStore = 1; 306 } 307} 308} 309 310} // End isCodeGenOnly = 1, isPseudo = 1 311 312/* Generic helper patterns for intrinsics */ 313/* -------------------------------------- */ 314 315class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul> 316 : Pat < 317 (fpow f32:$src0, f32:$src1), 318 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0))) 319>; 320 321/* Other helper patterns */ 322/* --------------------- */ 323 324/* Extract element pattern */ 325class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx, 326 SubRegIndex sub_reg> 327 : Pat< 328 (sub_type (vector_extract vec_type:$src, sub_idx)), 329 (EXTRACT_SUBREG $src, sub_reg) 330>; 331 332/* Insert element pattern */ 333class Insert_Element <ValueType elem_type, ValueType vec_type, 334 int sub_idx, SubRegIndex sub_reg> 335 : Pat < 336 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx), 337 (INSERT_SUBREG $vec, $elem, sub_reg) 338>; 339 340class Vector4_Build <ValueType vecType, ValueType elemType> : Pat < 341 (vecType (build_vector elemType:$x, elemType:$y, elemType:$z, elemType:$w)), 342 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG 343 (vecType (IMPLICIT_DEF)), $x, sub0), $y, sub1), $z, sub2), $w, sub3) 344>; 345 346// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer 347// can handle COPY instructions. 348// bitconvert pattern 349class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat < 350 (dt (bitconvert (st rc:$src0))), 351 (dt rc:$src0) 352>; 353 354// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer 355// can handle COPY instructions. 356class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat < 357 (vt (AMDGPUdwordaddr (vt rc:$addr))), 358 (vt rc:$addr) 359>; 360 361// BFI_INT patterns 362 363multiclass BFIPatterns <Instruction BFI_INT> { 364 365 // Definition from ISA doc: 366 // (y & x) | (z & ~x) 367 def : Pat < 368 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), 369 (BFI_INT $x, $y, $z) 370 >; 371 372 // SHA-256 Ch function 373 // z ^ (x & (y ^ z)) 374 def : Pat < 375 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), 376 (BFI_INT $x, $y, $z) 377 >; 378 379} 380 381// SHA-256 Ma patterns 382 383// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y 384class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat < 385 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))), 386 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y) 387>; 388 389// Bitfield extract patterns 390 391/* 392 393XXX: The BFE pattern is not working correctly because the XForm is not being 394applied. 395 396def legalshift32 : ImmLeaf <i32, [{return Imm >=0 && Imm < 32;}]>; 397def bfemask : PatLeaf <(imm), [{return isMask_32(N->getZExtValue());}], 398 SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(CountTrailingOnes_32(N->getZExtValue()), MVT::i32);}]>>; 399 400class BFEPattern <Instruction BFE> : Pat < 401 (and (srl i32:$x, legalshift32:$y), bfemask:$z), 402 (BFE $x, $y, $z) 403>; 404 405*/ 406 407// rotr pattern 408class ROTRPattern <Instruction BIT_ALIGN> : Pat < 409 (rotr i32:$src0, i32:$src1), 410 (BIT_ALIGN $src0, $src0, $src1) 411>; 412 413// 24-bit arithmetic patterns 414def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>; 415 416/* 417class UMUL24Pattern <Instruction UMUL24> : Pat < 418 (mul U24:$x, U24:$y), 419 (UMUL24 $x, $y) 420>; 421*/ 422 423include "R600Instructions.td" 424 425include "SIInstrInfo.td" 426 427