PPCFrameLowering.cpp revision 251662
1234353Sdim//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2218885Sdim// 3218885Sdim// The LLVM Compiler Infrastructure 4218885Sdim// 5218885Sdim// This file is distributed under the University of Illinois Open Source 6218885Sdim// License. See LICENSE.TXT for details. 7218885Sdim// 8218885Sdim//===----------------------------------------------------------------------===// 9218885Sdim// 10218885Sdim// This file contains the PPC implementation of TargetFrameLowering class. 11218885Sdim// 12218885Sdim//===----------------------------------------------------------------------===// 13218885Sdim 14218885Sdim#include "PPCFrameLowering.h" 15249423Sdim#include "PPCInstrBuilder.h" 16218885Sdim#include "PPCInstrInfo.h" 17218885Sdim#include "PPCMachineFunctionInfo.h" 18218885Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 19218885Sdim#include "llvm/CodeGen/MachineFunction.h" 20218885Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 21218885Sdim#include "llvm/CodeGen/MachineModuleInfo.h" 22218885Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 23218885Sdim#include "llvm/CodeGen/RegisterScavenging.h" 24249423Sdim#include "llvm/IR/Function.h" 25218885Sdim#include "llvm/Target/TargetOptions.h" 26218885Sdim 27218885Sdimusing namespace llvm; 28218885Sdim 29218885Sdim// FIXME This disables some code that aligns the stack to a boundary bigger than 30218885Sdim// the default (16 bytes on Darwin) when there is a stack local of greater 31218885Sdim// alignment. This does not currently work, because the delta between old and 32218885Sdim// new stack pointers is added to offsets that reference incoming parameters 33218885Sdim// after the prolog is generated, and the code that does that doesn't handle a 34218885Sdim// variable delta. You don't want to do that anyway; a better approach is to 35218885Sdim// reserve another register that retains to the incoming stack pointer, and 36218885Sdim// reference parameters relative to that. 37218885Sdim#define ALIGN_STACK 0 38218885Sdim 39218885Sdim 40218885Sdim/// VRRegNo - Map from a numbered VR register to its enum value. 41218885Sdim/// 42234353Sdimstatic const uint16_t VRRegNo[] = { 43218885Sdim PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44218885Sdim PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45218885Sdim PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46218885Sdim PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47218885Sdim}; 48218885Sdim 49218885Sdim/// RemoveVRSaveCode - We have found that this function does not need any code 50218885Sdim/// to manipulate the VRSAVE register, even though it uses vector registers. 51218885Sdim/// This can happen when the only registers used are known to be live in or out 52218885Sdim/// of the function. Remove all of the VRSAVE related code from the function. 53243830Sdim/// FIXME: The removal of the code results in a compile failure at -O0 when the 54243830Sdim/// function contains a function call, as the GPR containing original VRSAVE 55243830Sdim/// contents is spilled and reloaded around the call. Without the prolog code, 56243830Sdim/// the spill instruction refers to an undefined register. This code needs 57243830Sdim/// to account for all uses of that GPR. 58218885Sdimstatic void RemoveVRSaveCode(MachineInstr *MI) { 59218885Sdim MachineBasicBlock *Entry = MI->getParent(); 60218885Sdim MachineFunction *MF = Entry->getParent(); 61218885Sdim 62218885Sdim // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63218885Sdim MachineBasicBlock::iterator MBBI = MI; 64218885Sdim ++MBBI; 65218885Sdim assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66218885Sdim MBBI->eraseFromParent(); 67218885Sdim 68218885Sdim bool RemovedAllMTVRSAVEs = true; 69218885Sdim // See if we can find and remove the MTVRSAVE instruction from all of the 70218885Sdim // epilog blocks. 71218885Sdim for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72218885Sdim // If last instruction is a return instruction, add an epilogue 73234353Sdim if (!I->empty() && I->back().isReturn()) { 74218885Sdim bool FoundIt = false; 75218885Sdim for (MBBI = I->end(); MBBI != I->begin(); ) { 76218885Sdim --MBBI; 77218885Sdim if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78218885Sdim MBBI->eraseFromParent(); // remove it. 79218885Sdim FoundIt = true; 80218885Sdim break; 81218885Sdim } 82218885Sdim } 83218885Sdim RemovedAllMTVRSAVEs &= FoundIt; 84218885Sdim } 85218885Sdim } 86218885Sdim 87218885Sdim // If we found and removed all MTVRSAVE instructions, remove the read of 88218885Sdim // VRSAVE as well. 89218885Sdim if (RemovedAllMTVRSAVEs) { 90218885Sdim MBBI = MI; 91218885Sdim assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92218885Sdim --MBBI; 93218885Sdim assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94218885Sdim MBBI->eraseFromParent(); 95218885Sdim } 96218885Sdim 97218885Sdim // Finally, nuke the UPDATE_VRSAVE. 98218885Sdim MI->eraseFromParent(); 99218885Sdim} 100218885Sdim 101218885Sdim// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102218885Sdim// instruction selector. Based on the vector registers that have been used, 103218885Sdim// transform this into the appropriate ORI instruction. 104218885Sdimstatic void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105218885Sdim MachineFunction *MF = MI->getParent()->getParent(); 106249423Sdim const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 107218885Sdim DebugLoc dl = MI->getDebugLoc(); 108218885Sdim 109218885Sdim unsigned UsedRegMask = 0; 110218885Sdim for (unsigned i = 0; i != 32; ++i) 111218885Sdim if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 112218885Sdim UsedRegMask |= 1 << (31-i); 113218885Sdim 114218885Sdim // Live in and live out values already must be in the mask, so don't bother 115218885Sdim // marking them. 116218885Sdim for (MachineRegisterInfo::livein_iterator 117218885Sdim I = MF->getRegInfo().livein_begin(), 118218885Sdim E = MF->getRegInfo().livein_end(); I != E; ++I) { 119249423Sdim unsigned RegNo = TRI->getEncodingValue(I->first); 120218885Sdim if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 121218885Sdim UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122218885Sdim } 123249423Sdim 124249423Sdim // Live out registers appear as use operands on return instructions. 125249423Sdim for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 126249423Sdim UsedRegMask != 0 && BI != BE; ++BI) { 127249423Sdim const MachineBasicBlock &MBB = *BI; 128249423Sdim if (MBB.empty() || !MBB.back().isReturn()) 129249423Sdim continue; 130249423Sdim const MachineInstr &Ret = MBB.back(); 131249423Sdim for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 132249423Sdim const MachineOperand &MO = Ret.getOperand(I); 133249423Sdim if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 134249423Sdim continue; 135249423Sdim unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 136249423Sdim UsedRegMask &= ~(1 << (31-RegNo)); 137249423Sdim } 138218885Sdim } 139218885Sdim 140218885Sdim // If no registers are used, turn this into a copy. 141218885Sdim if (UsedRegMask == 0) { 142218885Sdim // Remove all VRSAVE code. 143218885Sdim RemoveVRSaveCode(MI); 144218885Sdim return; 145218885Sdim } 146218885Sdim 147218885Sdim unsigned SrcReg = MI->getOperand(1).getReg(); 148218885Sdim unsigned DstReg = MI->getOperand(0).getReg(); 149218885Sdim 150218885Sdim if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 151218885Sdim if (DstReg != SrcReg) 152218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 153218885Sdim .addReg(SrcReg) 154218885Sdim .addImm(UsedRegMask); 155218885Sdim else 156218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 157218885Sdim .addReg(SrcReg, RegState::Kill) 158218885Sdim .addImm(UsedRegMask); 159218885Sdim } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 160218885Sdim if (DstReg != SrcReg) 161218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 162218885Sdim .addReg(SrcReg) 163218885Sdim .addImm(UsedRegMask >> 16); 164218885Sdim else 165218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 166218885Sdim .addReg(SrcReg, RegState::Kill) 167218885Sdim .addImm(UsedRegMask >> 16); 168218885Sdim } else { 169218885Sdim if (DstReg != SrcReg) 170218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 171218885Sdim .addReg(SrcReg) 172218885Sdim .addImm(UsedRegMask >> 16); 173218885Sdim else 174218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 175218885Sdim .addReg(SrcReg, RegState::Kill) 176218885Sdim .addImm(UsedRegMask >> 16); 177218885Sdim 178218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 179218885Sdim .addReg(DstReg, RegState::Kill) 180218885Sdim .addImm(UsedRegMask & 0xFFFF); 181218885Sdim } 182218885Sdim 183218885Sdim // Remove the old UPDATE_VRSAVE instruction. 184218885Sdim MI->eraseFromParent(); 185218885Sdim} 186218885Sdim 187243830Sdimstatic bool spillsCR(const MachineFunction &MF) { 188243830Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 189243830Sdim return FuncInfo->isCRSpilled(); 190243830Sdim} 191243830Sdim 192249423Sdimstatic bool spillsVRSAVE(const MachineFunction &MF) { 193249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 194249423Sdim return FuncInfo->isVRSAVESpilled(); 195249423Sdim} 196249423Sdim 197249423Sdimstatic bool hasSpills(const MachineFunction &MF) { 198249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 199249423Sdim return FuncInfo->hasSpills(); 200249423Sdim} 201249423Sdim 202249423Sdimstatic bool hasNonRISpills(const MachineFunction &MF) { 203249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 204249423Sdim return FuncInfo->hasNonRISpills(); 205249423Sdim} 206249423Sdim 207218885Sdim/// determineFrameLayout - Determine the size of the frame and maximum call 208218885Sdim/// frame size. 209249423Sdimunsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 210249423Sdim bool UpdateMF, 211249423Sdim bool UseEstimate) const { 212218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 213218885Sdim 214218885Sdim // Get the number of bytes to allocate from the FrameInfo 215249423Sdim unsigned FrameSize = 216249423Sdim UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 217218885Sdim 218218885Sdim // Get the alignments provided by the target, and the maximum alignment 219218885Sdim // (if any) of the fixed frame objects. 220218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 221218885Sdim unsigned TargetAlign = getStackAlignment(); 222218885Sdim unsigned AlignMask = TargetAlign - 1; // 223218885Sdim 224218885Sdim // If we are a leaf function, and use up to 224 bytes of stack space, 225218885Sdim // don't have a frame pointer, calls, or dynamic alloca then we do not need 226251662Sdim // to adjust the stack pointer (we fit in the Red Zone). 227249423Sdim // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 228249423Sdim // stackless code if all local vars are reg-allocated. 229249423Sdim bool DisableRedZone = MF.getFunction()->getAttributes(). 230249423Sdim hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 231218885Sdim if (!DisableRedZone && 232249423Sdim (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 233249423Sdim !Subtarget.isSVR4ABI() || // allocated locals. 234249423Sdim FrameSize == 0) && 235218885Sdim FrameSize <= 224 && // Fits in red zone. 236218885Sdim !MFI->hasVarSizedObjects() && // No dynamic alloca. 237218885Sdim !MFI->adjustsStack() && // No calls. 238218885Sdim (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 239218885Sdim // No need for frame 240249423Sdim if (UpdateMF) 241249423Sdim MFI->setStackSize(0); 242249423Sdim return 0; 243218885Sdim } 244218885Sdim 245218885Sdim // Get the maximum call frame size of all the calls. 246218885Sdim unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 247218885Sdim 248218885Sdim // Maximum call frame needs to be at least big enough for linkage and 8 args. 249218885Sdim unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 250218885Sdim Subtarget.isDarwinABI()); 251218885Sdim maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 252218885Sdim 253218885Sdim // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 254218885Sdim // that allocations will be aligned. 255218885Sdim if (MFI->hasVarSizedObjects()) 256218885Sdim maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 257218885Sdim 258218885Sdim // Update maximum call frame size. 259249423Sdim if (UpdateMF) 260249423Sdim MFI->setMaxCallFrameSize(maxCallFrameSize); 261218885Sdim 262218885Sdim // Include call frame size in total. 263218885Sdim FrameSize += maxCallFrameSize; 264218885Sdim 265218885Sdim // Make sure the frame is aligned. 266218885Sdim FrameSize = (FrameSize + AlignMask) & ~AlignMask; 267218885Sdim 268218885Sdim // Update frame info. 269249423Sdim if (UpdateMF) 270249423Sdim MFI->setStackSize(FrameSize); 271249423Sdim 272249423Sdim return FrameSize; 273218885Sdim} 274218885Sdim 275218885Sdim// hasFP - Return true if the specified function actually has a dedicated frame 276218885Sdim// pointer register. 277218885Sdimbool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 278218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 279218885Sdim // FIXME: This is pretty much broken by design: hasFP() might be called really 280218885Sdim // early, before the stack layout was calculated and thus hasFP() might return 281218885Sdim // true or false here depending on the time of call. 282218885Sdim return (MFI->getStackSize()) && needsFP(MF); 283218885Sdim} 284218885Sdim 285218885Sdim// needsFP - Return true if the specified function should have a dedicated frame 286218885Sdim// pointer register. This is true if the function has variable sized allocas or 287218885Sdim// if frame pointer elimination is disabled. 288218885Sdimbool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 289218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 290218885Sdim 291218885Sdim // Naked functions have no stack frame pushed, so we don't have a frame 292218885Sdim // pointer. 293249423Sdim if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 294249423Sdim Attribute::Naked)) 295218885Sdim return false; 296218885Sdim 297234353Sdim return MF.getTarget().Options.DisableFramePointerElim(MF) || 298234353Sdim MFI->hasVarSizedObjects() || 299234353Sdim (MF.getTarget().Options.GuaranteedTailCallOpt && 300234353Sdim MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 301218885Sdim} 302218885Sdim 303249423Sdimvoid PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 304249423Sdim bool is31 = needsFP(MF); 305249423Sdim unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 306249423Sdim unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 307218885Sdim 308249423Sdim for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 309249423Sdim BI != BE; ++BI) 310249423Sdim for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 311249423Sdim --MBBI; 312249423Sdim for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 313249423Sdim MachineOperand &MO = MBBI->getOperand(I); 314249423Sdim if (!MO.isReg()) 315249423Sdim continue; 316249423Sdim 317249423Sdim switch (MO.getReg()) { 318249423Sdim case PPC::FP: 319249423Sdim MO.setReg(FPReg); 320249423Sdim break; 321249423Sdim case PPC::FP8: 322249423Sdim MO.setReg(FP8Reg); 323249423Sdim break; 324249423Sdim } 325249423Sdim } 326249423Sdim } 327249423Sdim} 328249423Sdim 329218885Sdimvoid PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 330218885Sdim MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 331218885Sdim MachineBasicBlock::iterator MBBI = MBB.begin(); 332218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 333218885Sdim const PPCInstrInfo &TII = 334218885Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 335218885Sdim 336218885Sdim MachineModuleInfo &MMI = MF.getMMI(); 337218885Sdim DebugLoc dl; 338218885Sdim bool needsFrameMoves = MMI.hasDebugInfo() || 339223017Sdim MF.getFunction()->needsUnwindTableEntry(); 340218885Sdim 341218885Sdim // Prepare for frame info. 342218885Sdim MCSymbol *FrameLabel = 0; 343218885Sdim 344218885Sdim // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 345218885Sdim // process it. 346243830Sdim if (!Subtarget.isSVR4ABI()) 347243830Sdim for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 348243830Sdim if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 349243830Sdim HandleVRSaveUpdate(MBBI, TII); 350243830Sdim break; 351243830Sdim } 352218885Sdim } 353218885Sdim 354218885Sdim // Move MBBI back to the beginning of the function. 355218885Sdim MBBI = MBB.begin(); 356218885Sdim 357218885Sdim // Work out frame sizes. 358249423Sdim unsigned FrameSize = determineFrameLayout(MF); 359218885Sdim int NegFrameSize = -FrameSize; 360218885Sdim 361249423Sdim if (MFI->isFrameAddressTaken()) 362249423Sdim replaceFPWithRealFP(MF); 363249423Sdim 364218885Sdim // Get processor type. 365218885Sdim bool isPPC64 = Subtarget.isPPC64(); 366218885Sdim // Get operating system 367218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 368218885Sdim // Check if the link register (LR) must be saved. 369218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 370218885Sdim bool MustSaveLR = FI->mustSaveLR(); 371251662Sdim const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs(); 372218885Sdim // Do we have a frame pointer for this function? 373218885Sdim bool HasFP = hasFP(MF); 374218885Sdim 375218885Sdim int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 376218885Sdim 377218885Sdim int FPOffset = 0; 378218885Sdim if (HasFP) { 379218885Sdim if (Subtarget.isSVR4ABI()) { 380218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 381218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 382218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 383218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 384218885Sdim } else { 385218885Sdim FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 386218885Sdim } 387218885Sdim } 388218885Sdim 389218885Sdim if (isPPC64) { 390218885Sdim if (MustSaveLR) 391218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 392218885Sdim 393251662Sdim if (!MustSaveCRs.empty()) { 394251662Sdim MachineInstrBuilder MIB = 395251662Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), PPC::X12); 396251662Sdim for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 397251662Sdim MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 398251662Sdim } 399251662Sdim 400218885Sdim if (HasFP) 401218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 402218885Sdim .addReg(PPC::X31) 403218885Sdim .addImm(FPOffset/4) 404218885Sdim .addReg(PPC::X1); 405218885Sdim 406218885Sdim if (MustSaveLR) 407218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 408218885Sdim .addReg(PPC::X0) 409218885Sdim .addImm(LROffset / 4) 410218885Sdim .addReg(PPC::X1); 411251662Sdim 412251662Sdim if (!MustSaveCRs.empty()) 413251662Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 414251662Sdim .addReg(PPC::X12, getKillRegState(true)) 415251662Sdim .addImm(8) 416251662Sdim .addReg(PPC::X1); 417218885Sdim } else { 418218885Sdim if (MustSaveLR) 419218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 420218885Sdim 421218885Sdim if (HasFP) 422239462Sdim // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 423239462Sdim // offsets of R1 is not allowed. 424218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 425218885Sdim .addReg(PPC::R31) 426218885Sdim .addImm(FPOffset) 427218885Sdim .addReg(PPC::R1); 428218885Sdim 429251662Sdim assert(MustSaveCRs.empty() && 430251662Sdim "Prologue CR saving supported only in 64-bit mode"); 431251662Sdim 432218885Sdim if (MustSaveLR) 433218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 434218885Sdim .addReg(PPC::R0) 435218885Sdim .addImm(LROffset) 436218885Sdim .addReg(PPC::R1); 437218885Sdim } 438218885Sdim 439218885Sdim // Skip if a leaf routine. 440218885Sdim if (!FrameSize) return; 441218885Sdim 442218885Sdim // Get stack alignments. 443218885Sdim unsigned TargetAlign = getStackAlignment(); 444218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 445218885Sdim 446218885Sdim // Adjust stack pointer: r1 += NegFrameSize. 447218885Sdim // If there is a preferred stack alignment, align R1 now 448218885Sdim if (!isPPC64) { 449218885Sdim // PPC32. 450218885Sdim if (ALIGN_STACK && MaxAlign > TargetAlign) { 451218885Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 452218885Sdim "Invalid alignment!"); 453218885Sdim assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 454218885Sdim 455218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 456218885Sdim .addReg(PPC::R1) 457218885Sdim .addImm(0) 458218885Sdim .addImm(32 - Log2_32(MaxAlign)) 459218885Sdim .addImm(31); 460218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 461218885Sdim .addReg(PPC::R0, RegState::Kill) 462218885Sdim .addImm(NegFrameSize); 463239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 464234353Sdim .addReg(PPC::R1, RegState::Kill) 465239462Sdim .addReg(PPC::R1) 466218885Sdim .addReg(PPC::R0); 467218885Sdim } else if (isInt<16>(NegFrameSize)) { 468218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 469218885Sdim .addReg(PPC::R1) 470218885Sdim .addImm(NegFrameSize) 471218885Sdim .addReg(PPC::R1); 472218885Sdim } else { 473218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 474218885Sdim .addImm(NegFrameSize >> 16); 475218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 476218885Sdim .addReg(PPC::R0, RegState::Kill) 477218885Sdim .addImm(NegFrameSize & 0xFFFF); 478239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 479234353Sdim .addReg(PPC::R1, RegState::Kill) 480239462Sdim .addReg(PPC::R1) 481218885Sdim .addReg(PPC::R0); 482218885Sdim } 483218885Sdim } else { // PPC64. 484218885Sdim if (ALIGN_STACK && MaxAlign > TargetAlign) { 485218885Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 486218885Sdim "Invalid alignment!"); 487218885Sdim assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 488218885Sdim 489218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 490218885Sdim .addReg(PPC::X1) 491218885Sdim .addImm(0) 492218885Sdim .addImm(64 - Log2_32(MaxAlign)); 493218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 494218885Sdim .addReg(PPC::X0) 495218885Sdim .addImm(NegFrameSize); 496239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 497234353Sdim .addReg(PPC::X1, RegState::Kill) 498239462Sdim .addReg(PPC::X1) 499218885Sdim .addReg(PPC::X0); 500218885Sdim } else if (isInt<16>(NegFrameSize)) { 501218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 502218885Sdim .addReg(PPC::X1) 503218885Sdim .addImm(NegFrameSize / 4) 504218885Sdim .addReg(PPC::X1); 505218885Sdim } else { 506218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 507218885Sdim .addImm(NegFrameSize >> 16); 508218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 509218885Sdim .addReg(PPC::X0, RegState::Kill) 510218885Sdim .addImm(NegFrameSize & 0xFFFF); 511239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 512234353Sdim .addReg(PPC::X1, RegState::Kill) 513239462Sdim .addReg(PPC::X1) 514218885Sdim .addReg(PPC::X0); 515218885Sdim } 516218885Sdim } 517218885Sdim 518218885Sdim std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 519218885Sdim 520218885Sdim // Add the "machine moves" for the instructions we generated above, but in 521218885Sdim // reverse order. 522218885Sdim if (needsFrameMoves) { 523218885Sdim // Mark effective beginning of when frame pointer becomes valid. 524218885Sdim FrameLabel = MMI.getContext().CreateTempSymbol(); 525218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 526218885Sdim 527218885Sdim // Show update of SP. 528218885Sdim if (NegFrameSize) { 529218885Sdim MachineLocation SPDst(MachineLocation::VirtualFP); 530218885Sdim MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 531218885Sdim Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 532218885Sdim } else { 533218885Sdim MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 534218885Sdim Moves.push_back(MachineMove(FrameLabel, SP, SP)); 535218885Sdim } 536218885Sdim 537218885Sdim if (HasFP) { 538218885Sdim MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 539218885Sdim MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 540218885Sdim Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 541218885Sdim } 542218885Sdim 543218885Sdim if (MustSaveLR) { 544218885Sdim MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 545218885Sdim MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 546218885Sdim Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 547218885Sdim } 548218885Sdim } 549218885Sdim 550218885Sdim MCSymbol *ReadyLabel = 0; 551218885Sdim 552218885Sdim // If there is a frame pointer, copy R1 into R31 553218885Sdim if (HasFP) { 554218885Sdim if (!isPPC64) { 555218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 556218885Sdim .addReg(PPC::R1) 557218885Sdim .addReg(PPC::R1); 558218885Sdim } else { 559218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 560218885Sdim .addReg(PPC::X1) 561218885Sdim .addReg(PPC::X1); 562218885Sdim } 563218885Sdim 564218885Sdim if (needsFrameMoves) { 565218885Sdim ReadyLabel = MMI.getContext().CreateTempSymbol(); 566218885Sdim 567218885Sdim // Mark effective beginning of when frame pointer is ready. 568218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 569218885Sdim 570218885Sdim MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 571218885Sdim (isPPC64 ? PPC::X1 : PPC::R1)); 572218885Sdim MachineLocation FPSrc(MachineLocation::VirtualFP); 573218885Sdim Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 574218885Sdim } 575218885Sdim } 576218885Sdim 577218885Sdim if (needsFrameMoves) { 578218885Sdim MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 579218885Sdim 580218885Sdim // Add callee saved registers to move list. 581218885Sdim const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 582218885Sdim for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 583218885Sdim unsigned Reg = CSI[I].getReg(); 584218885Sdim if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 585223017Sdim 586223017Sdim // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 587223017Sdim // subregisters of CR2. We just need to emit a move of CR2. 588239462Sdim if (PPC::CRBITRCRegClass.contains(Reg)) 589223017Sdim continue; 590223017Sdim 591243830Sdim // For SVR4, don't emit a move for the CR spill slot if we haven't 592243830Sdim // spilled CRs. 593243830Sdim if (Subtarget.isSVR4ABI() 594243830Sdim && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 595251662Sdim && MustSaveCRs.empty()) 596243830Sdim continue; 597243830Sdim 598243830Sdim // For 64-bit SVR4 when we have spilled CRs, the spill location 599243830Sdim // is SP+8, not a frame-relative slot. 600243830Sdim if (Subtarget.isSVR4ABI() 601243830Sdim && Subtarget.isPPC64() 602243830Sdim && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 603243830Sdim MachineLocation CSDst(PPC::X1, 8); 604243830Sdim MachineLocation CSSrc(PPC::CR2); 605243830Sdim Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 606243830Sdim continue; 607243830Sdim } 608243830Sdim 609243830Sdim int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 610218885Sdim MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 611218885Sdim MachineLocation CSSrc(Reg); 612218885Sdim Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 613218885Sdim } 614218885Sdim } 615218885Sdim} 616218885Sdim 617218885Sdimvoid PPCFrameLowering::emitEpilogue(MachineFunction &MF, 618218885Sdim MachineBasicBlock &MBB) const { 619218885Sdim MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 620218885Sdim assert(MBBI != MBB.end() && "Returning block has no terminator"); 621218885Sdim const PPCInstrInfo &TII = 622218885Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 623218885Sdim 624218885Sdim unsigned RetOpcode = MBBI->getOpcode(); 625218885Sdim DebugLoc dl; 626218885Sdim 627218885Sdim assert((RetOpcode == PPC::BLR || 628218885Sdim RetOpcode == PPC::TCRETURNri || 629218885Sdim RetOpcode == PPC::TCRETURNdi || 630218885Sdim RetOpcode == PPC::TCRETURNai || 631218885Sdim RetOpcode == PPC::TCRETURNri8 || 632218885Sdim RetOpcode == PPC::TCRETURNdi8 || 633218885Sdim RetOpcode == PPC::TCRETURNai8) && 634218885Sdim "Can only insert epilog into returning blocks"); 635218885Sdim 636218885Sdim // Get alignment info so we know how to restore r1 637218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 638218885Sdim unsigned TargetAlign = getStackAlignment(); 639218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 640218885Sdim 641218885Sdim // Get the number of bytes allocated from the FrameInfo. 642218885Sdim int FrameSize = MFI->getStackSize(); 643218885Sdim 644218885Sdim // Get processor type. 645218885Sdim bool isPPC64 = Subtarget.isPPC64(); 646218885Sdim // Get operating system 647218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 648218885Sdim // Check if the link register (LR) has been saved. 649218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 650218885Sdim bool MustSaveLR = FI->mustSaveLR(); 651251662Sdim const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs(); 652218885Sdim // Do we have a frame pointer for this function? 653218885Sdim bool HasFP = hasFP(MF); 654218885Sdim 655218885Sdim int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 656218885Sdim 657218885Sdim int FPOffset = 0; 658218885Sdim if (HasFP) { 659218885Sdim if (Subtarget.isSVR4ABI()) { 660218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 661218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 662218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 663218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 664218885Sdim } else { 665218885Sdim FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 666218885Sdim } 667218885Sdim } 668218885Sdim 669218885Sdim bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 670218885Sdim RetOpcode == PPC::TCRETURNdi || 671218885Sdim RetOpcode == PPC::TCRETURNai || 672218885Sdim RetOpcode == PPC::TCRETURNri8 || 673218885Sdim RetOpcode == PPC::TCRETURNdi8 || 674218885Sdim RetOpcode == PPC::TCRETURNai8; 675218885Sdim 676218885Sdim if (UsesTCRet) { 677218885Sdim int MaxTCRetDelta = FI->getTailCallSPDelta(); 678218885Sdim MachineOperand &StackAdjust = MBBI->getOperand(1); 679218885Sdim assert(StackAdjust.isImm() && "Expecting immediate value."); 680218885Sdim // Adjust stack pointer. 681218885Sdim int StackAdj = StackAdjust.getImm(); 682218885Sdim int Delta = StackAdj - MaxTCRetDelta; 683218885Sdim assert((Delta >= 0) && "Delta must be positive"); 684218885Sdim if (MaxTCRetDelta>0) 685218885Sdim FrameSize += (StackAdj +Delta); 686218885Sdim else 687218885Sdim FrameSize += StackAdj; 688218885Sdim } 689218885Sdim 690218885Sdim if (FrameSize) { 691218885Sdim // The loaded (or persistent) stack pointer value is offset by the 'stwu' 692218885Sdim // on entry to the function. Add this offset back now. 693218885Sdim if (!isPPC64) { 694218885Sdim // If this function contained a fastcc call and GuaranteedTailCallOpt is 695218885Sdim // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 696218885Sdim // call which invalidates the stack pointer value in SP(0). So we use the 697218885Sdim // value of R31 in this case. 698218885Sdim if (FI->hasFastCall() && isInt<16>(FrameSize)) { 699218885Sdim assert(hasFP(MF) && "Expecting a valid the frame pointer."); 700218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 701218885Sdim .addReg(PPC::R31).addImm(FrameSize); 702218885Sdim } else if(FI->hasFastCall()) { 703218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 704218885Sdim .addImm(FrameSize >> 16); 705218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 706218885Sdim .addReg(PPC::R0, RegState::Kill) 707218885Sdim .addImm(FrameSize & 0xFFFF); 708218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 709218885Sdim .addReg(PPC::R1) 710218885Sdim .addReg(PPC::R31) 711218885Sdim .addReg(PPC::R0); 712218885Sdim } else if (isInt<16>(FrameSize) && 713218885Sdim (!ALIGN_STACK || TargetAlign >= MaxAlign) && 714218885Sdim !MFI->hasVarSizedObjects()) { 715218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 716218885Sdim .addReg(PPC::R1).addImm(FrameSize); 717218885Sdim } else { 718218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 719218885Sdim .addImm(0).addReg(PPC::R1); 720218885Sdim } 721218885Sdim } else { 722218885Sdim if (FI->hasFastCall() && isInt<16>(FrameSize)) { 723218885Sdim assert(hasFP(MF) && "Expecting a valid the frame pointer."); 724218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 725218885Sdim .addReg(PPC::X31).addImm(FrameSize); 726218885Sdim } else if(FI->hasFastCall()) { 727218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 728218885Sdim .addImm(FrameSize >> 16); 729218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 730218885Sdim .addReg(PPC::X0, RegState::Kill) 731218885Sdim .addImm(FrameSize & 0xFFFF); 732218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 733218885Sdim .addReg(PPC::X1) 734218885Sdim .addReg(PPC::X31) 735218885Sdim .addReg(PPC::X0); 736218885Sdim } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 737218885Sdim !MFI->hasVarSizedObjects()) { 738218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 739218885Sdim .addReg(PPC::X1).addImm(FrameSize); 740218885Sdim } else { 741218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 742218885Sdim .addImm(0).addReg(PPC::X1); 743218885Sdim } 744218885Sdim } 745218885Sdim } 746218885Sdim 747218885Sdim if (isPPC64) { 748218885Sdim if (MustSaveLR) 749218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 750218885Sdim .addImm(LROffset/4).addReg(PPC::X1); 751218885Sdim 752251662Sdim if (!MustSaveCRs.empty()) 753251662Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), PPC::X12) 754251662Sdim .addImm(8).addReg(PPC::X1); 755251662Sdim 756218885Sdim if (HasFP) 757218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 758218885Sdim .addImm(FPOffset/4).addReg(PPC::X1); 759218885Sdim 760251662Sdim if (!MustSaveCRs.empty()) 761251662Sdim for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 762251662Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTCRF8), MustSaveCRs[i]) 763251662Sdim .addReg(PPC::X12, getKillRegState(i == e-1)); 764251662Sdim 765218885Sdim if (MustSaveLR) 766218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 767218885Sdim } else { 768218885Sdim if (MustSaveLR) 769218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 770218885Sdim .addImm(LROffset).addReg(PPC::R1); 771218885Sdim 772251662Sdim assert(MustSaveCRs.empty() && 773251662Sdim "Epilogue CR restoring supported only in 64-bit mode"); 774251662Sdim 775218885Sdim if (HasFP) 776218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 777218885Sdim .addImm(FPOffset).addReg(PPC::R1); 778218885Sdim 779218885Sdim if (MustSaveLR) 780218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 781218885Sdim } 782218885Sdim 783218885Sdim // Callee pop calling convention. Pop parameter/linkage area. Used for tail 784218885Sdim // call optimization 785234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 786218885Sdim MF.getFunction()->getCallingConv() == CallingConv::Fast) { 787218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 788218885Sdim unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 789218885Sdim unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 790218885Sdim unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 791218885Sdim unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 792218885Sdim unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 793218885Sdim unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 794218885Sdim unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 795218885Sdim unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 796218885Sdim 797218885Sdim if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 798218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 799218885Sdim .addReg(StackReg).addImm(CallerAllocatedAmt); 800218885Sdim } else { 801218885Sdim BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 802218885Sdim .addImm(CallerAllocatedAmt >> 16); 803218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 804218885Sdim .addReg(TmpReg, RegState::Kill) 805218885Sdim .addImm(CallerAllocatedAmt & 0xFFFF); 806218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 807218885Sdim .addReg(StackReg) 808218885Sdim .addReg(FPReg) 809218885Sdim .addReg(TmpReg); 810218885Sdim } 811218885Sdim } else if (RetOpcode == PPC::TCRETURNdi) { 812218885Sdim MBBI = MBB.getLastNonDebugInstr(); 813218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 814218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 815218885Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 816218885Sdim } else if (RetOpcode == PPC::TCRETURNri) { 817218885Sdim MBBI = MBB.getLastNonDebugInstr(); 818218885Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 819218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 820218885Sdim } else if (RetOpcode == PPC::TCRETURNai) { 821218885Sdim MBBI = MBB.getLastNonDebugInstr(); 822218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 823218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 824218885Sdim } else if (RetOpcode == PPC::TCRETURNdi8) { 825218885Sdim MBBI = MBB.getLastNonDebugInstr(); 826218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 827218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 828218885Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 829218885Sdim } else if (RetOpcode == PPC::TCRETURNri8) { 830218885Sdim MBBI = MBB.getLastNonDebugInstr(); 831218885Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 832218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 833218885Sdim } else if (RetOpcode == PPC::TCRETURNai8) { 834218885Sdim MBBI = MBB.getLastNonDebugInstr(); 835218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 836218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 837218885Sdim } 838218885Sdim} 839218885Sdim 840218885Sdim/// MustSaveLR - Return true if this function requires that we save the LR 841218885Sdim/// register onto the stack in the prolog and restore it in the epilog of the 842218885Sdim/// function. 843218885Sdimstatic bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 844218885Sdim const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 845218885Sdim 846218885Sdim // We need a save/restore of LR if there is any def of LR (which is 847218885Sdim // defined by calls, including the PIC setup sequence), or if there is 848218885Sdim // some use of the LR stack slot (e.g. for builtin_return_address). 849218885Sdim // (LR comes in 32 and 64 bit versions.) 850218885Sdim MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 851218885Sdim return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 852218885Sdim} 853218885Sdim 854218885Sdimvoid 855218885SdimPPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 856249423Sdim RegScavenger *) const { 857218885Sdim const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 858218885Sdim 859218885Sdim // Save and clear the LR state. 860218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 861218885Sdim unsigned LR = RegInfo->getRARegister(); 862218885Sdim FI->setMustSaveLR(MustSaveLR(MF, LR)); 863249423Sdim MachineRegisterInfo &MRI = MF.getRegInfo(); 864249423Sdim MRI.setPhysRegUnused(LR); 865218885Sdim 866218885Sdim // Save R31 if necessary 867218885Sdim int FPSI = FI->getFramePointerSaveIndex(); 868218885Sdim bool isPPC64 = Subtarget.isPPC64(); 869218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 870218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 871218885Sdim 872218885Sdim // If the frame pointer save index hasn't been defined yet. 873218885Sdim if (!FPSI && needsFP(MF)) { 874218885Sdim // Find out what the fix offset of the frame pointer save area. 875218885Sdim int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 876218885Sdim // Allocate the frame index for frame pointer save area. 877218885Sdim FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 878218885Sdim // Save the result. 879218885Sdim FI->setFramePointerSaveIndex(FPSI); 880218885Sdim } 881218885Sdim 882218885Sdim // Reserve stack space to move the linkage area to in case of a tail call. 883218885Sdim int TCSPDelta = 0; 884234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 885234353Sdim (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 886218885Sdim MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 887218885Sdim } 888218885Sdim 889249423Sdim // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 890249423Sdim // function uses CR 2, 3, or 4. 891249423Sdim if (!isPPC64 && !isDarwinABI && 892249423Sdim (MRI.isPhysRegUsed(PPC::CR2) || 893249423Sdim MRI.isPhysRegUsed(PPC::CR3) || 894249423Sdim MRI.isPhysRegUsed(PPC::CR4))) { 895249423Sdim int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 896249423Sdim FI->setCRSpillFrameIndex(FrameIdx); 897249423Sdim } 898218885Sdim} 899218885Sdim 900249423Sdimvoid PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 901249423Sdim RegScavenger *RS) const { 902218885Sdim // Early exit if not using the SVR4 ABI. 903249423Sdim if (!Subtarget.isSVR4ABI()) { 904249423Sdim addScavengingSpillSlot(MF, RS); 905218885Sdim return; 906249423Sdim } 907218885Sdim 908218885Sdim // Get callee saved register information. 909218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 910218885Sdim const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 911218885Sdim 912218885Sdim // Early exit if no callee saved registers are modified! 913218885Sdim if (CSI.empty() && !needsFP(MF)) { 914249423Sdim addScavengingSpillSlot(MF, RS); 915218885Sdim return; 916218885Sdim } 917218885Sdim 918218885Sdim unsigned MinGPR = PPC::R31; 919218885Sdim unsigned MinG8R = PPC::X31; 920218885Sdim unsigned MinFPR = PPC::F31; 921218885Sdim unsigned MinVR = PPC::V31; 922218885Sdim 923218885Sdim bool HasGPSaveArea = false; 924218885Sdim bool HasG8SaveArea = false; 925218885Sdim bool HasFPSaveArea = false; 926218885Sdim bool HasVRSAVESaveArea = false; 927218885Sdim bool HasVRSaveArea = false; 928218885Sdim 929218885Sdim SmallVector<CalleeSavedInfo, 18> GPRegs; 930218885Sdim SmallVector<CalleeSavedInfo, 18> G8Regs; 931218885Sdim SmallVector<CalleeSavedInfo, 18> FPRegs; 932218885Sdim SmallVector<CalleeSavedInfo, 18> VRegs; 933218885Sdim 934218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 935218885Sdim unsigned Reg = CSI[i].getReg(); 936239462Sdim if (PPC::GPRCRegClass.contains(Reg)) { 937218885Sdim HasGPSaveArea = true; 938218885Sdim 939218885Sdim GPRegs.push_back(CSI[i]); 940218885Sdim 941218885Sdim if (Reg < MinGPR) { 942218885Sdim MinGPR = Reg; 943218885Sdim } 944239462Sdim } else if (PPC::G8RCRegClass.contains(Reg)) { 945218885Sdim HasG8SaveArea = true; 946218885Sdim 947218885Sdim G8Regs.push_back(CSI[i]); 948218885Sdim 949218885Sdim if (Reg < MinG8R) { 950218885Sdim MinG8R = Reg; 951218885Sdim } 952239462Sdim } else if (PPC::F8RCRegClass.contains(Reg)) { 953218885Sdim HasFPSaveArea = true; 954218885Sdim 955218885Sdim FPRegs.push_back(CSI[i]); 956218885Sdim 957218885Sdim if (Reg < MinFPR) { 958218885Sdim MinFPR = Reg; 959218885Sdim } 960239462Sdim } else if (PPC::CRBITRCRegClass.contains(Reg) || 961239462Sdim PPC::CRRCRegClass.contains(Reg)) { 962243830Sdim ; // do nothing, as we already know whether CRs are spilled 963239462Sdim } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 964218885Sdim HasVRSAVESaveArea = true; 965239462Sdim } else if (PPC::VRRCRegClass.contains(Reg)) { 966218885Sdim HasVRSaveArea = true; 967218885Sdim 968218885Sdim VRegs.push_back(CSI[i]); 969218885Sdim 970218885Sdim if (Reg < MinVR) { 971218885Sdim MinVR = Reg; 972218885Sdim } 973218885Sdim } else { 974218885Sdim llvm_unreachable("Unknown RegisterClass!"); 975218885Sdim } 976218885Sdim } 977218885Sdim 978218885Sdim PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 979249423Sdim const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 980218885Sdim 981218885Sdim int64_t LowerBound = 0; 982218885Sdim 983218885Sdim // Take into account stack space reserved for tail calls. 984218885Sdim int TCSPDelta = 0; 985234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 986234353Sdim (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 987218885Sdim LowerBound = TCSPDelta; 988218885Sdim } 989218885Sdim 990218885Sdim // The Floating-point register save area is right below the back chain word 991218885Sdim // of the previous stack frame. 992218885Sdim if (HasFPSaveArea) { 993218885Sdim for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 994218885Sdim int FI = FPRegs[i].getFrameIdx(); 995218885Sdim 996218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 997218885Sdim } 998218885Sdim 999249423Sdim LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1000218885Sdim } 1001218885Sdim 1002218885Sdim // Check whether the frame pointer register is allocated. If so, make sure it 1003218885Sdim // is spilled to the correct offset. 1004218885Sdim if (needsFP(MF)) { 1005218885Sdim HasGPSaveArea = true; 1006218885Sdim 1007218885Sdim int FI = PFI->getFramePointerSaveIndex(); 1008218885Sdim assert(FI && "No Frame Pointer Save Slot!"); 1009218885Sdim 1010218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1011218885Sdim } 1012218885Sdim 1013218885Sdim // General register save area starts right below the Floating-point 1014218885Sdim // register save area. 1015218885Sdim if (HasGPSaveArea || HasG8SaveArea) { 1016218885Sdim // Move general register save area spill slots down, taking into account 1017218885Sdim // the size of the Floating-point register save area. 1018218885Sdim for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1019218885Sdim int FI = GPRegs[i].getFrameIdx(); 1020218885Sdim 1021218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1022218885Sdim } 1023218885Sdim 1024218885Sdim // Move general register save area spill slots down, taking into account 1025218885Sdim // the size of the Floating-point register save area. 1026218885Sdim for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1027218885Sdim int FI = G8Regs[i].getFrameIdx(); 1028218885Sdim 1029218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1030218885Sdim } 1031218885Sdim 1032218885Sdim unsigned MinReg = 1033249423Sdim std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1034249423Sdim TRI->getEncodingValue(MinG8R)); 1035218885Sdim 1036218885Sdim if (Subtarget.isPPC64()) { 1037218885Sdim LowerBound -= (31 - MinReg + 1) * 8; 1038218885Sdim } else { 1039218885Sdim LowerBound -= (31 - MinReg + 1) * 4; 1040218885Sdim } 1041218885Sdim } 1042218885Sdim 1043243830Sdim // For 32-bit only, the CR save area is below the general register 1044243830Sdim // save area. For 64-bit SVR4, the CR save area is addressed relative 1045243830Sdim // to the stack pointer and hence does not need an adjustment here. 1046243830Sdim // Only CR2 (the first nonvolatile spilled) has an associated frame 1047243830Sdim // index so that we have a single uniform save area. 1048243830Sdim if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1049218885Sdim // Adjust the frame index of the CR spill slot. 1050218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1051218885Sdim unsigned Reg = CSI[i].getReg(); 1052218885Sdim 1053243830Sdim if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1054243830Sdim // Leave Darwin logic as-is. 1055243830Sdim || (!Subtarget.isSVR4ABI() && 1056243830Sdim (PPC::CRBITRCRegClass.contains(Reg) || 1057243830Sdim PPC::CRRCRegClass.contains(Reg)))) { 1058218885Sdim int FI = CSI[i].getFrameIdx(); 1059218885Sdim 1060218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1061218885Sdim } 1062218885Sdim } 1063218885Sdim 1064218885Sdim LowerBound -= 4; // The CR save area is always 4 bytes long. 1065218885Sdim } 1066218885Sdim 1067218885Sdim if (HasVRSAVESaveArea) { 1068218885Sdim // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1069218885Sdim // which have the VRSAVE register class? 1070218885Sdim // Adjust the frame index of the VRSAVE spill slot. 1071218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1072218885Sdim unsigned Reg = CSI[i].getReg(); 1073218885Sdim 1074239462Sdim if (PPC::VRSAVERCRegClass.contains(Reg)) { 1075218885Sdim int FI = CSI[i].getFrameIdx(); 1076218885Sdim 1077218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1078218885Sdim } 1079218885Sdim } 1080218885Sdim 1081218885Sdim LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1082218885Sdim } 1083218885Sdim 1084218885Sdim if (HasVRSaveArea) { 1085218885Sdim // Insert alignment padding, we need 16-byte alignment. 1086218885Sdim LowerBound = (LowerBound - 15) & ~(15); 1087218885Sdim 1088218885Sdim for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1089218885Sdim int FI = VRegs[i].getFrameIdx(); 1090218885Sdim 1091218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1092218885Sdim } 1093218885Sdim } 1094249423Sdim 1095249423Sdim addScavengingSpillSlot(MF, RS); 1096218885Sdim} 1097243830Sdim 1098249423Sdimvoid 1099249423SdimPPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1100249423Sdim RegScavenger *RS) const { 1101249423Sdim // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1102249423Sdim // a large stack, which will require scavenging a register to materialize a 1103249423Sdim // large offset. 1104249423Sdim 1105249423Sdim // We need to have a scavenger spill slot for spills if the frame size is 1106249423Sdim // large. In case there is no free register for large-offset addressing, 1107249423Sdim // this slot is used for the necessary emergency spill. Also, we need the 1108249423Sdim // slot for dynamic stack allocations. 1109249423Sdim 1110249423Sdim // The scavenger might be invoked if the frame offset does not fit into 1111249423Sdim // the 16-bit immediate. We don't know the complete frame size here 1112249423Sdim // because we've not yet computed callee-saved register spills or the 1113249423Sdim // needed alignment padding. 1114249423Sdim unsigned StackSize = determineFrameLayout(MF, false, true); 1115249423Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1116249423Sdim if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1117249423Sdim hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1118249423Sdim const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1119249423Sdim const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1120249423Sdim const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1121249423Sdim RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1122249423Sdim RC->getAlignment(), 1123249423Sdim false)); 1124249423Sdim 1125249423Sdim // These kinds of spills might need two registers. 1126249423Sdim if (spillsCR(MF) || spillsVRSAVE(MF)) 1127249423Sdim RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1128249423Sdim RC->getAlignment(), 1129249423Sdim false)); 1130249423Sdim 1131249423Sdim } 1132249423Sdim} 1133249423Sdim 1134243830Sdimbool 1135243830SdimPPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1136243830Sdim MachineBasicBlock::iterator MI, 1137243830Sdim const std::vector<CalleeSavedInfo> &CSI, 1138243830Sdim const TargetRegisterInfo *TRI) const { 1139243830Sdim 1140243830Sdim // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1141243830Sdim // Return false otherwise to maintain pre-existing behavior. 1142243830Sdim if (!Subtarget.isSVR4ABI()) 1143243830Sdim return false; 1144243830Sdim 1145243830Sdim MachineFunction *MF = MBB.getParent(); 1146243830Sdim const PPCInstrInfo &TII = 1147243830Sdim *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1148243830Sdim DebugLoc DL; 1149243830Sdim bool CRSpilled = false; 1150251662Sdim MachineInstrBuilder CRMIB; 1151243830Sdim 1152243830Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1153243830Sdim unsigned Reg = CSI[i].getReg(); 1154243830Sdim // CR2 through CR4 are the nonvolatile CR fields. 1155243830Sdim bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1156243830Sdim 1157243830Sdim // Add the callee-saved register as live-in; it's killed at the spill. 1158243830Sdim MBB.addLiveIn(Reg); 1159243830Sdim 1160251662Sdim if (CRSpilled && IsCRField) { 1161251662Sdim CRMIB.addReg(Reg, RegState::ImplicitKill); 1162251662Sdim continue; 1163251662Sdim } 1164251662Sdim 1165243830Sdim // Insert the spill to the stack frame. 1166243830Sdim if (IsCRField) { 1167251662Sdim PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1168243830Sdim if (Subtarget.isPPC64()) { 1169251662Sdim // The actual spill will happen at the start of the prologue. 1170251662Sdim FuncInfo->addMustSaveCR(Reg); 1171243830Sdim } else { 1172251662Sdim CRSpilled = true; 1173251662Sdim FuncInfo->setSpillsCR(); 1174251662Sdim 1175243830Sdim // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1176243830Sdim // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1177251662Sdim CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1178251662Sdim .addReg(Reg, RegState::ImplicitKill); 1179251662Sdim 1180251662Sdim MBB.insert(MI, CRMIB); 1181243830Sdim MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1182243830Sdim .addReg(PPC::R12, 1183243830Sdim getKillRegState(true)), 1184243830Sdim CSI[i].getFrameIdx())); 1185243830Sdim } 1186243830Sdim } else { 1187243830Sdim const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1188243830Sdim TII.storeRegToStackSlot(MBB, MI, Reg, true, 1189243830Sdim CSI[i].getFrameIdx(), RC, TRI); 1190243830Sdim } 1191243830Sdim } 1192243830Sdim return true; 1193243830Sdim} 1194243830Sdim 1195243830Sdimstatic void 1196251662SdimrestoreCRs(bool isPPC64, bool is31, 1197251662Sdim bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1198243830Sdim MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1199243830Sdim const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1200243830Sdim 1201243830Sdim MachineFunction *MF = MBB.getParent(); 1202243830Sdim const PPCInstrInfo &TII = 1203243830Sdim *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1204243830Sdim DebugLoc DL; 1205243830Sdim unsigned RestoreOp, MoveReg; 1206243830Sdim 1207251662Sdim if (isPPC64) 1208251662Sdim // This is handled during epilogue generation. 1209251662Sdim return; 1210251662Sdim else { 1211243830Sdim // 32-bit: FP-relative 1212243830Sdim MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1213243830Sdim PPC::R12), 1214243830Sdim CSI[CSIIndex].getFrameIdx())); 1215243830Sdim RestoreOp = PPC::MTCRF; 1216243830Sdim MoveReg = PPC::R12; 1217243830Sdim } 1218243830Sdim 1219243830Sdim if (CR2Spilled) 1220243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1221249423Sdim .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1222243830Sdim 1223243830Sdim if (CR3Spilled) 1224243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1225249423Sdim .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1226243830Sdim 1227243830Sdim if (CR4Spilled) 1228243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1229249423Sdim .addReg(MoveReg, getKillRegState(true))); 1230243830Sdim} 1231243830Sdim 1232249423Sdimvoid PPCFrameLowering:: 1233249423SdimeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1234249423Sdim MachineBasicBlock::iterator I) const { 1235249423Sdim const PPCInstrInfo &TII = 1236249423Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1237249423Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 1238249423Sdim I->getOpcode() == PPC::ADJCALLSTACKUP) { 1239249423Sdim // Add (actually subtract) back the amount the callee popped on return. 1240249423Sdim if (int CalleeAmt = I->getOperand(1).getImm()) { 1241249423Sdim bool is64Bit = Subtarget.isPPC64(); 1242249423Sdim CalleeAmt *= -1; 1243249423Sdim unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1244249423Sdim unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1245249423Sdim unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1246249423Sdim unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1247249423Sdim unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1248249423Sdim unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1249249423Sdim MachineInstr *MI = I; 1250249423Sdim DebugLoc dl = MI->getDebugLoc(); 1251249423Sdim 1252249423Sdim if (isInt<16>(CalleeAmt)) { 1253249423Sdim BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1254249423Sdim .addReg(StackReg, RegState::Kill) 1255249423Sdim .addImm(CalleeAmt); 1256249423Sdim } else { 1257249423Sdim MachineBasicBlock::iterator MBBI = I; 1258249423Sdim BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1259249423Sdim .addImm(CalleeAmt >> 16); 1260249423Sdim BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1261249423Sdim .addReg(TmpReg, RegState::Kill) 1262249423Sdim .addImm(CalleeAmt & 0xFFFF); 1263249423Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1264249423Sdim .addReg(StackReg, RegState::Kill) 1265249423Sdim .addReg(TmpReg); 1266249423Sdim } 1267249423Sdim } 1268249423Sdim } 1269249423Sdim // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1270249423Sdim MBB.erase(I); 1271249423Sdim} 1272249423Sdim 1273243830Sdimbool 1274243830SdimPPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1275243830Sdim MachineBasicBlock::iterator MI, 1276243830Sdim const std::vector<CalleeSavedInfo> &CSI, 1277243830Sdim const TargetRegisterInfo *TRI) const { 1278243830Sdim 1279243830Sdim // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1280243830Sdim // Return false otherwise to maintain pre-existing behavior. 1281243830Sdim if (!Subtarget.isSVR4ABI()) 1282243830Sdim return false; 1283243830Sdim 1284243830Sdim MachineFunction *MF = MBB.getParent(); 1285243830Sdim const PPCInstrInfo &TII = 1286243830Sdim *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1287243830Sdim bool CR2Spilled = false; 1288243830Sdim bool CR3Spilled = false; 1289243830Sdim bool CR4Spilled = false; 1290243830Sdim unsigned CSIIndex = 0; 1291243830Sdim 1292243830Sdim // Initialize insertion-point logic; we will be restoring in reverse 1293243830Sdim // order of spill. 1294243830Sdim MachineBasicBlock::iterator I = MI, BeforeI = I; 1295243830Sdim bool AtStart = I == MBB.begin(); 1296243830Sdim 1297243830Sdim if (!AtStart) 1298243830Sdim --BeforeI; 1299243830Sdim 1300243830Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1301243830Sdim unsigned Reg = CSI[i].getReg(); 1302243830Sdim 1303243830Sdim if (Reg == PPC::CR2) { 1304243830Sdim CR2Spilled = true; 1305243830Sdim // The spill slot is associated only with CR2, which is the 1306243830Sdim // first nonvolatile spilled. Save it here. 1307243830Sdim CSIIndex = i; 1308243830Sdim continue; 1309243830Sdim } else if (Reg == PPC::CR3) { 1310243830Sdim CR3Spilled = true; 1311243830Sdim continue; 1312243830Sdim } else if (Reg == PPC::CR4) { 1313243830Sdim CR4Spilled = true; 1314243830Sdim continue; 1315243830Sdim } else { 1316243830Sdim // When we first encounter a non-CR register after seeing at 1317243830Sdim // least one CR register, restore all spilled CRs together. 1318243830Sdim if ((CR2Spilled || CR3Spilled || CR4Spilled) 1319243830Sdim && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1320251662Sdim bool is31 = needsFP(*MF); 1321251662Sdim restoreCRs(Subtarget.isPPC64(), is31, 1322251662Sdim CR2Spilled, CR3Spilled, CR4Spilled, 1323243830Sdim MBB, I, CSI, CSIIndex); 1324243830Sdim CR2Spilled = CR3Spilled = CR4Spilled = false; 1325243830Sdim } 1326243830Sdim 1327243830Sdim // Default behavior for non-CR saves. 1328243830Sdim const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1329243830Sdim TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1330243830Sdim RC, TRI); 1331243830Sdim assert(I != MBB.begin() && 1332243830Sdim "loadRegFromStackSlot didn't insert any code!"); 1333243830Sdim } 1334243830Sdim 1335243830Sdim // Insert in reverse order. 1336243830Sdim if (AtStart) 1337243830Sdim I = MBB.begin(); 1338243830Sdim else { 1339243830Sdim I = BeforeI; 1340243830Sdim ++I; 1341243830Sdim } 1342243830Sdim } 1343243830Sdim 1344243830Sdim // If we haven't yet spilled the CRs, do so now. 1345251662Sdim if (CR2Spilled || CR3Spilled || CR4Spilled) { 1346251662Sdim bool is31 = needsFP(*MF); 1347251662Sdim restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1348243830Sdim MBB, I, CSI, CSIIndex); 1349251662Sdim } 1350243830Sdim 1351243830Sdim return true; 1352243830Sdim} 1353243830Sdim 1354