PPCFrameLowering.cpp revision 251662
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrBuilder.h" 16#include "PPCInstrInfo.h" 17#include "PPCMachineFunctionInfo.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/MachineModuleInfo.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/RegisterScavenging.h" 24#include "llvm/IR/Function.h" 25#include "llvm/Target/TargetOptions.h" 26 27using namespace llvm; 28 29// FIXME This disables some code that aligns the stack to a boundary bigger than 30// the default (16 bytes on Darwin) when there is a stack local of greater 31// alignment. This does not currently work, because the delta between old and 32// new stack pointers is added to offsets that reference incoming parameters 33// after the prolog is generated, and the code that does that doesn't handle a 34// variable delta. You don't want to do that anyway; a better approach is to 35// reserve another register that retains to the incoming stack pointer, and 36// reference parameters relative to that. 37#define ALIGN_STACK 0 38 39 40/// VRRegNo - Map from a numbered VR register to its enum value. 41/// 42static const uint16_t VRRegNo[] = { 43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47}; 48 49/// RemoveVRSaveCode - We have found that this function does not need any code 50/// to manipulate the VRSAVE register, even though it uses vector registers. 51/// This can happen when the only registers used are known to be live in or out 52/// of the function. Remove all of the VRSAVE related code from the function. 53/// FIXME: The removal of the code results in a compile failure at -O0 when the 54/// function contains a function call, as the GPR containing original VRSAVE 55/// contents is spilled and reloaded around the call. Without the prolog code, 56/// the spill instruction refers to an undefined register. This code needs 57/// to account for all uses of that GPR. 58static void RemoveVRSaveCode(MachineInstr *MI) { 59 MachineBasicBlock *Entry = MI->getParent(); 60 MachineFunction *MF = Entry->getParent(); 61 62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63 MachineBasicBlock::iterator MBBI = MI; 64 ++MBBI; 65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66 MBBI->eraseFromParent(); 67 68 bool RemovedAllMTVRSAVEs = true; 69 // See if we can find and remove the MTVRSAVE instruction from all of the 70 // epilog blocks. 71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72 // If last instruction is a return instruction, add an epilogue 73 if (!I->empty() && I->back().isReturn()) { 74 bool FoundIt = false; 75 for (MBBI = I->end(); MBBI != I->begin(); ) { 76 --MBBI; 77 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78 MBBI->eraseFromParent(); // remove it. 79 FoundIt = true; 80 break; 81 } 82 } 83 RemovedAllMTVRSAVEs &= FoundIt; 84 } 85 } 86 87 // If we found and removed all MTVRSAVE instructions, remove the read of 88 // VRSAVE as well. 89 if (RemovedAllMTVRSAVEs) { 90 MBBI = MI; 91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92 --MBBI; 93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94 MBBI->eraseFromParent(); 95 } 96 97 // Finally, nuke the UPDATE_VRSAVE. 98 MI->eraseFromParent(); 99} 100 101// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102// instruction selector. Based on the vector registers that have been used, 103// transform this into the appropriate ORI instruction. 104static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105 MachineFunction *MF = MI->getParent()->getParent(); 106 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 107 DebugLoc dl = MI->getDebugLoc(); 108 109 unsigned UsedRegMask = 0; 110 for (unsigned i = 0; i != 32; ++i) 111 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 112 UsedRegMask |= 1 << (31-i); 113 114 // Live in and live out values already must be in the mask, so don't bother 115 // marking them. 116 for (MachineRegisterInfo::livein_iterator 117 I = MF->getRegInfo().livein_begin(), 118 E = MF->getRegInfo().livein_end(); I != E; ++I) { 119 unsigned RegNo = TRI->getEncodingValue(I->first); 120 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122 } 123 124 // Live out registers appear as use operands on return instructions. 125 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 126 UsedRegMask != 0 && BI != BE; ++BI) { 127 const MachineBasicBlock &MBB = *BI; 128 if (MBB.empty() || !MBB.back().isReturn()) 129 continue; 130 const MachineInstr &Ret = MBB.back(); 131 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 132 const MachineOperand &MO = Ret.getOperand(I); 133 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 134 continue; 135 unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 136 UsedRegMask &= ~(1 << (31-RegNo)); 137 } 138 } 139 140 // If no registers are used, turn this into a copy. 141 if (UsedRegMask == 0) { 142 // Remove all VRSAVE code. 143 RemoveVRSaveCode(MI); 144 return; 145 } 146 147 unsigned SrcReg = MI->getOperand(1).getReg(); 148 unsigned DstReg = MI->getOperand(0).getReg(); 149 150 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 151 if (DstReg != SrcReg) 152 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 153 .addReg(SrcReg) 154 .addImm(UsedRegMask); 155 else 156 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 157 .addReg(SrcReg, RegState::Kill) 158 .addImm(UsedRegMask); 159 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 160 if (DstReg != SrcReg) 161 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 162 .addReg(SrcReg) 163 .addImm(UsedRegMask >> 16); 164 else 165 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 166 .addReg(SrcReg, RegState::Kill) 167 .addImm(UsedRegMask >> 16); 168 } else { 169 if (DstReg != SrcReg) 170 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 171 .addReg(SrcReg) 172 .addImm(UsedRegMask >> 16); 173 else 174 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 175 .addReg(SrcReg, RegState::Kill) 176 .addImm(UsedRegMask >> 16); 177 178 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 179 .addReg(DstReg, RegState::Kill) 180 .addImm(UsedRegMask & 0xFFFF); 181 } 182 183 // Remove the old UPDATE_VRSAVE instruction. 184 MI->eraseFromParent(); 185} 186 187static bool spillsCR(const MachineFunction &MF) { 188 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 189 return FuncInfo->isCRSpilled(); 190} 191 192static bool spillsVRSAVE(const MachineFunction &MF) { 193 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 194 return FuncInfo->isVRSAVESpilled(); 195} 196 197static bool hasSpills(const MachineFunction &MF) { 198 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 199 return FuncInfo->hasSpills(); 200} 201 202static bool hasNonRISpills(const MachineFunction &MF) { 203 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 204 return FuncInfo->hasNonRISpills(); 205} 206 207/// determineFrameLayout - Determine the size of the frame and maximum call 208/// frame size. 209unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 210 bool UpdateMF, 211 bool UseEstimate) const { 212 MachineFrameInfo *MFI = MF.getFrameInfo(); 213 214 // Get the number of bytes to allocate from the FrameInfo 215 unsigned FrameSize = 216 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 217 218 // Get the alignments provided by the target, and the maximum alignment 219 // (if any) of the fixed frame objects. 220 unsigned MaxAlign = MFI->getMaxAlignment(); 221 unsigned TargetAlign = getStackAlignment(); 222 unsigned AlignMask = TargetAlign - 1; // 223 224 // If we are a leaf function, and use up to 224 bytes of stack space, 225 // don't have a frame pointer, calls, or dynamic alloca then we do not need 226 // to adjust the stack pointer (we fit in the Red Zone). 227 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 228 // stackless code if all local vars are reg-allocated. 229 bool DisableRedZone = MF.getFunction()->getAttributes(). 230 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 231 if (!DisableRedZone && 232 (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 233 !Subtarget.isSVR4ABI() || // allocated locals. 234 FrameSize == 0) && 235 FrameSize <= 224 && // Fits in red zone. 236 !MFI->hasVarSizedObjects() && // No dynamic alloca. 237 !MFI->adjustsStack() && // No calls. 238 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 239 // No need for frame 240 if (UpdateMF) 241 MFI->setStackSize(0); 242 return 0; 243 } 244 245 // Get the maximum call frame size of all the calls. 246 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 247 248 // Maximum call frame needs to be at least big enough for linkage and 8 args. 249 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 250 Subtarget.isDarwinABI()); 251 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 252 253 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 254 // that allocations will be aligned. 255 if (MFI->hasVarSizedObjects()) 256 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 257 258 // Update maximum call frame size. 259 if (UpdateMF) 260 MFI->setMaxCallFrameSize(maxCallFrameSize); 261 262 // Include call frame size in total. 263 FrameSize += maxCallFrameSize; 264 265 // Make sure the frame is aligned. 266 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 267 268 // Update frame info. 269 if (UpdateMF) 270 MFI->setStackSize(FrameSize); 271 272 return FrameSize; 273} 274 275// hasFP - Return true if the specified function actually has a dedicated frame 276// pointer register. 277bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 278 const MachineFrameInfo *MFI = MF.getFrameInfo(); 279 // FIXME: This is pretty much broken by design: hasFP() might be called really 280 // early, before the stack layout was calculated and thus hasFP() might return 281 // true or false here depending on the time of call. 282 return (MFI->getStackSize()) && needsFP(MF); 283} 284 285// needsFP - Return true if the specified function should have a dedicated frame 286// pointer register. This is true if the function has variable sized allocas or 287// if frame pointer elimination is disabled. 288bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 289 const MachineFrameInfo *MFI = MF.getFrameInfo(); 290 291 // Naked functions have no stack frame pushed, so we don't have a frame 292 // pointer. 293 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 294 Attribute::Naked)) 295 return false; 296 297 return MF.getTarget().Options.DisableFramePointerElim(MF) || 298 MFI->hasVarSizedObjects() || 299 (MF.getTarget().Options.GuaranteedTailCallOpt && 300 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 301} 302 303void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 304 bool is31 = needsFP(MF); 305 unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 306 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 307 308 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 309 BI != BE; ++BI) 310 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 311 --MBBI; 312 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 313 MachineOperand &MO = MBBI->getOperand(I); 314 if (!MO.isReg()) 315 continue; 316 317 switch (MO.getReg()) { 318 case PPC::FP: 319 MO.setReg(FPReg); 320 break; 321 case PPC::FP8: 322 MO.setReg(FP8Reg); 323 break; 324 } 325 } 326 } 327} 328 329void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 330 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 331 MachineBasicBlock::iterator MBBI = MBB.begin(); 332 MachineFrameInfo *MFI = MF.getFrameInfo(); 333 const PPCInstrInfo &TII = 334 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 335 336 MachineModuleInfo &MMI = MF.getMMI(); 337 DebugLoc dl; 338 bool needsFrameMoves = MMI.hasDebugInfo() || 339 MF.getFunction()->needsUnwindTableEntry(); 340 341 // Prepare for frame info. 342 MCSymbol *FrameLabel = 0; 343 344 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 345 // process it. 346 if (!Subtarget.isSVR4ABI()) 347 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 348 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 349 HandleVRSaveUpdate(MBBI, TII); 350 break; 351 } 352 } 353 354 // Move MBBI back to the beginning of the function. 355 MBBI = MBB.begin(); 356 357 // Work out frame sizes. 358 unsigned FrameSize = determineFrameLayout(MF); 359 int NegFrameSize = -FrameSize; 360 361 if (MFI->isFrameAddressTaken()) 362 replaceFPWithRealFP(MF); 363 364 // Get processor type. 365 bool isPPC64 = Subtarget.isPPC64(); 366 // Get operating system 367 bool isDarwinABI = Subtarget.isDarwinABI(); 368 // Check if the link register (LR) must be saved. 369 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 370 bool MustSaveLR = FI->mustSaveLR(); 371 const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs(); 372 // Do we have a frame pointer for this function? 373 bool HasFP = hasFP(MF); 374 375 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 376 377 int FPOffset = 0; 378 if (HasFP) { 379 if (Subtarget.isSVR4ABI()) { 380 MachineFrameInfo *FFI = MF.getFrameInfo(); 381 int FPIndex = FI->getFramePointerSaveIndex(); 382 assert(FPIndex && "No Frame Pointer Save Slot!"); 383 FPOffset = FFI->getObjectOffset(FPIndex); 384 } else { 385 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 386 } 387 } 388 389 if (isPPC64) { 390 if (MustSaveLR) 391 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 392 393 if (!MustSaveCRs.empty()) { 394 MachineInstrBuilder MIB = 395 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), PPC::X12); 396 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 397 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); 398 } 399 400 if (HasFP) 401 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 402 .addReg(PPC::X31) 403 .addImm(FPOffset/4) 404 .addReg(PPC::X1); 405 406 if (MustSaveLR) 407 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 408 .addReg(PPC::X0) 409 .addImm(LROffset / 4) 410 .addReg(PPC::X1); 411 412 if (!MustSaveCRs.empty()) 413 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8)) 414 .addReg(PPC::X12, getKillRegState(true)) 415 .addImm(8) 416 .addReg(PPC::X1); 417 } else { 418 if (MustSaveLR) 419 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 420 421 if (HasFP) 422 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 423 // offsets of R1 is not allowed. 424 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 425 .addReg(PPC::R31) 426 .addImm(FPOffset) 427 .addReg(PPC::R1); 428 429 assert(MustSaveCRs.empty() && 430 "Prologue CR saving supported only in 64-bit mode"); 431 432 if (MustSaveLR) 433 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 434 .addReg(PPC::R0) 435 .addImm(LROffset) 436 .addReg(PPC::R1); 437 } 438 439 // Skip if a leaf routine. 440 if (!FrameSize) return; 441 442 // Get stack alignments. 443 unsigned TargetAlign = getStackAlignment(); 444 unsigned MaxAlign = MFI->getMaxAlignment(); 445 446 // Adjust stack pointer: r1 += NegFrameSize. 447 // If there is a preferred stack alignment, align R1 now 448 if (!isPPC64) { 449 // PPC32. 450 if (ALIGN_STACK && MaxAlign > TargetAlign) { 451 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 452 "Invalid alignment!"); 453 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 454 455 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 456 .addReg(PPC::R1) 457 .addImm(0) 458 .addImm(32 - Log2_32(MaxAlign)) 459 .addImm(31); 460 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 461 .addReg(PPC::R0, RegState::Kill) 462 .addImm(NegFrameSize); 463 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 464 .addReg(PPC::R1, RegState::Kill) 465 .addReg(PPC::R1) 466 .addReg(PPC::R0); 467 } else if (isInt<16>(NegFrameSize)) { 468 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 469 .addReg(PPC::R1) 470 .addImm(NegFrameSize) 471 .addReg(PPC::R1); 472 } else { 473 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 474 .addImm(NegFrameSize >> 16); 475 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 476 .addReg(PPC::R0, RegState::Kill) 477 .addImm(NegFrameSize & 0xFFFF); 478 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 479 .addReg(PPC::R1, RegState::Kill) 480 .addReg(PPC::R1) 481 .addReg(PPC::R0); 482 } 483 } else { // PPC64. 484 if (ALIGN_STACK && MaxAlign > TargetAlign) { 485 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 486 "Invalid alignment!"); 487 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 488 489 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 490 .addReg(PPC::X1) 491 .addImm(0) 492 .addImm(64 - Log2_32(MaxAlign)); 493 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 494 .addReg(PPC::X0) 495 .addImm(NegFrameSize); 496 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 497 .addReg(PPC::X1, RegState::Kill) 498 .addReg(PPC::X1) 499 .addReg(PPC::X0); 500 } else if (isInt<16>(NegFrameSize)) { 501 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 502 .addReg(PPC::X1) 503 .addImm(NegFrameSize / 4) 504 .addReg(PPC::X1); 505 } else { 506 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 507 .addImm(NegFrameSize >> 16); 508 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 509 .addReg(PPC::X0, RegState::Kill) 510 .addImm(NegFrameSize & 0xFFFF); 511 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 512 .addReg(PPC::X1, RegState::Kill) 513 .addReg(PPC::X1) 514 .addReg(PPC::X0); 515 } 516 } 517 518 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 519 520 // Add the "machine moves" for the instructions we generated above, but in 521 // reverse order. 522 if (needsFrameMoves) { 523 // Mark effective beginning of when frame pointer becomes valid. 524 FrameLabel = MMI.getContext().CreateTempSymbol(); 525 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 526 527 // Show update of SP. 528 if (NegFrameSize) { 529 MachineLocation SPDst(MachineLocation::VirtualFP); 530 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 531 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 532 } else { 533 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 534 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 535 } 536 537 if (HasFP) { 538 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 539 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 540 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 541 } 542 543 if (MustSaveLR) { 544 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 545 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 546 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 547 } 548 } 549 550 MCSymbol *ReadyLabel = 0; 551 552 // If there is a frame pointer, copy R1 into R31 553 if (HasFP) { 554 if (!isPPC64) { 555 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 556 .addReg(PPC::R1) 557 .addReg(PPC::R1); 558 } else { 559 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 560 .addReg(PPC::X1) 561 .addReg(PPC::X1); 562 } 563 564 if (needsFrameMoves) { 565 ReadyLabel = MMI.getContext().CreateTempSymbol(); 566 567 // Mark effective beginning of when frame pointer is ready. 568 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 569 570 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 571 (isPPC64 ? PPC::X1 : PPC::R1)); 572 MachineLocation FPSrc(MachineLocation::VirtualFP); 573 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 574 } 575 } 576 577 if (needsFrameMoves) { 578 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 579 580 // Add callee saved registers to move list. 581 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 582 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 583 unsigned Reg = CSI[I].getReg(); 584 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 585 586 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 587 // subregisters of CR2. We just need to emit a move of CR2. 588 if (PPC::CRBITRCRegClass.contains(Reg)) 589 continue; 590 591 // For SVR4, don't emit a move for the CR spill slot if we haven't 592 // spilled CRs. 593 if (Subtarget.isSVR4ABI() 594 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 595 && MustSaveCRs.empty()) 596 continue; 597 598 // For 64-bit SVR4 when we have spilled CRs, the spill location 599 // is SP+8, not a frame-relative slot. 600 if (Subtarget.isSVR4ABI() 601 && Subtarget.isPPC64() 602 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 603 MachineLocation CSDst(PPC::X1, 8); 604 MachineLocation CSSrc(PPC::CR2); 605 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 606 continue; 607 } 608 609 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 610 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 611 MachineLocation CSSrc(Reg); 612 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 613 } 614 } 615} 616 617void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 618 MachineBasicBlock &MBB) const { 619 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 620 assert(MBBI != MBB.end() && "Returning block has no terminator"); 621 const PPCInstrInfo &TII = 622 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 623 624 unsigned RetOpcode = MBBI->getOpcode(); 625 DebugLoc dl; 626 627 assert((RetOpcode == PPC::BLR || 628 RetOpcode == PPC::TCRETURNri || 629 RetOpcode == PPC::TCRETURNdi || 630 RetOpcode == PPC::TCRETURNai || 631 RetOpcode == PPC::TCRETURNri8 || 632 RetOpcode == PPC::TCRETURNdi8 || 633 RetOpcode == PPC::TCRETURNai8) && 634 "Can only insert epilog into returning blocks"); 635 636 // Get alignment info so we know how to restore r1 637 const MachineFrameInfo *MFI = MF.getFrameInfo(); 638 unsigned TargetAlign = getStackAlignment(); 639 unsigned MaxAlign = MFI->getMaxAlignment(); 640 641 // Get the number of bytes allocated from the FrameInfo. 642 int FrameSize = MFI->getStackSize(); 643 644 // Get processor type. 645 bool isPPC64 = Subtarget.isPPC64(); 646 // Get operating system 647 bool isDarwinABI = Subtarget.isDarwinABI(); 648 // Check if the link register (LR) has been saved. 649 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 650 bool MustSaveLR = FI->mustSaveLR(); 651 const SmallVector<unsigned, 3> &MustSaveCRs = FI->getMustSaveCRs(); 652 // Do we have a frame pointer for this function? 653 bool HasFP = hasFP(MF); 654 655 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 656 657 int FPOffset = 0; 658 if (HasFP) { 659 if (Subtarget.isSVR4ABI()) { 660 MachineFrameInfo *FFI = MF.getFrameInfo(); 661 int FPIndex = FI->getFramePointerSaveIndex(); 662 assert(FPIndex && "No Frame Pointer Save Slot!"); 663 FPOffset = FFI->getObjectOffset(FPIndex); 664 } else { 665 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 666 } 667 } 668 669 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 670 RetOpcode == PPC::TCRETURNdi || 671 RetOpcode == PPC::TCRETURNai || 672 RetOpcode == PPC::TCRETURNri8 || 673 RetOpcode == PPC::TCRETURNdi8 || 674 RetOpcode == PPC::TCRETURNai8; 675 676 if (UsesTCRet) { 677 int MaxTCRetDelta = FI->getTailCallSPDelta(); 678 MachineOperand &StackAdjust = MBBI->getOperand(1); 679 assert(StackAdjust.isImm() && "Expecting immediate value."); 680 // Adjust stack pointer. 681 int StackAdj = StackAdjust.getImm(); 682 int Delta = StackAdj - MaxTCRetDelta; 683 assert((Delta >= 0) && "Delta must be positive"); 684 if (MaxTCRetDelta>0) 685 FrameSize += (StackAdj +Delta); 686 else 687 FrameSize += StackAdj; 688 } 689 690 if (FrameSize) { 691 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 692 // on entry to the function. Add this offset back now. 693 if (!isPPC64) { 694 // If this function contained a fastcc call and GuaranteedTailCallOpt is 695 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 696 // call which invalidates the stack pointer value in SP(0). So we use the 697 // value of R31 in this case. 698 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 699 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 700 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 701 .addReg(PPC::R31).addImm(FrameSize); 702 } else if(FI->hasFastCall()) { 703 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 704 .addImm(FrameSize >> 16); 705 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 706 .addReg(PPC::R0, RegState::Kill) 707 .addImm(FrameSize & 0xFFFF); 708 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 709 .addReg(PPC::R1) 710 .addReg(PPC::R31) 711 .addReg(PPC::R0); 712 } else if (isInt<16>(FrameSize) && 713 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 714 !MFI->hasVarSizedObjects()) { 715 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 716 .addReg(PPC::R1).addImm(FrameSize); 717 } else { 718 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 719 .addImm(0).addReg(PPC::R1); 720 } 721 } else { 722 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 723 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 724 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 725 .addReg(PPC::X31).addImm(FrameSize); 726 } else if(FI->hasFastCall()) { 727 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 728 .addImm(FrameSize >> 16); 729 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 730 .addReg(PPC::X0, RegState::Kill) 731 .addImm(FrameSize & 0xFFFF); 732 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 733 .addReg(PPC::X1) 734 .addReg(PPC::X31) 735 .addReg(PPC::X0); 736 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 737 !MFI->hasVarSizedObjects()) { 738 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 739 .addReg(PPC::X1).addImm(FrameSize); 740 } else { 741 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 742 .addImm(0).addReg(PPC::X1); 743 } 744 } 745 } 746 747 if (isPPC64) { 748 if (MustSaveLR) 749 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 750 .addImm(LROffset/4).addReg(PPC::X1); 751 752 if (!MustSaveCRs.empty()) 753 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), PPC::X12) 754 .addImm(8).addReg(PPC::X1); 755 756 if (HasFP) 757 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 758 .addImm(FPOffset/4).addReg(PPC::X1); 759 760 if (!MustSaveCRs.empty()) 761 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i) 762 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTCRF8), MustSaveCRs[i]) 763 .addReg(PPC::X12, getKillRegState(i == e-1)); 764 765 if (MustSaveLR) 766 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 767 } else { 768 if (MustSaveLR) 769 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 770 .addImm(LROffset).addReg(PPC::R1); 771 772 assert(MustSaveCRs.empty() && 773 "Epilogue CR restoring supported only in 64-bit mode"); 774 775 if (HasFP) 776 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 777 .addImm(FPOffset).addReg(PPC::R1); 778 779 if (MustSaveLR) 780 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 781 } 782 783 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 784 // call optimization 785 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 786 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 787 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 788 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 789 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 790 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 791 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 792 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 793 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 794 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 795 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 796 797 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 798 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 799 .addReg(StackReg).addImm(CallerAllocatedAmt); 800 } else { 801 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 802 .addImm(CallerAllocatedAmt >> 16); 803 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 804 .addReg(TmpReg, RegState::Kill) 805 .addImm(CallerAllocatedAmt & 0xFFFF); 806 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 807 .addReg(StackReg) 808 .addReg(FPReg) 809 .addReg(TmpReg); 810 } 811 } else if (RetOpcode == PPC::TCRETURNdi) { 812 MBBI = MBB.getLastNonDebugInstr(); 813 MachineOperand &JumpTarget = MBBI->getOperand(0); 814 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 815 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 816 } else if (RetOpcode == PPC::TCRETURNri) { 817 MBBI = MBB.getLastNonDebugInstr(); 818 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 819 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 820 } else if (RetOpcode == PPC::TCRETURNai) { 821 MBBI = MBB.getLastNonDebugInstr(); 822 MachineOperand &JumpTarget = MBBI->getOperand(0); 823 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 824 } else if (RetOpcode == PPC::TCRETURNdi8) { 825 MBBI = MBB.getLastNonDebugInstr(); 826 MachineOperand &JumpTarget = MBBI->getOperand(0); 827 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 828 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 829 } else if (RetOpcode == PPC::TCRETURNri8) { 830 MBBI = MBB.getLastNonDebugInstr(); 831 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 832 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 833 } else if (RetOpcode == PPC::TCRETURNai8) { 834 MBBI = MBB.getLastNonDebugInstr(); 835 MachineOperand &JumpTarget = MBBI->getOperand(0); 836 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 837 } 838} 839 840/// MustSaveLR - Return true if this function requires that we save the LR 841/// register onto the stack in the prolog and restore it in the epilog of the 842/// function. 843static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 844 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 845 846 // We need a save/restore of LR if there is any def of LR (which is 847 // defined by calls, including the PIC setup sequence), or if there is 848 // some use of the LR stack slot (e.g. for builtin_return_address). 849 // (LR comes in 32 and 64 bit versions.) 850 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 851 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 852} 853 854void 855PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 856 RegScavenger *) const { 857 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 858 859 // Save and clear the LR state. 860 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 861 unsigned LR = RegInfo->getRARegister(); 862 FI->setMustSaveLR(MustSaveLR(MF, LR)); 863 MachineRegisterInfo &MRI = MF.getRegInfo(); 864 MRI.setPhysRegUnused(LR); 865 866 // Save R31 if necessary 867 int FPSI = FI->getFramePointerSaveIndex(); 868 bool isPPC64 = Subtarget.isPPC64(); 869 bool isDarwinABI = Subtarget.isDarwinABI(); 870 MachineFrameInfo *MFI = MF.getFrameInfo(); 871 872 // If the frame pointer save index hasn't been defined yet. 873 if (!FPSI && needsFP(MF)) { 874 // Find out what the fix offset of the frame pointer save area. 875 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 876 // Allocate the frame index for frame pointer save area. 877 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 878 // Save the result. 879 FI->setFramePointerSaveIndex(FPSI); 880 } 881 882 // Reserve stack space to move the linkage area to in case of a tail call. 883 int TCSPDelta = 0; 884 if (MF.getTarget().Options.GuaranteedTailCallOpt && 885 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 886 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 887 } 888 889 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 890 // function uses CR 2, 3, or 4. 891 if (!isPPC64 && !isDarwinABI && 892 (MRI.isPhysRegUsed(PPC::CR2) || 893 MRI.isPhysRegUsed(PPC::CR3) || 894 MRI.isPhysRegUsed(PPC::CR4))) { 895 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 896 FI->setCRSpillFrameIndex(FrameIdx); 897 } 898} 899 900void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 901 RegScavenger *RS) const { 902 // Early exit if not using the SVR4 ABI. 903 if (!Subtarget.isSVR4ABI()) { 904 addScavengingSpillSlot(MF, RS); 905 return; 906 } 907 908 // Get callee saved register information. 909 MachineFrameInfo *FFI = MF.getFrameInfo(); 910 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 911 912 // Early exit if no callee saved registers are modified! 913 if (CSI.empty() && !needsFP(MF)) { 914 addScavengingSpillSlot(MF, RS); 915 return; 916 } 917 918 unsigned MinGPR = PPC::R31; 919 unsigned MinG8R = PPC::X31; 920 unsigned MinFPR = PPC::F31; 921 unsigned MinVR = PPC::V31; 922 923 bool HasGPSaveArea = false; 924 bool HasG8SaveArea = false; 925 bool HasFPSaveArea = false; 926 bool HasVRSAVESaveArea = false; 927 bool HasVRSaveArea = false; 928 929 SmallVector<CalleeSavedInfo, 18> GPRegs; 930 SmallVector<CalleeSavedInfo, 18> G8Regs; 931 SmallVector<CalleeSavedInfo, 18> FPRegs; 932 SmallVector<CalleeSavedInfo, 18> VRegs; 933 934 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 935 unsigned Reg = CSI[i].getReg(); 936 if (PPC::GPRCRegClass.contains(Reg)) { 937 HasGPSaveArea = true; 938 939 GPRegs.push_back(CSI[i]); 940 941 if (Reg < MinGPR) { 942 MinGPR = Reg; 943 } 944 } else if (PPC::G8RCRegClass.contains(Reg)) { 945 HasG8SaveArea = true; 946 947 G8Regs.push_back(CSI[i]); 948 949 if (Reg < MinG8R) { 950 MinG8R = Reg; 951 } 952 } else if (PPC::F8RCRegClass.contains(Reg)) { 953 HasFPSaveArea = true; 954 955 FPRegs.push_back(CSI[i]); 956 957 if (Reg < MinFPR) { 958 MinFPR = Reg; 959 } 960 } else if (PPC::CRBITRCRegClass.contains(Reg) || 961 PPC::CRRCRegClass.contains(Reg)) { 962 ; // do nothing, as we already know whether CRs are spilled 963 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 964 HasVRSAVESaveArea = true; 965 } else if (PPC::VRRCRegClass.contains(Reg)) { 966 HasVRSaveArea = true; 967 968 VRegs.push_back(CSI[i]); 969 970 if (Reg < MinVR) { 971 MinVR = Reg; 972 } 973 } else { 974 llvm_unreachable("Unknown RegisterClass!"); 975 } 976 } 977 978 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 979 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 980 981 int64_t LowerBound = 0; 982 983 // Take into account stack space reserved for tail calls. 984 int TCSPDelta = 0; 985 if (MF.getTarget().Options.GuaranteedTailCallOpt && 986 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 987 LowerBound = TCSPDelta; 988 } 989 990 // The Floating-point register save area is right below the back chain word 991 // of the previous stack frame. 992 if (HasFPSaveArea) { 993 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 994 int FI = FPRegs[i].getFrameIdx(); 995 996 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 997 } 998 999 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 1000 } 1001 1002 // Check whether the frame pointer register is allocated. If so, make sure it 1003 // is spilled to the correct offset. 1004 if (needsFP(MF)) { 1005 HasGPSaveArea = true; 1006 1007 int FI = PFI->getFramePointerSaveIndex(); 1008 assert(FI && "No Frame Pointer Save Slot!"); 1009 1010 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1011 } 1012 1013 // General register save area starts right below the Floating-point 1014 // register save area. 1015 if (HasGPSaveArea || HasG8SaveArea) { 1016 // Move general register save area spill slots down, taking into account 1017 // the size of the Floating-point register save area. 1018 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 1019 int FI = GPRegs[i].getFrameIdx(); 1020 1021 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1022 } 1023 1024 // Move general register save area spill slots down, taking into account 1025 // the size of the Floating-point register save area. 1026 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1027 int FI = G8Regs[i].getFrameIdx(); 1028 1029 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1030 } 1031 1032 unsigned MinReg = 1033 std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1034 TRI->getEncodingValue(MinG8R)); 1035 1036 if (Subtarget.isPPC64()) { 1037 LowerBound -= (31 - MinReg + 1) * 8; 1038 } else { 1039 LowerBound -= (31 - MinReg + 1) * 4; 1040 } 1041 } 1042 1043 // For 32-bit only, the CR save area is below the general register 1044 // save area. For 64-bit SVR4, the CR save area is addressed relative 1045 // to the stack pointer and hence does not need an adjustment here. 1046 // Only CR2 (the first nonvolatile spilled) has an associated frame 1047 // index so that we have a single uniform save area. 1048 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1049 // Adjust the frame index of the CR spill slot. 1050 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1051 unsigned Reg = CSI[i].getReg(); 1052 1053 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1054 // Leave Darwin logic as-is. 1055 || (!Subtarget.isSVR4ABI() && 1056 (PPC::CRBITRCRegClass.contains(Reg) || 1057 PPC::CRRCRegClass.contains(Reg)))) { 1058 int FI = CSI[i].getFrameIdx(); 1059 1060 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1061 } 1062 } 1063 1064 LowerBound -= 4; // The CR save area is always 4 bytes long. 1065 } 1066 1067 if (HasVRSAVESaveArea) { 1068 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1069 // which have the VRSAVE register class? 1070 // Adjust the frame index of the VRSAVE spill slot. 1071 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1072 unsigned Reg = CSI[i].getReg(); 1073 1074 if (PPC::VRSAVERCRegClass.contains(Reg)) { 1075 int FI = CSI[i].getFrameIdx(); 1076 1077 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1078 } 1079 } 1080 1081 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1082 } 1083 1084 if (HasVRSaveArea) { 1085 // Insert alignment padding, we need 16-byte alignment. 1086 LowerBound = (LowerBound - 15) & ~(15); 1087 1088 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1089 int FI = VRegs[i].getFrameIdx(); 1090 1091 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1092 } 1093 } 1094 1095 addScavengingSpillSlot(MF, RS); 1096} 1097 1098void 1099PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1100 RegScavenger *RS) const { 1101 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1102 // a large stack, which will require scavenging a register to materialize a 1103 // large offset. 1104 1105 // We need to have a scavenger spill slot for spills if the frame size is 1106 // large. In case there is no free register for large-offset addressing, 1107 // this slot is used for the necessary emergency spill. Also, we need the 1108 // slot for dynamic stack allocations. 1109 1110 // The scavenger might be invoked if the frame offset does not fit into 1111 // the 16-bit immediate. We don't know the complete frame size here 1112 // because we've not yet computed callee-saved register spills or the 1113 // needed alignment padding. 1114 unsigned StackSize = determineFrameLayout(MF, false, true); 1115 MachineFrameInfo *MFI = MF.getFrameInfo(); 1116 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1117 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1118 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1119 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1120 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1121 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1122 RC->getAlignment(), 1123 false)); 1124 1125 // These kinds of spills might need two registers. 1126 if (spillsCR(MF) || spillsVRSAVE(MF)) 1127 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1128 RC->getAlignment(), 1129 false)); 1130 1131 } 1132} 1133 1134bool 1135PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1136 MachineBasicBlock::iterator MI, 1137 const std::vector<CalleeSavedInfo> &CSI, 1138 const TargetRegisterInfo *TRI) const { 1139 1140 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1141 // Return false otherwise to maintain pre-existing behavior. 1142 if (!Subtarget.isSVR4ABI()) 1143 return false; 1144 1145 MachineFunction *MF = MBB.getParent(); 1146 const PPCInstrInfo &TII = 1147 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1148 DebugLoc DL; 1149 bool CRSpilled = false; 1150 MachineInstrBuilder CRMIB; 1151 1152 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1153 unsigned Reg = CSI[i].getReg(); 1154 // CR2 through CR4 are the nonvolatile CR fields. 1155 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1156 1157 // Add the callee-saved register as live-in; it's killed at the spill. 1158 MBB.addLiveIn(Reg); 1159 1160 if (CRSpilled && IsCRField) { 1161 CRMIB.addReg(Reg, RegState::ImplicitKill); 1162 continue; 1163 } 1164 1165 // Insert the spill to the stack frame. 1166 if (IsCRField) { 1167 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1168 if (Subtarget.isPPC64()) { 1169 // The actual spill will happen at the start of the prologue. 1170 FuncInfo->addMustSaveCR(Reg); 1171 } else { 1172 CRSpilled = true; 1173 FuncInfo->setSpillsCR(); 1174 1175 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1176 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1177 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12) 1178 .addReg(Reg, RegState::ImplicitKill); 1179 1180 MBB.insert(MI, CRMIB); 1181 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1182 .addReg(PPC::R12, 1183 getKillRegState(true)), 1184 CSI[i].getFrameIdx())); 1185 } 1186 } else { 1187 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1188 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1189 CSI[i].getFrameIdx(), RC, TRI); 1190 } 1191 } 1192 return true; 1193} 1194 1195static void 1196restoreCRs(bool isPPC64, bool is31, 1197 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1198 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1199 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1200 1201 MachineFunction *MF = MBB.getParent(); 1202 const PPCInstrInfo &TII = 1203 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1204 DebugLoc DL; 1205 unsigned RestoreOp, MoveReg; 1206 1207 if (isPPC64) 1208 // This is handled during epilogue generation. 1209 return; 1210 else { 1211 // 32-bit: FP-relative 1212 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1213 PPC::R12), 1214 CSI[CSIIndex].getFrameIdx())); 1215 RestoreOp = PPC::MTCRF; 1216 MoveReg = PPC::R12; 1217 } 1218 1219 if (CR2Spilled) 1220 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1221 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1222 1223 if (CR3Spilled) 1224 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1225 .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1226 1227 if (CR4Spilled) 1228 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1229 .addReg(MoveReg, getKillRegState(true))); 1230} 1231 1232void PPCFrameLowering:: 1233eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1234 MachineBasicBlock::iterator I) const { 1235 const PPCInstrInfo &TII = 1236 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1237 if (MF.getTarget().Options.GuaranteedTailCallOpt && 1238 I->getOpcode() == PPC::ADJCALLSTACKUP) { 1239 // Add (actually subtract) back the amount the callee popped on return. 1240 if (int CalleeAmt = I->getOperand(1).getImm()) { 1241 bool is64Bit = Subtarget.isPPC64(); 1242 CalleeAmt *= -1; 1243 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1244 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1245 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1246 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1247 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1248 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1249 MachineInstr *MI = I; 1250 DebugLoc dl = MI->getDebugLoc(); 1251 1252 if (isInt<16>(CalleeAmt)) { 1253 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1254 .addReg(StackReg, RegState::Kill) 1255 .addImm(CalleeAmt); 1256 } else { 1257 MachineBasicBlock::iterator MBBI = I; 1258 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1259 .addImm(CalleeAmt >> 16); 1260 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1261 .addReg(TmpReg, RegState::Kill) 1262 .addImm(CalleeAmt & 0xFFFF); 1263 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1264 .addReg(StackReg, RegState::Kill) 1265 .addReg(TmpReg); 1266 } 1267 } 1268 } 1269 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1270 MBB.erase(I); 1271} 1272 1273bool 1274PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1275 MachineBasicBlock::iterator MI, 1276 const std::vector<CalleeSavedInfo> &CSI, 1277 const TargetRegisterInfo *TRI) const { 1278 1279 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1280 // Return false otherwise to maintain pre-existing behavior. 1281 if (!Subtarget.isSVR4ABI()) 1282 return false; 1283 1284 MachineFunction *MF = MBB.getParent(); 1285 const PPCInstrInfo &TII = 1286 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1287 bool CR2Spilled = false; 1288 bool CR3Spilled = false; 1289 bool CR4Spilled = false; 1290 unsigned CSIIndex = 0; 1291 1292 // Initialize insertion-point logic; we will be restoring in reverse 1293 // order of spill. 1294 MachineBasicBlock::iterator I = MI, BeforeI = I; 1295 bool AtStart = I == MBB.begin(); 1296 1297 if (!AtStart) 1298 --BeforeI; 1299 1300 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1301 unsigned Reg = CSI[i].getReg(); 1302 1303 if (Reg == PPC::CR2) { 1304 CR2Spilled = true; 1305 // The spill slot is associated only with CR2, which is the 1306 // first nonvolatile spilled. Save it here. 1307 CSIIndex = i; 1308 continue; 1309 } else if (Reg == PPC::CR3) { 1310 CR3Spilled = true; 1311 continue; 1312 } else if (Reg == PPC::CR4) { 1313 CR4Spilled = true; 1314 continue; 1315 } else { 1316 // When we first encounter a non-CR register after seeing at 1317 // least one CR register, restore all spilled CRs together. 1318 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1319 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1320 bool is31 = needsFP(*MF); 1321 restoreCRs(Subtarget.isPPC64(), is31, 1322 CR2Spilled, CR3Spilled, CR4Spilled, 1323 MBB, I, CSI, CSIIndex); 1324 CR2Spilled = CR3Spilled = CR4Spilled = false; 1325 } 1326 1327 // Default behavior for non-CR saves. 1328 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1329 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1330 RC, TRI); 1331 assert(I != MBB.begin() && 1332 "loadRegFromStackSlot didn't insert any code!"); 1333 } 1334 1335 // Insert in reverse order. 1336 if (AtStart) 1337 I = MBB.begin(); 1338 else { 1339 I = BeforeI; 1340 ++I; 1341 } 1342 } 1343 1344 // If we haven't yet spilled the CRs, do so now. 1345 if (CR2Spilled || CR3Spilled || CR4Spilled) { 1346 bool is31 = needsFP(*MF); 1347 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled, 1348 MBB, I, CSI, CSIIndex); 1349 } 1350 1351 return true; 1352} 1353 1354