1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004, 5 2005, 2006 6 Free Software Foundation, Inc. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify it under 11the terms of the GNU General Public License as published by the Free 12Software Foundation; either version 2, or (at your option) any later 13version. 14 15GCC is distributed in the hope that it will be useful, but WITHOUT ANY 16WARRANTY; without even the implied warranty of MERCHANTABILITY or 17FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING. If not, write to the Free 22Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 2302110-1301, USA. */ 24 25 26/* Expression definitions and descriptions for all targets are in this file. 27 Some will not be used for some targets. 28 29 The fields in the cpp macro call "DEF_RTL_EXPR()" 30 are used to create declarations in the C source of the compiler. 31 32 The fields are: 33 34 1. The internal name of the rtx used in the C source. 35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 36 By convention these are in UPPER_CASE. 37 38 2. The name of the rtx in the external ASCII format read by 39 read_rtx(), and printed by print_rtx(). 40 These names are stored in rtx_name[]. 41 By convention these are the internal (field 1) names in lower_case. 42 43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. 44 These formats are stored in rtx_format[]. 45 The meaning of the formats is documented in front of this array in rtl.c 46 47 4. The class of the rtx. These are stored in rtx_class and are accessed 48 via the GET_RTX_CLASS macro. They are defined as follows: 49 50 RTX_CONST_OBJ 51 an rtx code that can be used to represent a constant object 52 (e.g, CONST_INT) 53 RTX_OBJ 54 an rtx code that can be used to represent an object (e.g, REG, MEM) 55 RTX_COMPARE 56 an rtx code for a comparison (e.g, LT, GT) 57 RTX_COMM_COMPARE 58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) 59 RTX_UNARY 60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 61 RTX_COMM_ARITH 62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 63 RTX_TERNARY 64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 65 RTX_BIN_ARITH 66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 67 RTX_BITFIELD_OPS 68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 69 RTX_INSN 70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 71 RTX_MATCH 72 an rtx code for something that matches in insns (e.g, MATCH_DUP) 73 RTX_AUTOINC 74 an rtx code for autoincrement addressing modes (e.g. POST_DEC) 75 RTX_EXTRA 76 everything else 77 78 All of the expressions that appear only in machine descriptions, 79 not in RTL used by the compiler itself, are at the end of the file. */ 80 81/* Unknown, or no such operation; the enumeration constant should have 82 value zero. */ 83DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) 84 85/* --------------------------------------------------------------------- 86 Expressions used in constructing lists. 87 --------------------------------------------------------------------- */ 88 89/* a linked list of expressions */ 90DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) 91 92/* a linked list of instructions. 93 The insns are represented in print by their uids. */ 94DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) 95 96/* a linked list of dependencies. 97 The insns are represented in print by their uids. 98 Operand 2 is the status of a dependence (see sched-int.h for more). */ 99DEF_RTL_EXPR(DEPS_LIST, "deps_list", "uei", RTX_EXTRA) 100 101/* SEQUENCE appears in the result of a `gen_...' function 102 for a DEFINE_EXPAND that wants to make several insns. 103 Its elements are the bodies of the insns that should be made. 104 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 105DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) 106 107/* Refers to the address of its argument. This is only used in alias.c. */ 108DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH) 109 110/* ---------------------------------------------------------------------- 111 Expression types used for things in the instruction chain. 112 113 All formats must start with "iuu" to handle the chain. 114 Each insn expression holds an rtl instruction and its semantics 115 during back-end processing. 116 See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. 117 118 ---------------------------------------------------------------------- */ 119 120/* An instruction that cannot jump. */ 121DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN) 122 123/* An instruction that can possibly jump. 124 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 125DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN) 126 127/* An instruction that can possibly call a subroutine 128 but which will not change which instruction comes next 129 in the current function. 130 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE. 131 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 132DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN) 133 134/* A marker that indicates that control will not flow through. */ 135DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA) 136 137/* Holds a label that is followed by instructions. 138 Operand: 139 4: is used in jump.c for the use-count of the label. 140 5: is used in flow.c to point to the chain of label_ref's to this label. 141 6: is a number that is unique in the entire compilation. 142 APPLE LOCAL begin for-fsf-4_4 3274130 5295549 143 7: is the user-given name of the label, if any. 144 8: is the alignment of the label, made up of two parts, 145 LABEL_ALIGNMENT and LABEL_MAX_SKIP. */ 146DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00isi", RTX_EXTRA) 147 148/* APPLE LOCAL end for-fsf-4_4 3274130 5295549 */ \ 149#ifdef USE_MAPPED_LOCATION 150/* Say where in the code a source line starts, for symbol table's sake. 151 Operand: 152 4: unused if line number > 0, note-specific data otherwise. 153 5: line number if > 0, enum note_insn otherwise. 154 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */ 155#else 156/* Say where in the code a source line starts, for symbol table's sake. 157 Operand: 158 4: filename, if line number > 0, note-specific data otherwise. 159 5: line number if > 0, enum note_insn otherwise. 160 6: unique number if line number == note_insn_deleted_label. */ 161#endif 162DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) 163 164/* ---------------------------------------------------------------------- 165 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 166 ---------------------------------------------------------------------- */ 167 168/* Conditionally execute code. 169 Operand 0 is the condition that if true, the code is executed. 170 Operand 1 is the code to be executed (typically a SET). 171 172 Semantics are that there are no side effects if the condition 173 is false. This pattern is created automatically by the if_convert 174 pass run after reload or by target-specific splitters. */ 175DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) 176 177/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 178DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) 179 180/* A string that is passed through to the assembler as input. 181 One can obviously pass comments through by using the 182 assembler comment syntax. 183 These occur in an insn all by themselves as the PATTERN. 184 They also appear inside an ASM_OPERANDS 185 as a convenient way to hold a string. */ 186DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA) 187 188#ifdef USE_MAPPED_LOCATION 189/* An assembler instruction with operands. 190 1st operand is the instruction template. 191 2nd operand is the constraint for the output. 192 3rd operand is the number of the output this expression refers to. 193 When an insn stores more than one value, a separate ASM_OPERANDS 194 is made for each output; this integer distinguishes them. 195 4th is a vector of values of input operands. 196 5th is a vector of modes and constraints for the input operands. 197 Each element is an ASM_INPUT containing a constraint string 198 and whose mode indicates the mode of the input operand. 199 6th is the source line number. */ 200DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA) 201#else 202/* An assembler instruction with operands. 203 1st operand is the instruction template. 204 2nd operand is the constraint for the output. 205 3rd operand is the number of the output this expression refers to. 206 When an insn stores more than one value, a separate ASM_OPERANDS 207 is made for each output; this integer distinguishes them. 208 4th is a vector of values of input operands. 209 5th is a vector of modes and constraints for the input operands. 210 Each element is an ASM_INPUT containing a constraint string 211 and whose mode indicates the mode of the input operand. 212 6th is the name of the containing source file. 213 7th is the source line number. */ 214DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA) 215#endif 216 217/* A machine-specific operation. 218 1st operand is a vector of operands being used by the operation so that 219 any needed reloads can be done. 220 2nd operand is a unique value saying which of a number of machine-specific 221 operations is to be performed. 222 (Note that the vector must be the first operand because of the way that 223 genrecog.c record positions within an insn.) 224 This can occur all by itself in a PATTERN, as a component of a PARALLEL, 225 or inside an expression. */ 226DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) 227 228/* Similar, but a volatile operation and one which may trap. */ 229DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) 230 231/* Vector of addresses, stored as full words. */ 232/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 233DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) 234 235/* Vector of address differences X0 - BASE, X1 - BASE, ... 236 First operand is BASE; the vector contains the X's. 237 The machine mode of this rtx says how much space to leave 238 for each difference and is adjusted by branch shortening if 239 CASE_VECTOR_SHORTEN_MODE is defined. 240 The third and fourth operands store the target labels with the 241 minimum and maximum addresses respectively. 242 The fifth operand stores flags for use by branch shortening. 243 Set at the start of shorten_branches: 244 min_align: the minimum alignment for any of the target labels. 245 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 246 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 247 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 248 min_after_base: true iff minimum address target label is after BASE. 249 max_after_base: true iff maximum address target label is after BASE. 250 Set by the actual branch shortening process: 251 offset_unsigned: true iff offsets have to be treated as unsigned. 252 scale: scaling that is necessary to make offsets fit into the mode. 253 254 The third, fourth and fifth operands are only valid when 255 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 256 compilations. */ 257 258DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) 259 260/* Memory prefetch, with attributes supported on some targets. 261 Operand 1 is the address of the memory to fetch. 262 Operand 2 is 1 for a write access, 0 otherwise. 263 Operand 3 is the level of temporal locality; 0 means there is no 264 temporal locality and 1, 2, and 3 are for increasing levels of temporal 265 locality. 266 267 The attributes specified by operands 2 and 3 are ignored for targets 268 whose prefetch instructions do not support them. */ 269DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) 270 271/* ---------------------------------------------------------------------- 272 At the top level of an instruction (perhaps under PARALLEL). 273 ---------------------------------------------------------------------- */ 274 275/* Assignment. 276 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 277 Operand 2 is the value stored there. 278 ALL assignment must use SET. 279 Instructions that do multiple assignments must use multiple SET, 280 under PARALLEL. */ 281DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) 282 283/* Indicate something is used in a way that we don't want to explain. 284 For example, subroutine calls will use the register 285 in which the static chain is passed. */ 286DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) 287 288/* Indicate something is clobbered in a way that we don't want to explain. 289 For example, subroutine calls will clobber some physical registers 290 (the ones that are by convention not saved). */ 291DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) 292 293/* Call a subroutine. 294 Operand 1 is the address to call. 295 Operand 2 is the number of arguments. */ 296 297DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) 298 299/* Return from a subroutine. */ 300 301DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) 302 303/* Conditional trap. 304 Operand 1 is the condition. 305 Operand 2 is the trap code. 306 For an unconditional trap, make the condition (const_int 1). */ 307DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) 308 309/* Placeholder for _Unwind_Resume before we know if a function call 310 or a branch is needed. Operand 1 is the exception region from 311 which control is flowing. */ 312DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA) 313 314/* ---------------------------------------------------------------------- 315 Primitive values for use in expressions. 316 ---------------------------------------------------------------------- */ 317 318/* numeric integer constant */ 319DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) 320 321/* numeric floating point constant. 322 Operands hold the value. They are all 'w' and there may be from 2 to 6; 323 see real.h. */ 324DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) 325 326/* Describes a vector constant. */ 327DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) 328 329/* String constant. Used for attributes in machine descriptions and 330 for special cases in DWARF2 debug output. NOT used for source- 331 language string constants. */ 332DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) 333 334/* This is used to encapsulate an expression whose value is constant 335 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 336 recognized as a constant operand rather than by arithmetic instructions. */ 337 338DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) 339 340/* program counter. Ordinary jumps are represented 341 by a SET whose first operand is (PC). */ 342DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) 343 344/* Used in the cselib routines to describe a value. Objects of this 345 kind are only allocated in cselib.c, in an alloc pool instead of 346 in GC memory. The only operand of a VALUE is a cselib_val_struct. */ 347DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) 348 349/* A register. The "operand" is the register number, accessed with 350 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 351 than a hardware register is being referred to. The second operand 352 holds the original register number - this will be different for a 353 pseudo register that got turned into a hard register. The third 354 operand points to a reg_attrs structure. 355 This rtx needs to have as many (or more) fields as a MEM, since we 356 can change REG rtx's into MEMs during reload. */ 357DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) 358 359/* A scratch register. This represents a register used only within a 360 single insn. It will be turned into a REG during register allocation 361 or reload unless the constraint indicates that the register won't be 362 needed, in which case it can remain a SCRATCH. This code is 363 marked as having one operand so it can be turned into a REG. */ 364DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) 365 366/* One word of a multi-word value. 367 The first operand is the complete value; the second says which word. 368 The WORDS_BIG_ENDIAN flag controls whether word number 0 369 (as numbered in a SUBREG) is the most or least significant word. 370 371 This is also used to refer to a value in a different machine mode. 372 For example, it can be used to refer to a SImode value as if it were 373 Qimode, or vice versa. Then the word number is always 0. */ 374DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) 375 376/* This one-argument rtx is used for move instructions 377 that are guaranteed to alter only the low part of a destination. 378 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 379 has an unspecified effect on the high part of REG, 380 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 381 is guaranteed to alter only the bits of REG that are in HImode. 382 383 The actual instruction used is probably the same in both cases, 384 but the register constraints may be tighter when STRICT_LOW_PART 385 is in use. */ 386 387DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) 388 389/* (CONCAT a b) represents the virtual concatenation of a and b 390 to make a value that has as many bits as a and b put together. 391 This is used for complex values. Normally it appears only 392 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 393DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) 394 395/* A memory location; operand is the address. The second operand is the 396 alias set to which this MEM belongs. We use `0' instead of `w' for this 397 field so that the field need not be specified in machine descriptions. */ 398DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) 399 400/* Reference to an assembler label in the code for this function. 401 The operand is a CODE_LABEL found in the insn chain. */ 402DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ) 403 404/* Reference to a named label: 405 Operand 0: label name 406 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) 407 Operand 2: tree from which this symbol is derived, or null. 408 This is either a DECL node, or some kind of constant. */ 409DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) 410 411/* The condition code register is represented, in our imagination, 412 as a register holding a value that can be compared to zero. 413 In fact, the machine has already compared them and recorded the 414 results; but instructions that look at the condition code 415 pretend to be looking at the entire value and comparing it. */ 416DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) 417 418/* ---------------------------------------------------------------------- 419 Expressions for operators in an rtl pattern 420 ---------------------------------------------------------------------- */ 421 422/* if_then_else. This is used in representing ordinary 423 conditional jump instructions. 424 Operand: 425 0: condition 426 1: then expr 427 2: else expr */ 428DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) 429 430/* Comparison, produces a condition code result. */ 431DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) 432 433/* plus */ 434DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) 435 436/* Operand 0 minus operand 1. */ 437DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) 438 439/* Minus operand 0. */ 440DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) 441 442DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) 443 444/* Operand 0 divided by operand 1. */ 445DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) 446/* Remainder of operand 0 divided by operand 1. */ 447DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) 448 449/* Unsigned divide and remainder. */ 450DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) 451DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) 452 453/* Bitwise operations. */ 454DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) 455DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) 456DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) 457DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) 458 459/* Operand: 460 0: value to be shifted. 461 1: number of bits. */ 462DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ 463DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ 464DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ 465DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ 466DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ 467 468/* Minimum and maximum values of two operands. We need both signed and 469 unsigned forms. (We cannot use MIN for SMIN because it conflicts 470 with a macro of the same name.) The signed variants should be used 471 with floating point. Further, if both operands are zeros, or if either 472 operand is NaN, then it is unspecified which of the two operands is 473 returned as the result. */ 474 475DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) 476DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) 477DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) 478DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) 479 480/* These unary operations are used to represent incrementation 481 and decrementation as they occur in memory addresses. 482 The amount of increment or decrement are not represented 483 because they can be understood from the machine-mode of the 484 containing MEM. These operations exist in only two cases: 485 1. pushes onto the stack. 486 2. created automatically by the life_analysis pass in flow.c. */ 487DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) 488DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) 489DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) 490DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) 491 492/* These binary operations are used to represent generic address 493 side-effects in memory addresses, except for simple incrementation 494 or decrementation which use the above operations. They are 495 created automatically by the life_analysis pass in flow.c. 496 The first operand is a REG which is used as the address. 497 The second operand is an expression that is assigned to the 498 register, either before (PRE_MODIFY) or after (POST_MODIFY) 499 evaluating the address. 500 Currently, the compiler can only handle second operands of the 501 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 502 the first operand of the PLUS has to be the same register as 503 the first operand of the *_MODIFY. */ 504DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) 505DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) 506 507/* Comparison operations. The ordered comparisons exist in two 508 flavors, signed and unsigned. */ 509DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) 510DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) 511DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) 512DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) 513DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) 514DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) 515DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) 516DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) 517DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) 518DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) 519 520/* Additional floating point unordered comparison flavors. */ 521DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) 522DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) 523 524/* These are equivalent to unordered or ... */ 525DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) 526DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) 527DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) 528DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) 529DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) 530 531/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 532DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) 533 534/* Represents the result of sign-extending the sole operand. 535 The machine modes of the operand and of the SIGN_EXTEND expression 536 determine how much sign-extension is going on. */ 537DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) 538 539/* Similar for zero-extension (such as unsigned short to int). */ 540DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) 541 542/* Similar but here the operand has a wider mode. */ 543DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) 544 545/* Similar for extending floating-point values (such as SFmode to DFmode). */ 546DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) 547DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) 548 549/* Conversion of fixed point operand to floating point value. */ 550DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) 551 552/* With fixed-point machine mode: 553 Conversion of floating point operand to fixed point value. 554 Value is defined only when the operand's value is an integer. 555 With floating-point machine mode (and operand with same mode): 556 Operand is rounded toward zero to produce an integer value 557 represented in floating point. */ 558DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) 559 560/* Conversion of unsigned fixed point operand to floating point value. */ 561DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) 562 563/* With fixed-point machine mode: 564 Conversion of floating point operand to *unsigned* fixed point value. 565 Value is defined only when the operand's value is an integer. */ 566DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) 567 568/* Absolute value */ 569DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) 570 571/* Square root */ 572DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) 573 574/* Swap bytes. */ 575DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY) 576 577/* Find first bit that is set. 578 Value is 1 + number of trailing zeros in the arg., 579 or 0 if arg is 0. */ 580DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) 581 582/* Count leading zeros. */ 583DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) 584 585/* Count trailing zeros. */ 586DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) 587 588/* Population count (number of 1 bits). */ 589DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) 590 591/* Population parity (number of 1 bits modulo 2). */ 592DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) 593 594/* Reference to a signed bit-field of specified size and position. 595 Operand 0 is the memory unit (usually SImode or QImode) which 596 contains the field's first bit. Operand 1 is the width, in bits. 597 Operand 2 is the number of bits in the memory unit before the 598 first bit of this field. 599 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 600 operand 2 counts from the msb of the memory unit. 601 Otherwise, the first bit is the lsb and operand 2 counts from 602 the lsb of the memory unit. 603 This kind of expression can not appear as an lvalue in RTL. */ 604DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) 605 606/* Similar for unsigned bit-field. 607 But note! This kind of expression _can_ appear as an lvalue. */ 608DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) 609 610/* For RISC machines. These save memory when splitting insns. */ 611 612/* HIGH are the high-order bits of a constant expression. */ 613DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) 614 615/* LO_SUM is the sum of a register and the low-order bits 616 of a constant expression. */ 617DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 618 619/* Describes a merge operation between two vector values. 620 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 621 that specifies where the parts of the result are taken from. Set bits 622 indicate operand 0, clear bits indicate operand 1. The parts are defined 623 by the mode of the vectors. */ 624DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) 625 626/* Describes an operation that selects parts of a vector. 627 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 628 a CONST_INT for each of the subparts of the result vector, giving the 629 number of the source subpart that should be stored into it. */ 630DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) 631 632/* Describes a vector concat operation. Operands 0 and 1 are the source 633 vectors, the result is a vector that is as long as operands 0 and 1 634 combined and is the concatenation of the two source vectors. */ 635DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) 636 637/* Describes an operation that converts a small vector into a larger one by 638 duplicating the input values. The output vector mode must have the same 639 submodes as the input vector mode, and the number of output parts must be 640 an integer multiple of the number of input parts. */ 641DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) 642 643/* Addition with signed saturation */ 644DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) 645 646/* Addition with unsigned saturation */ 647DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) 648 649/* Operand 0 minus operand 1, with signed saturation. */ 650DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) 651 652/* Negation with signed saturation. */ 653DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY) 654 655/* Shift left with signed saturation. */ 656DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH) 657 658/* Operand 0 minus operand 1, with unsigned saturation. */ 659DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) 660 661/* Signed saturating truncate. */ 662DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) 663 664/* Unsigned saturating truncate. */ 665DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) 666 667/* Information about the variable and its location. */ 668DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA) 669 670/* All expressions from this point forward appear only in machine 671 descriptions. */ 672#ifdef GENERATOR_FILE 673 674/* Include a secondary machine-description file at this point. */ 675DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA) 676 677/* Pattern-matching operators: */ 678 679/* Use the function named by the second arg (the string) 680 as a predicate; if matched, store the structure that was matched 681 in the operand table at index specified by the first arg (the integer). 682 If the second arg is the null string, the structure is just stored. 683 684 A third string argument indicates to the register allocator restrictions 685 on where the operand can be allocated. 686 687 If the target needs no restriction on any instruction this field should 688 be the null string. 689 690 The string is prepended by: 691 '=' to indicate the operand is only written to. 692 '+' to indicate the operand is both read and written to. 693 694 Each character in the string represents an allocable class for an operand. 695 'g' indicates the operand can be any valid class. 696 'i' indicates the operand can be immediate (in the instruction) data. 697 'r' indicates the operand can be in a register. 698 'm' indicates the operand can be in memory. 699 'o' a subset of the 'm' class. Those memory addressing modes that 700 can be offset at compile time (have a constant added to them). 701 702 Other characters indicate target dependent operand classes and 703 are described in each target's machine description. 704 705 For instructions with more than one operand, sets of classes can be 706 separated by a comma to indicate the appropriate multi-operand constraints. 707 There must be a 1 to 1 correspondence between these sets of classes in 708 all operands for an instruction. 709 */ 710DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) 711 712/* Match a SCRATCH or a register. When used to generate rtl, a 713 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 714 the desired mode and the first argument is the operand number. 715 The second argument is the constraint. */ 716DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) 717 718/* Apply a predicate, AND match recursively the operands of the rtx. 719 Operand 0 is the operand-number, as in match_operand. 720 Operand 1 is a predicate to apply (as a string, a function name). 721 Operand 2 is a vector of expressions, each of which must match 722 one subexpression of the rtx this construct is matching. */ 723DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) 724 725/* Match a PARALLEL of arbitrary length. The predicate is applied 726 to the PARALLEL and the initial expressions in the PARALLEL are matched. 727 Operand 0 is the operand-number, as in match_operand. 728 Operand 1 is a predicate to apply to the PARALLEL. 729 Operand 2 is a vector of expressions, each of which must match the 730 corresponding element in the PARALLEL. */ 731DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) 732 733/* Match only something equal to what is stored in the operand table 734 at the index specified by the argument. Use with MATCH_OPERAND. */ 735DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 736 737/* Match only something equal to what is stored in the operand table 738 at the index specified by the argument. Use with MATCH_OPERATOR. */ 739DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) 740 741/* Match only something equal to what is stored in the operand table 742 at the index specified by the argument. Use with MATCH_PARALLEL. */ 743DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) 744 745/* Appears only in define_predicate/define_special_predicate 746 expressions. Evaluates true only if the operand has an RTX code 747 from the set given by the argument (a comma-separated list). If the 748 second argument is present and nonempty, it is a sequence of digits 749 and/or letters which indicates the subexpression to test, using the 750 same syntax as genextract/genrecog's location strings: 0-9 for 751 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to 752 the result of the one before it. */ 753DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) 754 755/* Appears only in define_predicate/define_special_predicate 756 expressions. The argument is a C expression to be injected at this 757 point in the predicate formula. */ 758DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 759 760/* Insn (and related) definitions. */ 761 762/* Definition of the pattern for one kind of instruction. 763 Operand: 764 0: names this instruction. 765 If the name is the null string, the instruction is in the 766 machine description just to be recognized, and will never be emitted by 767 the tree to rtl expander. 768 1: is the pattern. 769 2: is a string which is a C expression 770 giving an additional condition for recognizing this pattern. 771 A null string means no extra condition. 772 3: is the action to execute if this pattern is matched. 773 If this assembler code template starts with a * then it is a fragment of 774 C code to run to decide on a template to use. Otherwise, it is the 775 template to use. 776 4: optionally, a vector of attributes for this insn. 777 */ 778DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) 779 780/* Definition of a peephole optimization. 781 1st operand: vector of insn patterns to match 782 2nd operand: C expression that must be true 783 3rd operand: template or C code to produce assembler output. 784 4: optionally, a vector of attributes for this insn. 785 786 This form is deprecated; use define_peephole2 instead. */ 787DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) 788 789/* Definition of a split operation. 790 1st operand: insn pattern to match 791 2nd operand: C expression that must be true 792 3rd operand: vector of insn patterns to place into a SEQUENCE 793 4th operand: optionally, some C code to execute before generating the 794 insns. This might, for example, create some RTX's and store them in 795 elements of `recog_data.operand' for use by the vector of 796 insn-patterns. 797 (`operands' is an alias here for `recog_data.operand'). */ 798DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) 799 800/* Definition of an insn and associated split. 801 This is the concatenation, with a few modifications, of a define_insn 802 and a define_split which share the same pattern. 803 Operand: 804 0: names this instruction. 805 If the name is the null string, the instruction is in the 806 machine description just to be recognized, and will never be emitted by 807 the tree to rtl expander. 808 1: is the pattern. 809 2: is a string which is a C expression 810 giving an additional condition for recognizing this pattern. 811 A null string means no extra condition. 812 3: is the action to execute if this pattern is matched. 813 If this assembler code template starts with a * then it is a fragment of 814 C code to run to decide on a template to use. Otherwise, it is the 815 template to use. 816 4: C expression that must be true for split. This may start with "&&" 817 in which case the split condition is the logical and of the insn 818 condition and what follows the "&&" of this operand. 819 5: vector of insn patterns to place into a SEQUENCE 820 6: optionally, some C code to execute before generating the 821 insns. This might, for example, create some RTX's and store them in 822 elements of `recog_data.operand' for use by the vector of 823 insn-patterns. 824 (`operands' is an alias here for `recog_data.operand'). 825 7: optionally, a vector of attributes for this insn. */ 826DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) 827 828/* Definition of an RTL peephole operation. 829 Follows the same arguments as define_split. */ 830DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) 831 832/* Define how to generate multiple insns for a standard insn name. 833 1st operand: the insn name. 834 2nd operand: vector of insn-patterns. 835 Use match_operand to substitute an element of `recog_data.operand'. 836 3rd operand: C expression that must be true for this to be available. 837 This may not test any operands. 838 4th operand: Extra C code to execute before generating the insns. 839 This might, for example, create some RTX's and store them in 840 elements of `recog_data.operand' for use by the vector of 841 insn-patterns. 842 (`operands' is an alias here for `recog_data.operand'). */ 843DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA) 844 845/* Define a requirement for delay slots. 846 1st operand: Condition involving insn attributes that, if true, 847 indicates that the insn requires the number of delay slots 848 shown. 849 2nd operand: Vector whose length is the three times the number of delay 850 slots required. 851 Each entry gives three conditions, each involving attributes. 852 The first must be true for an insn to occupy that delay slot 853 location. The second is true for all insns that can be 854 annulled if the branch is true and the third is true for all 855 insns that can be annulled if the branch is false. 856 857 Multiple DEFINE_DELAYs may be present. They indicate differing 858 requirements for delay slots. */ 859DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) 860 861/* Define attribute computation for `asm' instructions. */ 862DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) 863 864/* Definition of a conditional execution meta operation. Automatically 865 generates new instances of DEFINE_INSN, selected by having attribute 866 "predicable" true. The new pattern will contain a COND_EXEC and the 867 predicate at top-level. 868 869 Operand: 870 0: The predicate pattern. The top-level form should match a 871 relational operator. Operands should have only one alternative. 872 1: A C expression giving an additional condition for recognizing 873 the generated pattern. 874 2: A template or C code to produce assembler output. */ 875DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) 876 877/* Definition of an operand predicate. The difference between 878 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will 879 not warn about a match_operand with no mode if it has a predicate 880 defined with DEFINE_SPECIAL_PREDICATE. 881 882 Operand: 883 0: The name of the predicate. 884 1: A boolean expression which computes whether or not the predicate 885 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, 886 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog 887 can calculate the set of RTX codes that can possibly match. 888 2: A C function body which must return true for the predicate to match. 889 Optional. Use this when the test is too complicated to fit into a 890 match_test expression. */ 891DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) 892DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) 893 894/* Definition of a register operand constraint. This simply maps the 895 constraint string to a register class. 896 897 Operand: 898 0: The name of the constraint (often, but not always, a single letter). 899 1: A C expression which evaluates to the appropriate register class for 900 this constraint. If this is not just a constant, it should look only 901 at -m switches and the like. 902 2: A docstring for this constraint, in Texinfo syntax; not currently 903 used, in future will be incorporated into the manual's list of 904 machine-specific operand constraints. */ 905DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) 906 907/* Definition of a non-register operand constraint. These look at the 908 operand and decide whether it fits the constraint. 909 910 DEFINE_CONSTRAINT gets no special treatment if it fails to match. 911 It is appropriate for constant-only constraints, and most others. 912 913 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made 914 to match, if it doesn't already, by converting the operand to the form 915 (mem (reg X)) where X is a base register. It is suitable for constraints 916 that describe a subset of all memory references. 917 918 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made 919 to match, if it doesn't already, by converting the operand to the form 920 (reg X) where X is a base register. It is suitable for constraints that 921 describe a subset of all address references. 922 923 When in doubt, use plain DEFINE_CONSTRAINT. 924 925 Operand: 926 0: The name of the constraint (often, but not always, a single letter). 927 1: A docstring for this constraint, in Texinfo syntax; not currently 928 used, in future will be incorporated into the manual's list of 929 machine-specific operand constraints. 930 2: A boolean expression which computes whether or not the constraint 931 matches. It should follow the same rules as a define_predicate 932 expression, including the bit about specifying the set of RTX codes 933 that could possibly match. MATCH_TEST subexpressions may make use of 934 these variables: 935 `op' - the RTL object defining the operand. 936 `mode' - the mode of `op'. 937 `ival' - INTVAL(op), if op is a CONST_INT. 938 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. 939 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. 940 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point 941 CONST_DOUBLE. 942 Do not use ival/hval/lval/rval if op is not the appropriate kind of 943 RTL object. */ 944DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) 945DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) 946DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) 947 948 949/* Constructions for CPU pipeline description described by NDFAs. */ 950 951/* (define_cpu_unit string [string]) describes cpu functional 952 units (separated by comma). 953 954 1st operand: Names of cpu functional units. 955 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 956 957 All define_reservations, define_cpu_units, and 958 define_query_cpu_units should have unique names which may not be 959 "nothing". */ 960DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) 961 962/* (define_query_cpu_unit string [string]) describes cpu functional 963 units analogously to define_cpu_unit. The reservation of such 964 units can be queried for automaton state. */ 965DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) 966 967/* (exclusion_set string string) means that each CPU functional unit 968 in the first string can not be reserved simultaneously with any 969 unit whose name is in the second string and vise versa. CPU units 970 in the string are separated by commas. For example, it is useful 971 for description CPU with fully pipelined floating point functional 972 unit which can execute simultaneously only single floating point 973 insns or only double floating point insns. All CPU functional 974 units in a set should belong to the same automaton. */ 975DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) 976 977/* (presence_set string string) means that each CPU functional unit in 978 the first string can not be reserved unless at least one of pattern 979 of units whose names are in the second string is reserved. This is 980 an asymmetric relation. CPU units or unit patterns in the strings 981 are separated by commas. Pattern is one unit name or unit names 982 separated by white-spaces. 983 984 For example, it is useful for description that slot1 is reserved 985 after slot0 reservation for a VLIW processor. We could describe it 986 by the following construction 987 988 (presence_set "slot1" "slot0") 989 990 Or slot1 is reserved only after slot0 and unit b0 reservation. In 991 this case we could write 992 993 (presence_set "slot1" "slot0 b0") 994 995 All CPU functional units in a set should belong to the same 996 automaton. */ 997DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) 998 999/* (final_presence_set string string) is analogous to `presence_set'. 1000 The difference between them is when checking is done. When an 1001 instruction is issued in given automaton state reflecting all 1002 current and planned unit reservations, the automaton state is 1003 changed. The first state is a source state, the second one is a 1004 result state. Checking for `presence_set' is done on the source 1005 state reservation, checking for `final_presence_set' is done on the 1006 result reservation. This construction is useful to describe a 1007 reservation which is actually two subsequent reservations. For 1008 example, if we use 1009 1010 (presence_set "slot1" "slot0") 1011 1012 the following insn will be never issued (because slot1 requires 1013 slot0 which is absent in the source state). 1014 1015 (define_reservation "insn_and_nop" "slot0 + slot1") 1016 1017 but it can be issued if we use analogous `final_presence_set'. */ 1018DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) 1019 1020/* (absence_set string string) means that each CPU functional unit in 1021 the first string can be reserved only if each pattern of units 1022 whose names are in the second string is not reserved. This is an 1023 asymmetric relation (actually exclusion set is analogous to this 1024 one but it is symmetric). CPU units or unit patterns in the string 1025 are separated by commas. Pattern is one unit name or unit names 1026 separated by white-spaces. 1027 1028 For example, it is useful for description that slot0 can not be 1029 reserved after slot1 or slot2 reservation for a VLIW processor. We 1030 could describe it by the following construction 1031 1032 (absence_set "slot2" "slot0, slot1") 1033 1034 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 1035 slot1 and unit b1 are reserved . In this case we could write 1036 1037 (absence_set "slot2" "slot0 b0, slot1 b1") 1038 1039 All CPU functional units in a set should to belong the same 1040 automaton. */ 1041DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) 1042 1043/* (final_absence_set string string) is analogous to `absence_set' but 1044 checking is done on the result (state) reservation. See comments 1045 for `final_presence_set'. */ 1046DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 1047 1048/* (define_bypass number out_insn_names in_insn_names) names bypass 1049 with given latency (the first number) from insns given by the first 1050 string (see define_insn_reservation) into insns given by the second 1051 string. Insn names in the strings are separated by commas. The 1052 third operand is optional name of function which is additional 1053 guard for the bypass. The function will get the two insns as 1054 parameters. If the function returns zero the bypass will be 1055 ignored for this case. Additional guard is necessary to recognize 1056 complicated bypasses, e.g. when consumer is load address. */ 1057DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) 1058 1059/* (define_automaton string) describes names of automata generated and 1060 used for pipeline hazards recognition. The names are separated by 1061 comma. Actually it is possibly to generate the single automaton 1062 but unfortunately it can be very large. If we use more one 1063 automata, the summary size of the automata usually is less than the 1064 single one. The automaton name is used in define_cpu_unit and 1065 define_query_cpu_unit. All automata should have unique names. */ 1066DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) 1067 1068/* (automata_option string) describes option for generation of 1069 automata. Currently there are the following options: 1070 1071 o "no-minimization" which makes no minimization of automata. This 1072 is only worth to do when we are debugging the description and 1073 need to look more accurately at reservations of states. 1074 1075 o "time" which means printing additional time statistics about 1076 generation of automata. 1077 1078 o "v" which means generation of file describing the result 1079 automata. The file has suffix `.dfa' and can be used for the 1080 description verification and debugging. 1081 1082 o "w" which means generation of warning instead of error for 1083 non-critical errors. 1084 1085 o "ndfa" which makes nondeterministic finite state automata. 1086 1087 o "progress" which means output of a progress bar showing how many 1088 states were generated so far for automaton being processed. */ 1089DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) 1090 1091/* (define_reservation string string) names reservation (the first 1092 string) of cpu functional units (the 2nd string). Sometimes unit 1093 reservations for different insns contain common parts. In such 1094 case, you can describe common part and use its name (the 1st 1095 parameter) in regular expression in define_insn_reservation. All 1096 define_reservations, define_cpu_units, and define_query_cpu_units 1097 should have unique names which may not be "nothing". */ 1098DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) 1099 1100/* (define_insn_reservation name default_latency condition regexpr) 1101 describes reservation of cpu functional units (the 3nd operand) for 1102 instruction which is selected by the condition (the 2nd parameter). 1103 The first parameter is used for output of debugging information. 1104 The reservations are described by a regular expression according 1105 the following syntax: 1106 1107 regexp = regexp "," oneof 1108 | oneof 1109 1110 oneof = oneof "|" allof 1111 | allof 1112 1113 allof = allof "+" repeat 1114 | repeat 1115 1116 repeat = element "*" number 1117 | element 1118 1119 element = cpu_function_unit_name 1120 | reservation_name 1121 | result_name 1122 | "nothing" 1123 | "(" regexp ")" 1124 1125 1. "," is used for describing start of the next cycle in 1126 reservation. 1127 1128 2. "|" is used for describing the reservation described by the 1129 first regular expression *or* the reservation described by the 1130 second regular expression *or* etc. 1131 1132 3. "+" is used for describing the reservation described by the 1133 first regular expression *and* the reservation described by the 1134 second regular expression *and* etc. 1135 1136 4. "*" is used for convenience and simply means sequence in 1137 which the regular expression are repeated NUMBER times with 1138 cycle advancing (see ","). 1139 1140 5. cpu functional unit name which means its reservation. 1141 1142 6. reservation name -- see define_reservation. 1143 1144 7. string "nothing" means no units reservation. */ 1145 1146DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) 1147 1148/* Expressions used for insn attributes. */ 1149 1150/* Definition of an insn attribute. 1151 1st operand: name of the attribute 1152 2nd operand: comma-separated list of possible attribute values 1153 3rd operand: expression for the default value of the attribute. */ 1154DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) 1155 1156/* Marker for the name of an attribute. */ 1157DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) 1158 1159/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 1160 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 1161 pattern. 1162 1163 (set_attr "name" "value") is equivalent to 1164 (set (attr "name") (const_string "value")) */ 1165DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) 1166 1167/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 1168 specify that attribute values are to be assigned according to the 1169 alternative matched. 1170 1171 The following three expressions are equivalent: 1172 1173 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 1174 (eq_attrq "alternative" "2") (const_string "a2")] 1175 (const_string "a3"))) 1176 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 1177 (const_string "a3")]) 1178 (set_attr "att" "a1,a2,a3") 1179 */ 1180DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) 1181 1182/* A conditional expression true if the value of the specified attribute of 1183 the current insn equals the specified value. The first operand is the 1184 attribute name and the second is the comparison value. */ 1185DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) 1186 1187/* A special case of the above representing a set of alternatives. The first 1188 operand is bitmap of the set, the second one is the default value. */ 1189DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) 1190 1191/* A conditional expression which is true if the specified flag is 1192 true for the insn being scheduled in reorg. 1193 1194 genattr.c defines the following flags which can be tested by 1195 (attr_flag "foo") expressions in eligible_for_delay. 1196 1197 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 1198 1199DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) 1200 1201/* General conditional. The first operand is a vector composed of pairs of 1202 expressions. The first element of each pair is evaluated, in turn. 1203 The value of the conditional is the second expression of the first pair 1204 whose first expression evaluates nonzero. If none of the expressions is 1205 true, the second operand will be used as the value of the conditional. */ 1206DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) 1207 1208#endif /* GENERATOR_FILE */ 1209 1210/* 1211Local variables: 1212mode:c 1213End: 1214*/ 1215