arm.h revision 132718
190075Sobrien/* Definitions of target machine for GNU compiler, for ARM. 290075Sobrien Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3132718Skan 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 490075Sobrien Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 590075Sobrien and Martin Simmons (@harleqn.co.uk). 690075Sobrien More major hacks by Richard Earnshaw (rearnsha@arm.com) 790075Sobrien Minor hacks by Nick Clifton (nickc@cygnus.com) 890075Sobrien 9132718Skan This file is part of GCC. 1090075Sobrien 11132718Skan GCC is free software; you can redistribute it and/or modify it 12132718Skan under the terms of the GNU General Public License as published 13132718Skan by the Free Software Foundation; either version 2, or (at your 14132718Skan option) any later version. 1590075Sobrien 16132718Skan GCC is distributed in the hope that it will be useful, but WITHOUT 17132718Skan ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18132718Skan or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19132718Skan License for more details. 2090075Sobrien 21132718Skan You should have received a copy of the GNU General Public License 22132718Skan along with GCC; see the file COPYING. If not, write to 23132718Skan the Free Software Foundation, 59 Temple Place - Suite 330, Boston, 24132718Skan MA 02111-1307, USA. */ 2590075Sobrien 2690075Sobrien#ifndef GCC_ARM_H 2790075Sobrien#define GCC_ARM_H 2890075Sobrien 29117395Skan/* Target CPU builtins. */ 30117395Skan#define TARGET_CPU_CPP_BUILTINS() \ 31117395Skan do \ 32117395Skan { \ 33117395Skan if (TARGET_ARM) \ 34117395Skan builtin_define ("__arm__"); \ 35117395Skan else \ 36117395Skan builtin_define ("__thumb__"); \ 37117395Skan \ 38117395Skan if (TARGET_BIG_END) \ 39117395Skan { \ 40117395Skan builtin_define ("__ARMEB__"); \ 41117395Skan if (TARGET_THUMB) \ 42117395Skan builtin_define ("__THUMBEB__"); \ 43117395Skan if (TARGET_LITTLE_WORDS) \ 44117395Skan builtin_define ("__ARMWEL__"); \ 45117395Skan } \ 46117395Skan else \ 47117395Skan { \ 48117395Skan builtin_define ("__ARMEL__"); \ 49117395Skan if (TARGET_THUMB) \ 50117395Skan builtin_define ("__THUMBEL__"); \ 51117395Skan } \ 52117395Skan \ 53117395Skan if (TARGET_APCS_32) \ 54117395Skan builtin_define ("__APCS_32__"); \ 55117395Skan else \ 56117395Skan builtin_define ("__APCS_26__"); \ 57117395Skan \ 58117395Skan if (TARGET_SOFT_FLOAT) \ 59117395Skan builtin_define ("__SOFTFP__"); \ 60117395Skan \ 61117395Skan /* FIXME: TARGET_HARD_FLOAT currently implies \ 62117395Skan FPA. */ \ 63117395Skan if (TARGET_VFP && !TARGET_HARD_FLOAT) \ 64117395Skan builtin_define ("__VFP_FP__"); \ 65117395Skan \ 66117395Skan /* Add a define for interworking. \ 67117395Skan Needed when building libgcc.a. */ \ 68117395Skan if (TARGET_INTERWORK) \ 69117395Skan builtin_define ("__THUMB_INTERWORK__"); \ 70117395Skan \ 71117395Skan builtin_assert ("cpu=arm"); \ 72117395Skan builtin_assert ("machine=arm"); \ 73117395Skan } while (0) 74117395Skan 7590075Sobrien#define TARGET_CPU_arm2 0x0000 7690075Sobrien#define TARGET_CPU_arm250 0x0000 7790075Sobrien#define TARGET_CPU_arm3 0x0000 7890075Sobrien#define TARGET_CPU_arm6 0x0001 7990075Sobrien#define TARGET_CPU_arm600 0x0001 8090075Sobrien#define TARGET_CPU_arm610 0x0002 8190075Sobrien#define TARGET_CPU_arm7 0x0001 8290075Sobrien#define TARGET_CPU_arm7m 0x0004 8390075Sobrien#define TARGET_CPU_arm7dm 0x0004 8490075Sobrien#define TARGET_CPU_arm7dmi 0x0004 8590075Sobrien#define TARGET_CPU_arm700 0x0001 8690075Sobrien#define TARGET_CPU_arm710 0x0002 8790075Sobrien#define TARGET_CPU_arm7100 0x0002 8890075Sobrien#define TARGET_CPU_arm7500 0x0002 8990075Sobrien#define TARGET_CPU_arm7500fe 0x1001 9090075Sobrien#define TARGET_CPU_arm7tdmi 0x0008 9190075Sobrien#define TARGET_CPU_arm8 0x0010 9290075Sobrien#define TARGET_CPU_arm810 0x0020 9390075Sobrien#define TARGET_CPU_strongarm 0x0040 9490075Sobrien#define TARGET_CPU_strongarm110 0x0040 9590075Sobrien#define TARGET_CPU_strongarm1100 0x0040 9690075Sobrien#define TARGET_CPU_arm9 0x0080 9790075Sobrien#define TARGET_CPU_arm9tdmi 0x0080 9890075Sobrien#define TARGET_CPU_xscale 0x0100 99132718Skan#define TARGET_CPU_ep9312 0x0200 100132718Skan#define TARGET_CPU_iwmmxt 0x0400 101132718Skan#define TARGET_CPU_arm926ej_s 0x0800 102132718Skan#define TARGET_CPU_arm1026ej_s 0x1000 103132718Skan#define TARGET_CPU_arm1136j_s 0x2000 104132718Skan#define TARGET_CPU_arm1136jf_s 0x4000 10590075Sobrien/* Configure didn't specify. */ 10690075Sobrien#define TARGET_CPU_generic 0x8000 10790075Sobrien 10890075Sobrientypedef enum arm_cond_code 10990075Sobrien{ 11090075Sobrien ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 11190075Sobrien ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 11290075Sobrien} 11390075Sobrienarm_cc; 11490075Sobrien 11590075Sobrienextern arm_cc arm_current_cc; 11690075Sobrien 11790075Sobrien#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 11890075Sobrien 11990075Sobrienextern int arm_target_label; 12090075Sobrienextern int arm_ccfsm_state; 121117395Skanextern GTY(()) rtx arm_target_insn; 12290075Sobrien/* Run-time compilation parameters selecting different hardware subsets. */ 12390075Sobrienextern int target_flags; 12490075Sobrien/* The floating point instruction architecture, can be 2 or 3 */ 12590075Sobrienextern const char * target_fp_name; 12690075Sobrien/* Define the information needed to generate branch insns. This is 127117395Skan stored from the compare operation. */ 128117395Skanextern GTY(()) rtx arm_compare_op0; 129117395Skanextern GTY(()) rtx arm_compare_op1; 13090075Sobrien/* The label of the current constant pool. */ 131117395Skanextern rtx pool_vector_label; 13290075Sobrien/* Set to 1 when a return insn is output, this means that the epilogue 133132718Skan is not needed. */ 13490075Sobrienextern int return_used_this_function; 135117395Skan/* Used to produce AOF syntax assembler. */ 136117395Skanextern GTY(()) rtx aof_pic_label; 13790075Sobrien 138132718Skan/* Just in case configure has failed to define anything. */ 13990075Sobrien#ifndef TARGET_CPU_DEFAULT 14090075Sobrien#define TARGET_CPU_DEFAULT TARGET_CPU_generic 14190075Sobrien#endif 14290075Sobrien 14390075Sobrien/* If the configuration file doesn't specify the cpu, the subtarget may 14490075Sobrien override it. If it doesn't, then default to an ARM6. */ 14590075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_generic 14690075Sobrien#undef TARGET_CPU_DEFAULT 14790075Sobrien 14890075Sobrien#ifdef SUBTARGET_CPU_DEFAULT 14990075Sobrien#define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT 15090075Sobrien#else 15190075Sobrien#define TARGET_CPU_DEFAULT TARGET_CPU_arm6 15290075Sobrien#endif 15390075Sobrien#endif 15490075Sobrien 15590075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 15690075Sobrien#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" 15790075Sobrien#else 15890075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe 15990075Sobrien#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" 16090075Sobrien#else 16190075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m 16290075Sobrien#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" 16390075Sobrien#else 16490075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi 16590075Sobrien#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" 16690075Sobrien#else 16790075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 16890075Sobrien#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" 16990075Sobrien#else 17090075Sobrien#if TARGET_CPU_DEFAULT == TARGET_CPU_xscale 17190075Sobrien#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" 17290075Sobrien#else 173132718Skan#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 174132718Skan#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__" 175132718Skan/* Set TARGET_DEFAULT to the default, but without soft-float. */ 176132718Skan#ifdef TARGET_DEFAULT 177132718Skan#undef TARGET_DEFAULT 178132718Skan#define TARGET_DEFAULT \ 179132718Skan (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS | ARM_FLAG_APCS_FRAME) 18090075Sobrien#endif 181132718Skan#else 182132718Skan#if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt 183132718Skan#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__" 184132718Skan#else 185132718Skan#error Unrecognized value in TARGET_CPU_DEFAULT. 18690075Sobrien#endif 18790075Sobrien#endif 18890075Sobrien#endif 18990075Sobrien#endif 19090075Sobrien#endif 191132718Skan#endif 192132718Skan#endif 193132718Skan#endif 19490075Sobrien 19590075Sobrien#undef CPP_SPEC 196117395Skan#define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ 197117395Skan%{mapcs-32:%{mapcs-26: \ 198117395Skan %e-mapcs-26 and -mapcs-32 may not be used together}} \ 199117395Skan%{msoft-float:%{mhard-float: \ 200117395Skan %e-msoft-float and -mhard_float may not be used together}} \ 201117395Skan%{mbig-endian:%{mlittle-endian: \ 202117395Skan %e-mbig-endian and -mlittle-endian may not be used together}}" 20390075Sobrien 20490075Sobrien/* Set the architecture define -- if -march= is set, then it overrides 20590075Sobrien the -mcpu= setting. */ 20690075Sobrien#define CPP_CPU_ARCH_SPEC "\ 20790075Sobrien%{march=arm2:-D__ARM_ARCH_2__} \ 20890075Sobrien%{march=arm250:-D__ARM_ARCH_2__} \ 20990075Sobrien%{march=arm3:-D__ARM_ARCH_2__} \ 21090075Sobrien%{march=arm6:-D__ARM_ARCH_3__} \ 21190075Sobrien%{march=arm600:-D__ARM_ARCH_3__} \ 21290075Sobrien%{march=arm610:-D__ARM_ARCH_3__} \ 21390075Sobrien%{march=arm7:-D__ARM_ARCH_3__} \ 21490075Sobrien%{march=arm700:-D__ARM_ARCH_3__} \ 21590075Sobrien%{march=arm710:-D__ARM_ARCH_3__} \ 21690075Sobrien%{march=arm720:-D__ARM_ARCH_3__} \ 21790075Sobrien%{march=arm7100:-D__ARM_ARCH_3__} \ 21890075Sobrien%{march=arm7500:-D__ARM_ARCH_3__} \ 21990075Sobrien%{march=arm7500fe:-D__ARM_ARCH_3__} \ 22090075Sobrien%{march=arm7m:-D__ARM_ARCH_3M__} \ 22190075Sobrien%{march=arm7dm:-D__ARM_ARCH_3M__} \ 22290075Sobrien%{march=arm7dmi:-D__ARM_ARCH_3M__} \ 22390075Sobrien%{march=arm7tdmi:-D__ARM_ARCH_4T__} \ 22490075Sobrien%{march=arm8:-D__ARM_ARCH_4__} \ 22590075Sobrien%{march=arm810:-D__ARM_ARCH_4__} \ 22690075Sobrien%{march=arm9:-D__ARM_ARCH_4T__} \ 22790075Sobrien%{march=arm920:-D__ARM_ARCH_4__} \ 22890075Sobrien%{march=arm920t:-D__ARM_ARCH_4T__} \ 22990075Sobrien%{march=arm9tdmi:-D__ARM_ARCH_4T__} \ 23090075Sobrien%{march=strongarm:-D__ARM_ARCH_4__} \ 23190075Sobrien%{march=strongarm110:-D__ARM_ARCH_4__} \ 23290075Sobrien%{march=strongarm1100:-D__ARM_ARCH_4__} \ 23390075Sobrien%{march=xscale:-D__ARM_ARCH_5TE__} \ 23490075Sobrien%{march=xscale:-D__XSCALE__} \ 235132718Skan%{march=ep9312:-D__ARM_ARCH_4T__} \ 236132718Skan%{march=ep9312:-D__MAVERICK__} \ 23790075Sobrien%{march=armv2:-D__ARM_ARCH_2__} \ 23890075Sobrien%{march=armv2a:-D__ARM_ARCH_2__} \ 23990075Sobrien%{march=armv3:-D__ARM_ARCH_3__} \ 24090075Sobrien%{march=armv3m:-D__ARM_ARCH_3M__} \ 24190075Sobrien%{march=armv4:-D__ARM_ARCH_4__} \ 24290075Sobrien%{march=armv4t:-D__ARM_ARCH_4T__} \ 24390075Sobrien%{march=armv5:-D__ARM_ARCH_5__} \ 24490075Sobrien%{march=armv5t:-D__ARM_ARCH_5T__} \ 24590075Sobrien%{march=armv5e:-D__ARM_ARCH_5E__} \ 24690075Sobrien%{march=armv5te:-D__ARM_ARCH_5TE__} \ 24790075Sobrien%{!march=*: \ 24890075Sobrien %{mcpu=arm2:-D__ARM_ARCH_2__} \ 24990075Sobrien %{mcpu=arm250:-D__ARM_ARCH_2__} \ 25090075Sobrien %{mcpu=arm3:-D__ARM_ARCH_2__} \ 25190075Sobrien %{mcpu=arm6:-D__ARM_ARCH_3__} \ 25290075Sobrien %{mcpu=arm600:-D__ARM_ARCH_3__} \ 25390075Sobrien %{mcpu=arm610:-D__ARM_ARCH_3__} \ 25490075Sobrien %{mcpu=arm7:-D__ARM_ARCH_3__} \ 25590075Sobrien %{mcpu=arm700:-D__ARM_ARCH_3__} \ 25690075Sobrien %{mcpu=arm710:-D__ARM_ARCH_3__} \ 25790075Sobrien %{mcpu=arm720:-D__ARM_ARCH_3__} \ 25890075Sobrien %{mcpu=arm7100:-D__ARM_ARCH_3__} \ 25990075Sobrien %{mcpu=arm7500:-D__ARM_ARCH_3__} \ 26090075Sobrien %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ 26190075Sobrien %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ 26290075Sobrien %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ 26390075Sobrien %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ 26490075Sobrien %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ 26590075Sobrien %{mcpu=arm8:-D__ARM_ARCH_4__} \ 26690075Sobrien %{mcpu=arm810:-D__ARM_ARCH_4__} \ 26790075Sobrien %{mcpu=arm9:-D__ARM_ARCH_4T__} \ 26890075Sobrien %{mcpu=arm920:-D__ARM_ARCH_4__} \ 26990075Sobrien %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ 27090075Sobrien %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ 27190075Sobrien %{mcpu=strongarm:-D__ARM_ARCH_4__} \ 27290075Sobrien %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ 27390075Sobrien %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ 27490075Sobrien %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ 27590075Sobrien %{mcpu=xscale:-D__XSCALE__} \ 276132718Skan %{mcpu=ep9312:-D__ARM_ARCH_4T__} \ 277132718Skan %{mcpu=ep9312:-D__MAVERICK__} \ 278132718Skan %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \ 279132718Skan %{mcpu=iwmmxt:-D__XSCALE__} \ 280132718Skan %{mcpu=iwmmxt:-D__IWMMXT__} \ 28190075Sobrien %{!mcpu*:%(cpp_cpu_arch_default)}} \ 28290075Sobrien" 28390075Sobrien 28490075Sobrien#ifndef CC1_SPEC 28590075Sobrien#define CC1_SPEC "" 28690075Sobrien#endif 28790075Sobrien 28890075Sobrien/* This macro defines names of additional specifications to put in the specs 28990075Sobrien that can be used in various specifications like CC1_SPEC. Its definition 29090075Sobrien is an initializer with a subgrouping for each command option. 29190075Sobrien 29290075Sobrien Each subgrouping contains a string constant, that defines the 293132718Skan specification name, and a string constant that used by the GCC driver 29490075Sobrien program. 29590075Sobrien 29690075Sobrien Do not define this macro if it does not need to do anything. */ 29790075Sobrien#define EXTRA_SPECS \ 29890075Sobrien { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ 29990075Sobrien { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ 30090075Sobrien { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 30190075Sobrien SUBTARGET_EXTRA_SPECS 30290075Sobrien 30390075Sobrien#ifndef SUBTARGET_EXTRA_SPECS 30490075Sobrien#define SUBTARGET_EXTRA_SPECS 30590075Sobrien#endif 30690075Sobrien 30790075Sobrien#ifndef SUBTARGET_CPP_SPEC 30890075Sobrien#define SUBTARGET_CPP_SPEC "" 30990075Sobrien#endif 31090075Sobrien 31190075Sobrien/* Run-time Target Specification. */ 31290075Sobrien#ifndef TARGET_VERSION 31390075Sobrien#define TARGET_VERSION fputs (" (ARM/generic)", stderr); 31490075Sobrien#endif 31590075Sobrien 31690075Sobrien/* Nonzero if the function prologue (and epilogue) should obey 31790075Sobrien the ARM Procedure Call Standard. */ 31890075Sobrien#define ARM_FLAG_APCS_FRAME (1 << 0) 31990075Sobrien 32090075Sobrien/* Nonzero if the function prologue should output the function name to enable 32190075Sobrien the post mortem debugger to print a backtrace (very useful on RISCOS, 32290075Sobrien unused on RISCiX). Specifying this flag also enables 32390075Sobrien -fno-omit-frame-pointer. 32490075Sobrien XXX Must still be implemented in the prologue. */ 32590075Sobrien#define ARM_FLAG_POKE (1 << 1) 32690075Sobrien 32790075Sobrien/* Nonzero if floating point instructions are emulated by the FPE, in which 32890075Sobrien case instruction scheduling becomes very uninteresting. */ 32990075Sobrien#define ARM_FLAG_FPE (1 << 2) 33090075Sobrien 33190075Sobrien/* Nonzero if destined for a processor in 32-bit program mode. Takes out bit 33290075Sobrien that assume restoration of the condition flags when returning from a 33390075Sobrien branch and link (ie a function). */ 33490075Sobrien#define ARM_FLAG_APCS_32 (1 << 3) 33590075Sobrien 33690075Sobrien/* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ 33790075Sobrien 33890075Sobrien/* Nonzero if stack checking should be performed on entry to each function 33990075Sobrien which allocates temporary variables on the stack. */ 34090075Sobrien#define ARM_FLAG_APCS_STACK (1 << 4) 34190075Sobrien 34290075Sobrien/* Nonzero if floating point parameters should be passed to functions in 34390075Sobrien floating point registers. */ 34490075Sobrien#define ARM_FLAG_APCS_FLOAT (1 << 5) 34590075Sobrien 34690075Sobrien/* Nonzero if re-entrant, position independent code should be generated. 34790075Sobrien This is equivalent to -fpic. */ 34890075Sobrien#define ARM_FLAG_APCS_REENT (1 << 6) 34990075Sobrien 35090075Sobrien/* Nonzero if the MMU will trap unaligned word accesses, so shorts must 35190075Sobrien be loaded using either LDRH or LDRB instructions. */ 35290075Sobrien#define ARM_FLAG_MMU_TRAPS (1 << 7) 35390075Sobrien 35490075Sobrien/* Nonzero if all floating point instructions are missing (and there is no 35590075Sobrien emulator either). Generate function calls for all ops in this case. */ 35690075Sobrien#define ARM_FLAG_SOFT_FLOAT (1 << 8) 35790075Sobrien 35890075Sobrien/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ 35990075Sobrien#define ARM_FLAG_BIG_END (1 << 9) 36090075Sobrien 36190075Sobrien/* Nonzero if we should compile for Thumb interworking. */ 36290075Sobrien#define ARM_FLAG_INTERWORK (1 << 10) 36390075Sobrien 36490075Sobrien/* Nonzero if we should have little-endian words even when compiling for 36590075Sobrien big-endian (for backwards compatibility with older versions of GCC). */ 36690075Sobrien#define ARM_FLAG_LITTLE_WORDS (1 << 11) 36790075Sobrien 36890075Sobrien/* Nonzero if we need to protect the prolog from scheduling */ 36990075Sobrien#define ARM_FLAG_NO_SCHED_PRO (1 << 12) 37090075Sobrien 37190075Sobrien/* Nonzero if a call to abort should be generated if a noreturn 37290075Sobrien function tries to return. */ 37390075Sobrien#define ARM_FLAG_ABORT_NORETURN (1 << 13) 37490075Sobrien 375132718Skan/* Nonzero if function prologues should not load the PIC register. */ 37690075Sobrien#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) 37790075Sobrien 37890075Sobrien/* Nonzero if all call instructions should be indirect. */ 37990075Sobrien#define ARM_FLAG_LONG_CALLS (1 << 15) 38090075Sobrien 38190075Sobrien/* Nonzero means that the target ISA is the THUMB, not the ARM. */ 38290075Sobrien#define ARM_FLAG_THUMB (1 << 16) 38390075Sobrien 38490075Sobrien/* Set if a TPCS style stack frame should be generated, for non-leaf 38590075Sobrien functions, even if they do not need one. */ 38690075Sobrien#define THUMB_FLAG_BACKTRACE (1 << 17) 38790075Sobrien 38890075Sobrien/* Set if a TPCS style stack frame should be generated, for leaf 38990075Sobrien functions, even if they do not need one. */ 39090075Sobrien#define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) 39190075Sobrien 39290075Sobrien/* Set if externally visible functions should assume that they 39390075Sobrien might be called in ARM mode, from a non-thumb aware code. */ 39490075Sobrien#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) 39590075Sobrien 39690075Sobrien/* Set if calls via function pointers should assume that their 39790075Sobrien destination is non-Thumb aware. */ 39890075Sobrien#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) 39990075Sobrien 400117395Skan/* Nonzero means target uses VFP FP. */ 401117395Skan#define ARM_FLAG_VFP (1 << 21) 402117395Skan 403117395Skan/* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */ 404117395Skan#define ARM_FLAG_ATPCS (1 << 22) 405117395Skan 406132718Skan/* Fix invalid Cirrus instruction combinations by inserting NOPs. */ 407132718Skan#define CIRRUS_FIX_INVALID_INSNS (1 << 23) 408132718Skan 40990075Sobrien#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) 41090075Sobrien#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) 41190075Sobrien#define TARGET_FPE (target_flags & ARM_FLAG_FPE) 41290075Sobrien#define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) 41390075Sobrien#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) 41490075Sobrien#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) 41590075Sobrien#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) 416117395Skan#define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS) 41790075Sobrien#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) 41890075Sobrien#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) 41990075Sobrien#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) 420132718Skan#define TARGET_CIRRUS (arm_is_cirrus) 421132718Skan#define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS) 422132718Skan#define TARGET_IWMMXT (arm_arch_iwmmxt) 423132718Skan#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM) 424117395Skan#define TARGET_VFP (target_flags & ARM_FLAG_VFP) 42590075Sobrien#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) 42690075Sobrien#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) 42790075Sobrien#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) 42890075Sobrien#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) 42990075Sobrien#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) 43090075Sobrien#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) 43190075Sobrien#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) 43290075Sobrien#define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) 43390075Sobrien#define TARGET_ARM (! TARGET_THUMB) 43490075Sobrien#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 43590075Sobrien#define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) 43690075Sobrien#define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) 43790075Sobrien#define TARGET_BACKTRACE (leaf_function_p () \ 43890075Sobrien ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ 43990075Sobrien : (target_flags & THUMB_FLAG_BACKTRACE)) 440132718Skan#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS) 44190075Sobrien 442117395Skan/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ 44390075Sobrien#ifndef SUBTARGET_SWITCHES 44490075Sobrien#define SUBTARGET_SWITCHES 44590075Sobrien#endif 44690075Sobrien 44790075Sobrien#define TARGET_SWITCHES \ 44890075Sobrien{ \ 44990075Sobrien {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ 45090075Sobrien {"apcs-frame", ARM_FLAG_APCS_FRAME, \ 45190075Sobrien N_("Generate APCS conformant stack frames") }, \ 45290075Sobrien {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ 45390075Sobrien {"poke-function-name", ARM_FLAG_POKE, \ 45490075Sobrien N_("Store function names in object code") }, \ 45590075Sobrien {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ 45690075Sobrien {"fpe", ARM_FLAG_FPE, "" }, \ 45790075Sobrien {"apcs-32", ARM_FLAG_APCS_32, \ 45890075Sobrien N_("Use the 32-bit version of the APCS") }, \ 459132718Skan {"apcs-26", -ARM_FLAG_APCS_32, ""}, \ 46090075Sobrien {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ 46190075Sobrien {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ 46290075Sobrien {"apcs-float", ARM_FLAG_APCS_FLOAT, \ 46390075Sobrien N_("Pass FP arguments in FP registers") }, \ 46490075Sobrien {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ 46590075Sobrien {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ 46690075Sobrien N_("Generate re-entrant, PIC code") }, \ 46790075Sobrien {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ 46890075Sobrien {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ 46990075Sobrien N_("The MMU will trap on unaligned accesses") }, \ 47090075Sobrien {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ 47190075Sobrien {"soft-float", ARM_FLAG_SOFT_FLOAT, \ 47290075Sobrien N_("Use library calls to perform FP operations") }, \ 47390075Sobrien {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ 47490075Sobrien N_("Use hardware floating point instructions") }, \ 47590075Sobrien {"big-endian", ARM_FLAG_BIG_END, \ 47690075Sobrien N_("Assume target CPU is configured as big endian") }, \ 47790075Sobrien {"little-endian", -ARM_FLAG_BIG_END, \ 47890075Sobrien N_("Assume target CPU is configured as little endian") }, \ 47990075Sobrien {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ 48090075Sobrien N_("Assume big endian bytes, little endian words") }, \ 48190075Sobrien {"thumb-interwork", ARM_FLAG_INTERWORK, \ 48290075Sobrien N_("Support calls between Thumb and ARM instruction sets") }, \ 48390075Sobrien {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ 48490075Sobrien {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ 48590075Sobrien N_("Generate a call to abort if a noreturn function returns")}, \ 48690075Sobrien {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ 48790075Sobrien {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ 48890075Sobrien N_("Do not move instructions into a function's prologue") }, \ 48990075Sobrien {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ 49090075Sobrien {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ 49190075Sobrien N_("Do not load the PIC register in function prologues") }, \ 49290075Sobrien {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ 49390075Sobrien {"long-calls", ARM_FLAG_LONG_CALLS, \ 49490075Sobrien N_("Generate call insns as indirect calls, if necessary") }, \ 49590075Sobrien {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ 49690075Sobrien {"thumb", ARM_FLAG_THUMB, \ 49790075Sobrien N_("Compile for the Thumb not the ARM") }, \ 49890075Sobrien {"no-thumb", -ARM_FLAG_THUMB, "" }, \ 49990075Sobrien {"arm", -ARM_FLAG_THUMB, "" }, \ 50090075Sobrien {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ 50190075Sobrien N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ 50290075Sobrien {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ 50390075Sobrien {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ 50490075Sobrien N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ 50590075Sobrien {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ 50690075Sobrien {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ 50790075Sobrien N_("Thumb: Assume non-static functions may be called from ARM code") }, \ 50890075Sobrien {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ 50990075Sobrien "" }, \ 51090075Sobrien {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ 51190075Sobrien N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ 51290075Sobrien {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ 51390075Sobrien "" }, \ 514132718Skan {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \ 515132718Skan N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \ 516132718Skan {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \ 517132718Skan N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\ 51890075Sobrien SUBTARGET_SWITCHES \ 51990075Sobrien {"", TARGET_DEFAULT, "" } \ 52090075Sobrien} 52190075Sobrien 52290075Sobrien#define TARGET_OPTIONS \ 52390075Sobrien{ \ 52490075Sobrien {"cpu=", & arm_select[0].string, \ 525132718Skan N_("Specify the name of the target CPU"), 0}, \ 52690075Sobrien {"arch=", & arm_select[1].string, \ 527132718Skan N_("Specify the name of the target architecture"), 0}, \ 528132718Skan {"tune=", & arm_select[2].string, "", 0}, \ 529132718Skan {"fpe=", & target_fp_name, "" , 0}, \ 53090075Sobrien {"fp=", & target_fp_name, \ 531132718Skan N_("Specify the version of the floating point emulator"), 0},\ 53290075Sobrien {"structure-size-boundary=", & structure_size_string, \ 533132718Skan N_("Specify the minimum bit alignment of structures"), 0}, \ 53490075Sobrien {"pic-register=", & arm_pic_register_string, \ 535132718Skan N_("Specify the register to be used for PIC addressing"), 0} \ 53690075Sobrien} 53790075Sobrien 538132718Skan/* Support for a compile-time default CPU, et cetera. The rules are: 539132718Skan --with-arch is ignored if -march or -mcpu are specified. 540132718Skan --with-cpu is ignored if -march or -mcpu are specified, and is overridden 541132718Skan by --with-arch. 542132718Skan --with-tune is ignored if -mtune or -mcpu are specified (but not affected 543132718Skan by -march). 544132718Skan --with-float is ignored if -mhard-float or -msoft-float are 545132718Skan specified. */ 546132718Skan#define OPTION_DEFAULT_SPECS \ 547132718Skan {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 548132718Skan {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 549132718Skan {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 550132718Skan {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } 551132718Skan 55290075Sobrienstruct arm_cpu_select 55390075Sobrien{ 55490075Sobrien const char * string; 55590075Sobrien const char * name; 55690075Sobrien const struct processors * processors; 55790075Sobrien}; 55890075Sobrien 55990075Sobrien/* This is a magic array. If the user specifies a command line switch 56090075Sobrien which matches one of the entries in TARGET_OPTIONS then the corresponding 56190075Sobrien string pointer will be set to the value specified by the user. */ 56290075Sobrienextern struct arm_cpu_select arm_select[]; 56390075Sobrien 56490075Sobrienenum prog_mode_type 56590075Sobrien{ 56690075Sobrien prog_mode26, 56790075Sobrien prog_mode32 56890075Sobrien}; 56990075Sobrien 570132718Skan/* Recast the program mode class to be the prog_mode attribute. */ 57190075Sobrien#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) 57290075Sobrien 57390075Sobrienextern enum prog_mode_type arm_prgmode; 57490075Sobrien 57590075Sobrien/* What sort of floating point unit do we have? Hardware or software. 57690075Sobrien If software, is it issue 2 or issue 3? */ 577132718Skanenum fputype 57890075Sobrien{ 579132718Skan /* Software floating point, FPA style double fmt. */ 580132718Skan FPUTYPE_SOFT_FPA, 581132718Skan /* Full FPA support. */ 582132718Skan FPUTYPE_FPA, 583132718Skan /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */ 584132718Skan FPUTYPE_FPA_EMU2, 585132718Skan /* Emulated FPA hardware, Issue 3 emulator. */ 586132718Skan FPUTYPE_FPA_EMU3, 587132718Skan /* Cirrus Maverick floating point co-processor. */ 588132718Skan FPUTYPE_MAVERICK 58990075Sobrien}; 59090075Sobrien 59190075Sobrien/* Recast the floating point class to be the floating point attribute. */ 592132718Skan#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune) 59390075Sobrien 59490075Sobrien/* What type of floating point to tune for */ 595132718Skanextern enum fputype arm_fpu_tune; 59690075Sobrien 59790075Sobrien/* What type of floating point instructions are available */ 598132718Skanextern enum fputype arm_fpu_arch; 59990075Sobrien 60090075Sobrien/* Default floating point architecture. Override in sub-target if 60190075Sobrien necessary. */ 602132718Skan#ifndef FPUTYPE_DEFAULT 603132718Skan#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2 60490075Sobrien#endif 60590075Sobrien 606132718Skan#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 607132718Skan#undef FPUTYPE_DEFAULT 608132718Skan#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK 609132718Skan#endif 610132718Skan 61190075Sobrien/* Nonzero if the processor has a fast multiply insn, and one that does 61290075Sobrien a 64-bit multiply of two 32-bit values. */ 61390075Sobrienextern int arm_fast_multiply; 61490075Sobrien 61590075Sobrien/* Nonzero if this chip supports the ARM Architecture 4 extensions */ 61690075Sobrienextern int arm_arch4; 61790075Sobrien 61890075Sobrien/* Nonzero if this chip supports the ARM Architecture 5 extensions */ 61990075Sobrienextern int arm_arch5; 62090075Sobrien 62190075Sobrien/* Nonzero if this chip supports the ARM Architecture 5E extensions */ 62290075Sobrienextern int arm_arch5e; 62390075Sobrien 62490075Sobrien/* Nonzero if this chip can benefit from load scheduling. */ 62590075Sobrienextern int arm_ld_sched; 62690075Sobrien 62790075Sobrien/* Nonzero if generating thumb code. */ 62890075Sobrienextern int thumb_code; 62990075Sobrien 63090075Sobrien/* Nonzero if this chip is a StrongARM. */ 63190075Sobrienextern int arm_is_strong; 63290075Sobrien 633132718Skan/* Nonzero if this chip is a Cirrus variant. */ 634132718Skanextern int arm_is_cirrus; 635132718Skan 636132718Skan/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 637132718Skanextern int arm_arch_iwmmxt; 638132718Skan 63990075Sobrien/* Nonzero if this chip is an XScale. */ 640132718Skanextern int arm_arch_xscale; 64190075Sobrien 642132718Skan/* Nonzero if tuning for XScale */ 643132718Skanextern int arm_tune_xscale; 644132718Skan 64590075Sobrien/* Nonzero if this chip is an ARM6 or an ARM7. */ 64690075Sobrienextern int arm_is_6_or_7; 64790075Sobrien 64890075Sobrien#ifndef TARGET_DEFAULT 649132718Skan#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) 65090075Sobrien#endif 65190075Sobrien 65290075Sobrien/* The frame pointer register used in gcc has nothing to do with debugging; 65390075Sobrien that is controlled by the APCS-FRAME option. */ 65490075Sobrien#define CAN_DEBUG_WITHOUT_FP 65590075Sobrien 65690075Sobrien#undef TARGET_MEM_FUNCTIONS 65790075Sobrien#define TARGET_MEM_FUNCTIONS 1 65890075Sobrien 65990075Sobrien#define OVERRIDE_OPTIONS arm_override_options () 66090075Sobrien 66190075Sobrien/* Nonzero if PIC code requires explicit qualifiers to generate 66290075Sobrien PLT and GOT relocs rather than the assembler doing so implicitly. 66390075Sobrien Subtargets can override these if required. */ 66490075Sobrien#ifndef NEED_GOT_RELOC 66590075Sobrien#define NEED_GOT_RELOC 0 66690075Sobrien#endif 66790075Sobrien#ifndef NEED_PLT_RELOC 66890075Sobrien#define NEED_PLT_RELOC 0 66990075Sobrien#endif 67090075Sobrien 67190075Sobrien/* Nonzero if we need to refer to the GOT with a PC-relative 67290075Sobrien offset. In other words, generate 67390075Sobrien 67490075Sobrien .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 67590075Sobrien 67690075Sobrien rather than 67790075Sobrien 67890075Sobrien .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 67990075Sobrien 68090075Sobrien The default is true, which matches NetBSD. Subtargets can 68190075Sobrien override this if required. */ 68290075Sobrien#ifndef GOT_PCREL 68390075Sobrien#define GOT_PCREL 1 68490075Sobrien#endif 68590075Sobrien 68690075Sobrien/* Target machine storage Layout. */ 68790075Sobrien 68890075Sobrien 68990075Sobrien/* Define this macro if it is advisable to hold scalars in registers 69090075Sobrien in a wider mode than that declared by the program. In such cases, 69190075Sobrien the value is constrained to be within the bounds of the declared 69290075Sobrien type, but kept valid in the wider mode. The signedness of the 69390075Sobrien extension may differ from that of the type. */ 69490075Sobrien 69590075Sobrien/* It is far faster to zero extend chars than to sign extend them */ 69690075Sobrien 69790075Sobrien#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 69890075Sobrien if (GET_MODE_CLASS (MODE) == MODE_INT \ 69990075Sobrien && GET_MODE_SIZE (MODE) < 4) \ 70090075Sobrien { \ 70190075Sobrien if (MODE == QImode) \ 70290075Sobrien UNSIGNEDP = 1; \ 70390075Sobrien else if (MODE == HImode) \ 70490075Sobrien UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ 70590075Sobrien (MODE) = SImode; \ 70690075Sobrien } 70790075Sobrien 70890075Sobrien/* Define this macro if the promotion described by `PROMOTE_MODE' 70990075Sobrien should also be done for outgoing function arguments. */ 71090075Sobrien/* This is required to ensure that push insns always push a word. */ 71190075Sobrien#define PROMOTE_FUNCTION_ARGS 71290075Sobrien 71390075Sobrien/* Define this if most significant bit is lowest numbered 71490075Sobrien in instructions that operate on numbered bit-fields. */ 71590075Sobrien#define BITS_BIG_ENDIAN 0 71690075Sobrien 71790075Sobrien/* Define this if most significant byte of a word is the lowest numbered. 71890075Sobrien Most ARM processors are run in little endian mode, so that is the default. 71990075Sobrien If you want to have it run-time selectable, change the definition in a 72090075Sobrien cover file to be TARGET_BIG_ENDIAN. */ 72190075Sobrien#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 72290075Sobrien 72390075Sobrien/* Define this if most significant word of a multiword number is the lowest 72490075Sobrien numbered. 72590075Sobrien This is always false, even when in big-endian mode. */ 72690075Sobrien#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 72790075Sobrien 72890075Sobrien/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 72990075Sobrien on processor pre-defineds when compiling libgcc2.c. */ 73090075Sobrien#if defined(__ARMEB__) && !defined(__ARMWEL__) 73190075Sobrien#define LIBGCC2_WORDS_BIG_ENDIAN 1 73290075Sobrien#else 73390075Sobrien#define LIBGCC2_WORDS_BIG_ENDIAN 0 73490075Sobrien#endif 73590075Sobrien 73690075Sobrien/* Define this if most significant word of doubles is the lowest numbered. 737132718Skan The rules are different based on whether or not we use FPA-format, 738132718Skan VFP-format or some other floating point co-processor's format doubles. */ 739117395Skan#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 74090075Sobrien 74190075Sobrien#define UNITS_PER_WORD 4 74290075Sobrien 74390075Sobrien#define PARM_BOUNDARY 32 74490075Sobrien 745132718Skan#define IWMMXT_ALIGNMENT 64 746132718Skan 74790075Sobrien#define STACK_BOUNDARY 32 74890075Sobrien 749117395Skan#define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32) 750117395Skan 75190075Sobrien#define FUNCTION_BOUNDARY 32 75290075Sobrien 75390075Sobrien/* The lowest bit is used to indicate Thumb-mode functions, so the 75490075Sobrien vbit must go into the delta field of pointers to member 75590075Sobrien functions. */ 75690075Sobrien#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 75790075Sobrien 75890075Sobrien#define EMPTY_FIELD_BOUNDARY 32 75990075Sobrien 760132718Skan#define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32) 76190075Sobrien 762132718Skan#define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \ 763132718Skan (TARGET_REALLY_IWMMXT \ 764132718Skan && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode))) 765132718Skan 766132718Skan/* XXX Blah -- this macro is used directly by libobjc. Since it 767132718Skan supports no vector modes, cut out the complexity and fall back 768132718Skan on BIGGEST_FIELD_ALIGNMENT. */ 769132718Skan#ifdef IN_TARGET_LIBS 770132718Skan#define BIGGEST_FIELD_ALIGNMENT 64 771132718Skan#else 772132718Skan/* An expression for the alignment of a structure field FIELD if the 773132718Skan alignment computed in the usual way is COMPUTED. GCC uses this 774132718Skan value instead of the value in `BIGGEST_ALIGNMENT' or 775132718Skan `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ 776132718Skan#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 777132718Skan (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \ 778132718Skan ? IWMMXT_ALIGNMENT \ 779132718Skan : (COMPUTED)) 780132718Skan#endif 781132718Skan 782132718Skan/* If defined, a C expression to compute the alignment for a static variable. 783132718Skan TYPE is the data type, and ALIGN is the alignment that the object 784132718Skan would ordinarily have. The value of this macro is used instead of that 785132718Skan alignment to align the object. 786132718Skan 787132718Skan If this macro is not defined, then ALIGN is used. */ 788132718Skan#define DATA_ALIGNMENT(TYPE, ALIGN) \ 789132718Skan (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN) 790132718Skan 791132718Skan/* If defined, a C expression to compute the alignment for a 792132718Skan variables in the local store. TYPE is the data type, and 793132718Skan BASIC-ALIGN is the alignment that the object would ordinarily 794132718Skan have. The value of this macro is used instead of that alignment 795132718Skan to align the object. 796132718Skan 797132718Skan If this macro is not defined, then BASIC-ALIGN is used. */ 798132718Skan#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 799132718Skan (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN) 800132718Skan 80190075Sobrien/* Make strings word-aligned so strcpy from constants will be faster. */ 802132718Skan#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 80390075Sobrien 80490075Sobrien#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 805132718Skan ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \ 806132718Skan (TREE_CODE (EXP) == STRING_CST \ 80790075Sobrien && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 80890075Sobrien ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 80990075Sobrien 81090075Sobrien/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 81190075Sobrien value set in previous versions of this toolchain was 8, which produces more 81290075Sobrien compact structures. The command line option -mstructure_size_boundary=<n> 81390075Sobrien can be used to change this value. For compatibility with the ARM SDK 81490075Sobrien however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 81590075Sobrien 0020D) page 2-20 says "Structures are aligned on word boundaries". */ 81690075Sobrien#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 81790075Sobrienextern int arm_structure_size_boundary; 81890075Sobrien 819117395Skan/* This is the value used to initialize arm_structure_size_boundary. If a 82090075Sobrien particular arm target wants to change the default value it should change 821132718Skan the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 82290075Sobrien for an example of this. */ 82390075Sobrien#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 82490075Sobrien#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 82590075Sobrien#endif 82690075Sobrien 82790075Sobrien/* Used when parsing command line option -mstructure_size_boundary. */ 82890075Sobrienextern const char * structure_size_string; 82990075Sobrien 830117395Skan/* Nonzero if move instructions will actually fail to work 83190075Sobrien when given unaligned data. */ 83290075Sobrien#define STRICT_ALIGNMENT 1 83390075Sobrien 83490075Sobrien/* Standard register usage. */ 83590075Sobrien 83690075Sobrien/* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 83790075Sobrien (S - saved over call). 83890075Sobrien 83990075Sobrien r0 * argument word/integer result 84090075Sobrien r1-r3 argument word 84190075Sobrien 84290075Sobrien r4-r8 S register variable 84390075Sobrien r9 S (rfp) register variable (real frame pointer) 84490075Sobrien 84590075Sobrien r10 F S (sl) stack limit (used by -mapcs-stack-check) 84690075Sobrien r11 F S (fp) argument pointer 84790075Sobrien r12 (ip) temp workspace 84890075Sobrien r13 F S (sp) lower end of current stack frame 84990075Sobrien r14 (lr) link address/workspace 85090075Sobrien r15 F (pc) program counter 85190075Sobrien 85290075Sobrien f0 floating point result 85390075Sobrien f1-f3 floating point scratch 85490075Sobrien 85590075Sobrien f4-f7 S floating point variable 85690075Sobrien 85790075Sobrien cc This is NOT a real register, but is used internally 85890075Sobrien to represent things that use or set the condition 85990075Sobrien codes. 86090075Sobrien sfp This isn't either. It is used during rtl generation 86190075Sobrien since the offset between the frame pointer and the 86290075Sobrien auto's isn't known until after register allocation. 86390075Sobrien afp Nor this, we only need this because of non-local 86490075Sobrien goto. Without it fp appears to be used and the 86590075Sobrien elimination code won't get rid of sfp. It tracks 86690075Sobrien fp exactly at all times. 86790075Sobrien 86890075Sobrien *: See CONDITIONAL_REGISTER_USAGE */ 86990075Sobrien 870132718Skan/* 871132718Skan mvf0 Cirrus floating point result 872132718Skan mvf1-mvf3 Cirrus floating point scratch 873132718Skan mvf4-mvf15 S Cirrus floating point variable. */ 874132718Skan 87590075Sobrien/* The stack backtrace structure is as follows: 87690075Sobrien fp points to here: | save code pointer | [fp] 87790075Sobrien | return link value | [fp, #-4] 87890075Sobrien | return sp value | [fp, #-8] 87990075Sobrien | return fp value | [fp, #-12] 88090075Sobrien [| saved r10 value |] 88190075Sobrien [| saved r9 value |] 88290075Sobrien [| saved r8 value |] 88390075Sobrien [| saved r7 value |] 88490075Sobrien [| saved r6 value |] 88590075Sobrien [| saved r5 value |] 88690075Sobrien [| saved r4 value |] 88790075Sobrien [| saved r3 value |] 88890075Sobrien [| saved r2 value |] 88990075Sobrien [| saved r1 value |] 89090075Sobrien [| saved r0 value |] 89190075Sobrien [| saved f7 value |] three words 89290075Sobrien [| saved f6 value |] three words 89390075Sobrien [| saved f5 value |] three words 89490075Sobrien [| saved f4 value |] three words 89590075Sobrien r0-r3 are not normally saved in a C function. */ 89690075Sobrien 89790075Sobrien/* 1 for registers that have pervasive standard uses 89890075Sobrien and are not available for the register allocator. */ 89990075Sobrien#define FIXED_REGISTERS \ 90090075Sobrien{ \ 90190075Sobrien 0,0,0,0,0,0,0,0, \ 90290075Sobrien 0,0,0,0,0,1,0,1, \ 90390075Sobrien 0,0,0,0,0,0,0,0, \ 904132718Skan 1,1,1, \ 905132718Skan 1,1,1,1,1,1,1,1, \ 906132718Skan 1,1,1,1,1,1,1,1, \ 907132718Skan 1,1,1,1,1,1,1,1, \ 908132718Skan 1,1,1,1,1,1,1,1, \ 909132718Skan 1,1,1,1 \ 91090075Sobrien} 91190075Sobrien 91290075Sobrien/* 1 for registers not available across function calls. 91390075Sobrien These must include the FIXED_REGISTERS and also any 91490075Sobrien registers that can be used without being saved. 91590075Sobrien The latter must include the registers where values are returned 91690075Sobrien and the register where structure-value addresses are passed. 91790075Sobrien Aside from that, you can include as many other registers as you like. 91890075Sobrien The CC is not preserved over function calls on the ARM 6, so it is 919132718Skan easier to assume this for all. SFP is preserved, since FP is. */ 92090075Sobrien#define CALL_USED_REGISTERS \ 92190075Sobrien{ \ 92290075Sobrien 1,1,1,1,0,0,0,0, \ 92390075Sobrien 0,0,0,0,1,1,1,1, \ 92490075Sobrien 1,1,1,1,0,0,0,0, \ 925132718Skan 1,1,1, \ 926132718Skan 1,1,1,1,1,1,1,1, \ 927132718Skan 1,1,1,1,1,1,1,1, \ 928132718Skan 1,1,1,1,1,1,1,1, \ 929132718Skan 1,1,1,1,1,1,1,1, \ 930132718Skan 1,1,1,1 \ 93190075Sobrien} 93290075Sobrien 93390075Sobrien#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 93490075Sobrien#define SUBTARGET_CONDITIONAL_REGISTER_USAGE 93590075Sobrien#endif 93690075Sobrien 93790075Sobrien#define CONDITIONAL_REGISTER_USAGE \ 93890075Sobrien{ \ 93990075Sobrien int regno; \ 94090075Sobrien \ 94190075Sobrien if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ 94290075Sobrien { \ 94390075Sobrien for (regno = FIRST_ARM_FP_REGNUM; \ 94490075Sobrien regno <= LAST_ARM_FP_REGNUM; ++regno) \ 94590075Sobrien fixed_regs[regno] = call_used_regs[regno] = 1; \ 94690075Sobrien } \ 947132718Skan \ 948132718Skan if (TARGET_THUMB && optimize_size) \ 94990075Sobrien { \ 950132718Skan /* When optimizing for size, it's better not to use \ 951132718Skan the HI regs, because of the overhead of stacking \ 952132718Skan them. */ \ 953132718Skan for (regno = FIRST_HI_REGNUM; \ 954132718Skan regno <= LAST_HI_REGNUM; ++regno) \ 955132718Skan fixed_regs[regno] = call_used_regs[regno] = 1; \ 956132718Skan } \ 957132718Skan \ 958132718Skan /* The link register can be clobbered by any branch insn, \ 959132718Skan but we have no way to track that at present, so mark \ 960132718Skan it as unavailable. */ \ 961132718Skan if (TARGET_THUMB) \ 962132718Skan fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ 963132718Skan \ 964132718Skan if (TARGET_CIRRUS) \ 965132718Skan { \ 966132718Skan for (regno = FIRST_ARM_FP_REGNUM; \ 967132718Skan regno <= LAST_ARM_FP_REGNUM; ++ regno) \ 968132718Skan fixed_regs[regno] = call_used_regs[regno] = 1; \ 969132718Skan for (regno = FIRST_CIRRUS_FP_REGNUM; \ 970132718Skan regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ 971132718Skan { \ 972132718Skan fixed_regs[regno] = 0; \ 973132718Skan call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ 974132718Skan } \ 975132718Skan } \ 976132718Skan \ 977132718Skan if (TARGET_REALLY_IWMMXT) \ 978132718Skan { \ 979132718Skan regno = FIRST_IWMMXT_GR_REGNUM; \ 980132718Skan /* The 2002/10/09 revision of the XScale ABI has wCG0 \ 981132718Skan and wCG1 as call-preserved registers. The 2002/11/21 \ 982132718Skan revision changed this so that all wCG registers are \ 983132718Skan scratch registers. */ \ 984132718Skan for (regno = FIRST_IWMMXT_GR_REGNUM; \ 985132718Skan regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ 986132718Skan fixed_regs[regno] = call_used_regs[regno] = 0; \ 987132718Skan /* The XScale ABI has wR0 - wR9 as scratch registers, \ 988132718Skan the rest as call-preserved registers. */ \ 989132718Skan for (regno = FIRST_IWMMXT_REGNUM; \ 990132718Skan regno <= LAST_IWMMXT_REGNUM; ++ regno) \ 991132718Skan { \ 992132718Skan fixed_regs[regno] = 0; \ 993132718Skan call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ 994132718Skan } \ 995132718Skan } \ 996132718Skan \ 997132718Skan if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 998132718Skan { \ 99990075Sobrien fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 100090075Sobrien call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 100190075Sobrien } \ 100290075Sobrien else if (TARGET_APCS_STACK) \ 100390075Sobrien { \ 100490075Sobrien fixed_regs[10] = 1; \ 100590075Sobrien call_used_regs[10] = 1; \ 100690075Sobrien } \ 100790075Sobrien if (TARGET_APCS_FRAME) \ 100890075Sobrien { \ 100990075Sobrien fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 101090075Sobrien call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 101190075Sobrien } \ 101290075Sobrien SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 101390075Sobrien} 101490075Sobrien 1015132718Skan/* These are a couple of extensions to the formats accepted 101690075Sobrien by asm_fprintf: 101790075Sobrien %@ prints out ASM_COMMENT_START 101890075Sobrien %r prints out REGISTER_PREFIX reg_names[arg] */ 101990075Sobrien#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 102090075Sobrien case '@': \ 102190075Sobrien fputs (ASM_COMMENT_START, FILE); \ 102290075Sobrien break; \ 102390075Sobrien \ 102490075Sobrien case 'r': \ 102590075Sobrien fputs (REGISTER_PREFIX, FILE); \ 102690075Sobrien fputs (reg_names [va_arg (ARGS, int)], FILE); \ 102790075Sobrien break; 102890075Sobrien 102990075Sobrien/* Round X up to the nearest word. */ 1030132718Skan#define ROUND_UP_WORD(X) (((X) + 3) & ~3) 103190075Sobrien 103290075Sobrien/* Convert fron bytes to ints. */ 1033117395Skan#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 103490075Sobrien 103590075Sobrien/* The number of (integer) registers required to hold a quantity of type MODE. */ 1036117395Skan#define ARM_NUM_REGS(MODE) \ 1037117395Skan ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 103890075Sobrien 103990075Sobrien/* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 1040117395Skan#define ARM_NUM_REGS2(MODE, TYPE) \ 1041117395Skan ARM_NUM_INTS ((MODE) == BLKmode ? \ 104290075Sobrien int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 104390075Sobrien 104490075Sobrien/* The number of (integer) argument register available. */ 104590075Sobrien#define NUM_ARG_REGS 4 104690075Sobrien 1047132718Skan/* Return the register number of the N'th (integer) argument. */ 104890075Sobrien#define ARG_REGISTER(N) (N - 1) 104990075Sobrien 105090075Sobrien#if 0 /* FIXME: The ARM backend has special code to handle structure 105190075Sobrien returns, and will reserve its own hidden first argument. So 105290075Sobrien if this macro is enabled a *second* hidden argument will be 105390075Sobrien reserved, which will break binary compatibility with old 105490075Sobrien toolchains and also thunk handling. One day this should be 105590075Sobrien fixed. */ 105690075Sobrien/* RTX for structure returns. NULL means use a hidden first argument. */ 105790075Sobrien#define STRUCT_VALUE 0 105890075Sobrien#else 105990075Sobrien/* Register in which address to store a structure value 106090075Sobrien is passed to a function. */ 106190075Sobrien#define STRUCT_VALUE_REGNUM ARG_REGISTER (1) 106290075Sobrien#endif 106390075Sobrien 106490075Sobrien/* Specify the registers used for certain standard purposes. 106590075Sobrien The values of these macros are register numbers. */ 106690075Sobrien 106790075Sobrien/* The number of the last argument register. */ 106890075Sobrien#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 106990075Sobrien 1070132718Skan/* The numbers of the Thumb register ranges. */ 1071132718Skan#define FIRST_LO_REGNUM 0 107290075Sobrien#define LAST_LO_REGNUM 7 1073132718Skan#define FIRST_HI_REGNUM 8 1074132718Skan#define LAST_HI_REGNUM 11 107590075Sobrien 107690075Sobrien/* The register that holds the return address in exception handlers. */ 107790075Sobrien#define EXCEPTION_LR_REGNUM 2 107890075Sobrien 107990075Sobrien/* The native (Norcroft) Pascal compiler for the ARM passes the static chain 108090075Sobrien as an invisible last argument (possible since varargs don't exist in 108190075Sobrien Pascal), so the following is not true. */ 108290075Sobrien#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) 108390075Sobrien 108490075Sobrien/* Define this to be where the real frame pointer is if it is not possible to 108590075Sobrien work out the offset between the frame pointer and the automatic variables 108690075Sobrien until after register allocation has taken place. FRAME_POINTER_REGNUM 108790075Sobrien should point to a special register that we will make sure is eliminated. 108890075Sobrien 108990075Sobrien For the Thumb we have another problem. The TPCS defines the frame pointer 1090132718Skan as r11, and GCC believes that it is always possible to use the frame pointer 109190075Sobrien as base register for addressing purposes. (See comments in 109290075Sobrien find_reloads_address()). But - the Thumb does not allow high registers, 109390075Sobrien including r11, to be used as base address registers. Hence our problem. 109490075Sobrien 109590075Sobrien The solution used here, and in the old thumb port is to use r7 instead of 109690075Sobrien r11 as the hard frame pointer and to have special code to generate 109790075Sobrien backtrace structures on the stack (if required to do so via a command line 1098132718Skan option) using r11. This is the only 'user visible' use of r11 as a frame 109990075Sobrien pointer. */ 110090075Sobrien#define ARM_HARD_FRAME_POINTER_REGNUM 11 110190075Sobrien#define THUMB_HARD_FRAME_POINTER_REGNUM 7 110290075Sobrien 110390075Sobrien#define HARD_FRAME_POINTER_REGNUM \ 110490075Sobrien (TARGET_ARM \ 110590075Sobrien ? ARM_HARD_FRAME_POINTER_REGNUM \ 110690075Sobrien : THUMB_HARD_FRAME_POINTER_REGNUM) 110790075Sobrien 110890075Sobrien#define FP_REGNUM HARD_FRAME_POINTER_REGNUM 110990075Sobrien 111090075Sobrien/* Register to use for pushing function arguments. */ 111190075Sobrien#define STACK_POINTER_REGNUM SP_REGNUM 111290075Sobrien 111390075Sobrien/* ARM floating pointer registers. */ 111490075Sobrien#define FIRST_ARM_FP_REGNUM 16 111590075Sobrien#define LAST_ARM_FP_REGNUM 23 111690075Sobrien 1117132718Skan#define FIRST_IWMMXT_GR_REGNUM 43 1118132718Skan#define LAST_IWMMXT_GR_REGNUM 46 1119132718Skan#define FIRST_IWMMXT_REGNUM 47 1120132718Skan#define LAST_IWMMXT_REGNUM 62 1121132718Skan#define IS_IWMMXT_REGNUM(REGNUM) \ 1122132718Skan (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1123132718Skan#define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1124132718Skan (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1125132718Skan 112690075Sobrien/* Base register for access to local variables of the function. */ 112790075Sobrien#define FRAME_POINTER_REGNUM 25 112890075Sobrien 112990075Sobrien/* Base register for access to arguments of the function. */ 113090075Sobrien#define ARG_POINTER_REGNUM 26 113190075Sobrien 1132132718Skan#define FIRST_CIRRUS_FP_REGNUM 27 1133132718Skan#define LAST_CIRRUS_FP_REGNUM 42 1134132718Skan#define IS_CIRRUS_REGNUM(REGNUM) \ 1135132718Skan (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 113690075Sobrien 1137132718Skan/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 1138132718Skan/* + 16 Cirrus registers take us up to 43. */ 1139132718Skan/* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1140132718Skan#define FIRST_PSEUDO_REGISTER 63 1141132718Skan 114290075Sobrien/* Value should be nonzero if functions must have frame pointers. 114390075Sobrien Zero means the frame pointer need not be set up (and parms may be accessed 114490075Sobrien via the stack pointer) in functions that seem suitable. 114590075Sobrien If we have to have a frame pointer we might as well make use of it. 114690075Sobrien APCS says that the frame pointer does not need to be pushed in leaf 114790075Sobrien functions, or simple tail call functions. */ 114890075Sobrien#define FRAME_POINTER_REQUIRED \ 114990075Sobrien (current_function_has_nonlocal_label \ 115090075Sobrien || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) 115190075Sobrien 115290075Sobrien/* Return number of consecutive hard regs needed starting at reg REGNO 115390075Sobrien to hold something of mode MODE. 115490075Sobrien This is ordinarily the length in words of a value of mode MODE 115590075Sobrien but can be less for certain modes in special long registers. 115690075Sobrien 1157132718Skan On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 115890075Sobrien mode. */ 115990075Sobrien#define HARD_REGNO_NREGS(REGNO, MODE) \ 116090075Sobrien ((TARGET_ARM \ 116190075Sobrien && REGNO >= FIRST_ARM_FP_REGNUM \ 116290075Sobrien && REGNO != FRAME_POINTER_REGNUM \ 116390075Sobrien && REGNO != ARG_POINTER_REGNUM) \ 1164117395Skan ? 1 : ARM_NUM_REGS (MODE)) 116590075Sobrien 116690075Sobrien/* Return true if REGNO is suitable for holding a quantity of type MODE. */ 116790075Sobrien#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 116890075Sobrien arm_hard_regno_mode_ok ((REGNO), (MODE)) 116990075Sobrien 117090075Sobrien/* Value is 1 if it is a good idea to tie two pseudo registers 117190075Sobrien when one has mode MODE1 and one has mode MODE2. 117290075Sobrien If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 117390075Sobrien for any hard reg, then this must be 0 for correct output. */ 117490075Sobrien#define MODES_TIEABLE_P(MODE1, MODE2) \ 117590075Sobrien (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 117690075Sobrien 1177132718Skan#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1178132718Skan ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode) 1179132718Skan 1180132718Skan#define VALID_IWMMXT_REG_MODE(MODE) \ 1181132718Skan (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode) 1182132718Skan 118390075Sobrien/* The order in which register should be allocated. It is good to use ip 118490075Sobrien since no saving is required (though calls clobber it) and it never contains 118590075Sobrien function parameters. It is quite good to use lr since other calls may 118690075Sobrien clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 118790075Sobrien least likely to contain a function parameter; in addition results are 118890075Sobrien returned in r0. */ 118990075Sobrien#define REG_ALLOC_ORDER \ 119090075Sobrien{ \ 119190075Sobrien 3, 2, 1, 0, 12, 14, 4, 5, \ 119290075Sobrien 6, 7, 8, 10, 9, 11, 13, 15, \ 119390075Sobrien 16, 17, 18, 19, 20, 21, 22, 23, \ 1194132718Skan 27, 28, 29, 30, 31, 32, 33, 34, \ 1195132718Skan 35, 36, 37, 38, 39, 40, 41, 42, \ 1196132718Skan 43, 44, 45, 46, 47, 48, 49, 50, \ 1197132718Skan 51, 52, 53, 54, 55, 56, 57, 58, \ 1198132718Skan 59, 60, 61, 62, \ 119990075Sobrien 24, 25, 26 \ 120090075Sobrien} 120196263Sobrien 120296263Sobrien/* Interrupt functions can only use registers that have already been 120396263Sobrien saved by the prologue, even if they would normally be 120496263Sobrien call-clobbered. */ 120596263Sobrien#define HARD_REGNO_RENAME_OK(SRC, DST) \ 120696263Sobrien (! IS_INTERRUPT (cfun->machine->func_type) || \ 120796263Sobrien regs_ever_live[DST]) 120890075Sobrien 120990075Sobrien/* Register and constant classes. */ 121090075Sobrien 1211132718Skan/* Register classes: used to be simple, just all ARM regs or all FPA regs 121290075Sobrien Now that the Thumb is involved it has become more complicated. */ 121390075Sobrienenum reg_class 121490075Sobrien{ 121590075Sobrien NO_REGS, 1216132718Skan FPA_REGS, 1217132718Skan CIRRUS_REGS, 1218132718Skan IWMMXT_GR_REGS, 1219132718Skan IWMMXT_REGS, 122090075Sobrien LO_REGS, 122190075Sobrien STACK_REG, 122290075Sobrien BASE_REGS, 122390075Sobrien HI_REGS, 122490075Sobrien CC_REG, 122590075Sobrien GENERAL_REGS, 122690075Sobrien ALL_REGS, 122790075Sobrien LIM_REG_CLASSES 122890075Sobrien}; 122990075Sobrien 123090075Sobrien#define N_REG_CLASSES (int) LIM_REG_CLASSES 123190075Sobrien 1232132718Skan/* Give names of register classes as strings for dump file. */ 123390075Sobrien#define REG_CLASS_NAMES \ 123490075Sobrien{ \ 123590075Sobrien "NO_REGS", \ 1236132718Skan "FPA_REGS", \ 1237132718Skan "CIRRUS_REGS", \ 1238132718Skan "IWMMXT_GR_REGS", \ 1239132718Skan "IWMMXT_REGS", \ 124090075Sobrien "LO_REGS", \ 124190075Sobrien "STACK_REG", \ 124290075Sobrien "BASE_REGS", \ 124390075Sobrien "HI_REGS", \ 124490075Sobrien "CC_REG", \ 124590075Sobrien "GENERAL_REGS", \ 124690075Sobrien "ALL_REGS", \ 124790075Sobrien} 124890075Sobrien 124990075Sobrien/* Define which registers fit in which classes. 125090075Sobrien This is an initializer for a vector of HARD_REG_SET 125190075Sobrien of length N_REG_CLASSES. */ 125290075Sobrien#define REG_CLASS_CONTENTS \ 125390075Sobrien{ \ 1254132718Skan { 0x00000000, 0x0 }, /* NO_REGS */ \ 1255132718Skan { 0x00FF0000, 0x0 }, /* FPA_REGS */ \ 1256132718Skan { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \ 1257132718Skan { 0x00000000, 0x00007800 }, /* IWMMXT_GR_REGS */\ 1258132718Skan { 0x00000000, 0x7FFF8000 }, /* IWMMXT_REGS */ \ 1259132718Skan { 0x000000FF, 0x0 }, /* LO_REGS */ \ 1260132718Skan { 0x00002000, 0x0 }, /* STACK_REG */ \ 1261132718Skan { 0x000020FF, 0x0 }, /* BASE_REGS */ \ 1262132718Skan { 0x0000FF00, 0x0 }, /* HI_REGS */ \ 1263132718Skan { 0x01000000, 0x0 }, /* CC_REG */ \ 1264132718Skan { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\ 1265132718Skan { 0xFAFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 126690075Sobrien} 126790075Sobrien 126890075Sobrien/* The same information, inverted: 126990075Sobrien Return the class number of the smallest class containing 127090075Sobrien reg number REGNO. This could be a conditional expression 127190075Sobrien or could index an array. */ 127290075Sobrien#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 127390075Sobrien 1274132718Skan/* FPA registers can't do dubreg as all values are reformatted to internal 1275132718Skan precision. */ 1276132718Skan#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1277132718Skan (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1278132718Skan ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0) 1279132718Skan 128090075Sobrien/* The class value for index registers, and the one for base regs. */ 128190075Sobrien#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) 1282104752Skan#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) 128390075Sobrien 1284104752Skan/* For the Thumb the high registers cannot be used as base registers 1285132718Skan when addressing quantities in QI or HI mode; if we don't know the 1286104752Skan mode, then we must be conservative. After reload we must also be 1287104752Skan conservative, since we can't support SP+reg addressing, and we 1288104752Skan can't fix up any bad substitutions. */ 128990075Sobrien#define MODE_BASE_REG_CLASS(MODE) \ 1290104752Skan (TARGET_ARM ? GENERAL_REGS : \ 1291104752Skan (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS)) 129290075Sobrien 129390075Sobrien/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 129490075Sobrien registers explicitly used in the rtl to be used as spill registers 129590075Sobrien but prevents the compiler from extending the lifetime of these 1296132718Skan registers. */ 129790075Sobrien#define SMALL_REGISTER_CLASSES TARGET_THUMB 129890075Sobrien 129990075Sobrien/* Get reg_class from a letter such as appears in the machine description. 1300132718Skan We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the 130190075Sobrien ARM, but several more letters for the Thumb. */ 130290075Sobrien#define REG_CLASS_FROM_LETTER(C) \ 1303132718Skan ( (C) == 'f' ? FPA_REGS \ 1304132718Skan : (C) == 'v' ? CIRRUS_REGS \ 1305132718Skan : (C) == 'y' ? IWMMXT_REGS \ 1306132718Skan : (C) == 'z' ? IWMMXT_GR_REGS \ 130790075Sobrien : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ 130890075Sobrien : TARGET_ARM ? NO_REGS \ 130990075Sobrien : (C) == 'h' ? HI_REGS \ 131090075Sobrien : (C) == 'b' ? BASE_REGS \ 131190075Sobrien : (C) == 'k' ? STACK_REG \ 131290075Sobrien : (C) == 'c' ? CC_REG \ 131390075Sobrien : NO_REGS) 131490075Sobrien 131590075Sobrien/* The letters I, J, K, L and M in a register constraint string 131690075Sobrien can be used to stand for particular ranges of immediate operands. 131790075Sobrien This macro defines what the ranges are. 131890075Sobrien C is the letter, and VALUE is a constant value. 131990075Sobrien Return 1 if VALUE is in the range specified by C. 132090075Sobrien I: immediate arithmetic operand (i.e. 8 bits shifted as required). 132190075Sobrien J: valid indexing constants. 132290075Sobrien K: ~value ok in rhs argument of data operand. 132390075Sobrien L: -value ok in rhs argument of data operand. 132490075Sobrien M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ 132590075Sobrien#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ 132690075Sobrien ((C) == 'I' ? const_ok_for_arm (VALUE) : \ 132790075Sobrien (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ 132890075Sobrien (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ 132990075Sobrien (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ 133090075Sobrien (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ 133190075Sobrien || (((VALUE) & ((VALUE) - 1)) == 0)) \ 133290075Sobrien : 0) 133390075Sobrien 133490075Sobrien#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ 133590075Sobrien ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ 133690075Sobrien (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ 133790075Sobrien (C) == 'K' ? thumb_shiftable_const (VAL) : \ 133890075Sobrien (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ 133990075Sobrien (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ 134090075Sobrien && ((VAL) & 3) == 0) : \ 134190075Sobrien (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ 134290075Sobrien (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ 134390075Sobrien : 0) 134490075Sobrien 134590075Sobrien#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 134690075Sobrien (TARGET_ARM ? \ 134790075Sobrien CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) 134890075Sobrien 1349132718Skan/* Constant letter 'G' for the FPA immediate constants. 135090075Sobrien 'H' means the same constant negated. */ 135190075Sobrien#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ 1352132718Skan ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \ 1353132718Skan (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0) 135490075Sobrien 135590075Sobrien#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ 135690075Sobrien (TARGET_ARM ? \ 135790075Sobrien CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) 135890075Sobrien 135990075Sobrien/* For the ARM, `Q' means that this is a memory operand that is just 136090075Sobrien an offset from a register. 136190075Sobrien `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL 136290075Sobrien address. This means that the symbol is in the text segment and can be 1363132718Skan accessed without using a load. */ 136490075Sobrien 136590075Sobrien#define EXTRA_CONSTRAINT_ARM(OP, C) \ 136690075Sobrien ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ 136790075Sobrien (C) == 'R' ? (GET_CODE (OP) == MEM \ 136890075Sobrien && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 136990075Sobrien && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ 1370132718Skan (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \ 1371132718Skan (C) == 'T' ? cirrus_memory_offset (OP) : \ 1372132718Skan 0) 137390075Sobrien 137490075Sobrien#define EXTRA_CONSTRAINT_THUMB(X, C) \ 137590075Sobrien ((C) == 'Q' ? (GET_CODE (X) == MEM \ 137690075Sobrien && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) 137790075Sobrien 137890075Sobrien#define EXTRA_CONSTRAINT(X, C) \ 137990075Sobrien (TARGET_ARM ? \ 138090075Sobrien EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) 138190075Sobrien 138290075Sobrien/* Given an rtx X being reloaded into a reg required to be 138390075Sobrien in class CLASS, return the class of reg to actually use. 138490075Sobrien In general this is just CLASS, but for the Thumb we prefer 138590075Sobrien a LO_REGS class or a subset. */ 138690075Sobrien#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 138790075Sobrien (TARGET_ARM ? (CLASS) : \ 138890075Sobrien ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) 138990075Sobrien 139090075Sobrien/* Must leave BASE_REGS reloads alone */ 139190075Sobrien#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 139290075Sobrien ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 139390075Sobrien ? ((true_regnum (X) == -1 ? LO_REGS \ 139490075Sobrien : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 139590075Sobrien : NO_REGS)) \ 139690075Sobrien : NO_REGS) 139790075Sobrien 139890075Sobrien#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 139990075Sobrien ((CLASS) != LO_REGS \ 140090075Sobrien ? ((true_regnum (X) == -1 ? LO_REGS \ 140190075Sobrien : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 140290075Sobrien : NO_REGS)) \ 140390075Sobrien : NO_REGS) 140490075Sobrien 140590075Sobrien/* Return the register class of a scratch register needed to copy IN into 140690075Sobrien or out of a register in CLASS in MODE. If it can be done directly, 140790075Sobrien NO_REGS is returned. */ 140890075Sobrien#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 140990075Sobrien (TARGET_ARM ? \ 141090075Sobrien (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 141190075Sobrien ? GENERAL_REGS : NO_REGS) \ 141290075Sobrien : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 141390075Sobrien 1414132718Skan/* If we need to load shorts byte-at-a-time, then we need a scratch. */ 141590075Sobrien#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1416132718Skan /* Cannot load constants into Cirrus registers. */ \ 1417132718Skan ((TARGET_CIRRUS \ 1418132718Skan && (CLASS) == CIRRUS_REGS \ 1419132718Skan && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1420132718Skan ? GENERAL_REGS : \ 142190075Sobrien (TARGET_ARM ? \ 1422132718Skan (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1423132718Skan && CONSTANT_P (X)) \ 1424132718Skan ? GENERAL_REGS : \ 142590075Sobrien (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ 142690075Sobrien && (GET_CODE (X) == MEM \ 142790075Sobrien || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 142890075Sobrien && true_regnum (X) == -1))) \ 142990075Sobrien ? GENERAL_REGS : NO_REGS) \ 1430132718Skan : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 143190075Sobrien 143290075Sobrien/* Try a machine-dependent way of reloading an illegitimate address 143390075Sobrien operand. If we find one, push the reload and jump to WIN. This 143490075Sobrien macro is used in only one place: `find_reloads_address' in reload.c. 143590075Sobrien 143690075Sobrien For the ARM, we wish to handle large displacements off a base 143790075Sobrien register by splitting the addend across a MOV and the mem insn. 143890075Sobrien This can cut the number of reloads needed. */ 143990075Sobrien#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 144090075Sobrien do \ 144190075Sobrien { \ 144290075Sobrien if (GET_CODE (X) == PLUS \ 144390075Sobrien && GET_CODE (XEXP (X, 0)) == REG \ 144490075Sobrien && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 144590075Sobrien && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 144690075Sobrien && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 144790075Sobrien { \ 144890075Sobrien HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 144990075Sobrien HOST_WIDE_INT low, high; \ 145090075Sobrien \ 145190075Sobrien if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ 145290075Sobrien low = ((val & 0xf) ^ 0x8) - 0x8; \ 1453132718Skan else if (TARGET_CIRRUS) \ 1454132718Skan /* Need to be careful, -256 is not a valid offset. */ \ 1455132718Skan low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 145690075Sobrien else if (MODE == SImode \ 145790075Sobrien || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 145890075Sobrien || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 145990075Sobrien /* Need to be careful, -4096 is not a valid offset. */ \ 146090075Sobrien low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 146190075Sobrien else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 146290075Sobrien /* Need to be careful, -256 is not a valid offset. */ \ 146390075Sobrien low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 146490075Sobrien else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 146590075Sobrien && TARGET_HARD_FLOAT) \ 146690075Sobrien /* Need to be careful, -1024 is not a valid offset. */ \ 146790075Sobrien low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 146890075Sobrien else \ 146990075Sobrien break; \ 147090075Sobrien \ 147190075Sobrien high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 147290075Sobrien ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 147390075Sobrien - (unsigned HOST_WIDE_INT) 0x80000000); \ 147490075Sobrien /* Check for overflow or zero */ \ 147590075Sobrien if (low == 0 || high == 0 || (high + low != val)) \ 147690075Sobrien break; \ 147790075Sobrien \ 147890075Sobrien /* Reload the high part into a base reg; leave the low part \ 147990075Sobrien in the mem. */ \ 148090075Sobrien X = gen_rtx_PLUS (GET_MODE (X), \ 148190075Sobrien gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 148290075Sobrien GEN_INT (high)), \ 148390075Sobrien GEN_INT (low)); \ 148490075Sobrien push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 148590075Sobrien MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 148690075Sobrien VOIDmode, 0, 0, OPNUM, TYPE); \ 148790075Sobrien goto WIN; \ 148890075Sobrien } \ 148990075Sobrien } \ 149090075Sobrien while (0) 149190075Sobrien 1492132718Skan/* XXX If an HImode FP+large_offset address is converted to an HImode 149390075Sobrien SP+large_offset address, then reload won't know how to fix it. It sees 149490075Sobrien only that SP isn't valid for HImode, and so reloads the SP into an index 149590075Sobrien register, but the resulting address is still invalid because the offset 149690075Sobrien is too big. We fix it here instead by reloading the entire address. */ 149790075Sobrien/* We could probably achieve better results by defining PROMOTE_MODE to help 149890075Sobrien cope with the variances between the Thumb's signed and unsigned byte and 149990075Sobrien halfword load instructions. */ 150090075Sobrien#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 150190075Sobrien{ \ 150290075Sobrien if (GET_CODE (X) == PLUS \ 150390075Sobrien && GET_MODE_SIZE (MODE) < 4 \ 150490075Sobrien && GET_CODE (XEXP (X, 0)) == REG \ 150590075Sobrien && XEXP (X, 0) == stack_pointer_rtx \ 150690075Sobrien && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1507132718Skan && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \ 150890075Sobrien { \ 150990075Sobrien rtx orig_X = X; \ 151090075Sobrien X = copy_rtx (X); \ 151190075Sobrien push_reload (orig_X, NULL_RTX, &X, NULL, \ 151290075Sobrien MODE_BASE_REG_CLASS (MODE), \ 151390075Sobrien Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ 151490075Sobrien goto WIN; \ 151590075Sobrien } \ 151690075Sobrien} 151790075Sobrien 151890075Sobrien#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 151990075Sobrien if (TARGET_ARM) \ 152090075Sobrien ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 152190075Sobrien else \ 152290075Sobrien THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 152390075Sobrien 152490075Sobrien/* Return the maximum number of consecutive registers 152590075Sobrien needed to represent mode MODE in a register of class CLASS. 1526132718Skan ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 152790075Sobrien#define CLASS_MAX_NREGS(CLASS, MODE) \ 1528132718Skan (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 152990075Sobrien 1530132718Skan/* If defined, gives a class of registers that cannot be used as the 1531132718Skan operand of a SUBREG that changes the mode of the object illegally. */ 1532132718Skan 1533132718Skan/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */ 153490075Sobrien#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 153590075Sobrien (TARGET_ARM ? \ 1536132718Skan ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1537132718Skan (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1538132718Skan (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1539132718Skan (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1540132718Skan (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1541132718Skan (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1542132718Skan (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1543132718Skan 2) \ 154490075Sobrien : \ 154590075Sobrien ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 154690075Sobrien 154790075Sobrien/* Stack layout; function entry, exit and calling. */ 154890075Sobrien 154990075Sobrien/* Define this if pushing a word on the stack 155090075Sobrien makes the stack pointer a smaller address. */ 155190075Sobrien#define STACK_GROWS_DOWNWARD 1 155290075Sobrien 155390075Sobrien/* Define this if the nominal address of the stack frame 155490075Sobrien is at the high-address end of the local variables; 155590075Sobrien that is, each additional local variable allocated 155690075Sobrien goes at a more negative offset in the frame. */ 155790075Sobrien#define FRAME_GROWS_DOWNWARD 1 155890075Sobrien 155990075Sobrien/* Offset within stack frame to start allocating local variables at. 156090075Sobrien If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 156190075Sobrien first local allocated. Otherwise, it is the offset to the BEGINNING 156290075Sobrien of the first local allocated. */ 156390075Sobrien#define STARTING_FRAME_OFFSET 0 156490075Sobrien 156590075Sobrien/* If we generate an insn to push BYTES bytes, 156690075Sobrien this says how many the stack pointer really advances by. */ 156790075Sobrien/* The push insns do not do this rounding implicitly. 1568132718Skan So don't define this. */ 1569132718Skan/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 157090075Sobrien 157190075Sobrien/* Define this if the maximum size of all the outgoing args is to be 157290075Sobrien accumulated and pushed during the prologue. The amount can be 157390075Sobrien found in the variable current_function_outgoing_args_size. */ 157490075Sobrien#define ACCUMULATE_OUTGOING_ARGS 1 157590075Sobrien 157690075Sobrien/* Offset of first parameter from the argument pointer register value. */ 157790075Sobrien#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 157890075Sobrien 157990075Sobrien/* Value is the number of byte of arguments automatically 158090075Sobrien popped when returning from a subroutine call. 158190075Sobrien FUNDECL is the declaration node of the function (as a tree), 158290075Sobrien FUNTYPE is the data type of the function (as a tree), 158390075Sobrien or for a library call it is an identifier node for the subroutine name. 158490075Sobrien SIZE is the number of bytes of arguments passed on the stack. 158590075Sobrien 158690075Sobrien On the ARM, the caller does not pop any of its arguments that were passed 158790075Sobrien on the stack. */ 158890075Sobrien#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 158990075Sobrien 159090075Sobrien/* Define how to find the value returned by a library function 159190075Sobrien assuming the value has mode MODE. */ 159290075Sobrien#define LIBCALL_VALUE(MODE) \ 159390075Sobrien (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 159490075Sobrien ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ 1595132718Skan : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1596132718Skan ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1597132718Skan : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \ 1598132718Skan ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 159990075Sobrien : gen_rtx_REG (MODE, ARG_REGISTER (1))) 160090075Sobrien 160190075Sobrien/* Define how to find the value returned by a function. 160290075Sobrien VALTYPE is the data type of the value (as a tree). 160390075Sobrien If the precise function being called is known, FUNC is its FUNCTION_DECL; 160490075Sobrien otherwise, FUNC is 0. */ 160590075Sobrien#define FUNCTION_VALUE(VALTYPE, FUNC) \ 160690075Sobrien LIBCALL_VALUE (TYPE_MODE (VALTYPE)) 160790075Sobrien 160890075Sobrien/* 1 if N is a possible register number for a function value. 160990075Sobrien On the ARM, only r0 and f0 can return results. */ 1610132718Skan/* On a Cirrus chip, mvf0 can return results. */ 161190075Sobrien#define FUNCTION_VALUE_REGNO_P(REGNO) \ 161290075Sobrien ((REGNO) == ARG_REGISTER (1) \ 1613132718Skan || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \ 1614132718Skan || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \ 161590075Sobrien || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) 161690075Sobrien 161790075Sobrien/* How large values are returned */ 161890075Sobrien/* A C expression which can inhibit the returning of certain function values 1619132718Skan in registers, based on the type of value. */ 162090075Sobrien#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) 162190075Sobrien 162290075Sobrien/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 162390075Sobrien values must be in memory. On the ARM, they need only do so if larger 1624132718Skan than a word, or if they contain elements offset from zero in the struct. */ 162590075Sobrien#define DEFAULT_PCC_STRUCT_RETURN 0 162690075Sobrien 162790075Sobrien/* Flags for the call/call_value rtl operations set up by function_arg. */ 162890075Sobrien#define CALL_NORMAL 0x00000000 /* No special processing. */ 162990075Sobrien#define CALL_LONG 0x00000001 /* Always call indirect. */ 163090075Sobrien#define CALL_SHORT 0x00000002 /* Never call indirect. */ 163190075Sobrien 163290075Sobrien/* These bits describe the different types of function supported 163390075Sobrien by the ARM backend. They are exclusive. ie a function cannot be both a 163490075Sobrien normal function and an interworked function, for example. Knowing the 163590075Sobrien type of a function is important for determining its prologue and 163690075Sobrien epilogue sequences. 163790075Sobrien Note value 7 is currently unassigned. Also note that the interrupt 163890075Sobrien function types all have bit 2 set, so that they can be tested for easily. 163990075Sobrien Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1640117395Skan machine_function structure is initialized (to zero) func_type will 164190075Sobrien default to unknown. This will force the first use of arm_current_func_type 164290075Sobrien to call arm_compute_func_type. */ 164390075Sobrien#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 164490075Sobrien#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 164590075Sobrien#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 164690075Sobrien#define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ 164790075Sobrien#define ARM_FT_ISR 4 /* An interrupt service routine. */ 164890075Sobrien#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 164990075Sobrien#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 165090075Sobrien 165190075Sobrien#define ARM_FT_TYPE_MASK ((1 << 3) - 1) 165290075Sobrien 165390075Sobrien/* In addition functions can have several type modifiers, 165490075Sobrien outlined by these bit masks: */ 165590075Sobrien#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 165690075Sobrien#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 165790075Sobrien#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1658132718Skan#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 165990075Sobrien 166090075Sobrien/* Some macros to test these flags. */ 166190075Sobrien#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 166290075Sobrien#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 166390075Sobrien#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 166490075Sobrien#define IS_NAKED(t) (t & ARM_FT_NAKED) 166590075Sobrien#define IS_NESTED(t) (t & ARM_FT_NESTED) 166690075Sobrien 166790075Sobrien/* A C structure for machine-specific, per-function data. 166890075Sobrien This is added to the cfun structure. */ 1669117395Skantypedef struct machine_function GTY(()) 167090075Sobrien{ 1671132718Skan /* Additional stack adjustment in __builtin_eh_throw. */ 1672117395Skan rtx eh_epilogue_sp_ofs; 167390075Sobrien /* Records if LR has to be saved for far jumps. */ 167490075Sobrien int far_jump_used; 167590075Sobrien /* Records if ARG_POINTER was ever live. */ 167690075Sobrien int arg_pointer_live; 167790075Sobrien /* Records if the save of LR has been eliminated. */ 167890075Sobrien int lr_save_eliminated; 1679117395Skan /* The size of the stack frame. Only valid after reload. */ 1680117395Skan int frame_size; 168190075Sobrien /* Records the type of the current function. */ 168290075Sobrien unsigned long func_type; 168396263Sobrien /* Record if the function has a variable argument list. */ 168496263Sobrien int uses_anonymous_args; 1685132718Skan /* Records if sibcalls are blocked because an argument 1686132718Skan register is needed to preserve stack alignment. */ 1687132718Skan int sibcall_blocked; 168890075Sobrien} 168990075Sobrienmachine_function; 169090075Sobrien 169190075Sobrien/* A C type for declaring a variable that is used as the first argument of 169290075Sobrien `FUNCTION_ARG' and other related values. For some target machines, the 169390075Sobrien type `int' suffices and can hold the number of bytes of argument so far. */ 169490075Sobrientypedef struct 169590075Sobrien{ 169690075Sobrien /* This is the number of registers of arguments scanned so far. */ 169790075Sobrien int nregs; 1698132718Skan /* This is the number of iWMMXt register arguments scanned so far. */ 1699132718Skan int iwmmxt_nregs; 1700132718Skan int named_count; 1701132718Skan int nargs; 1702132718Skan /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */ 170390075Sobrien int call_cookie; 170490075Sobrien} CUMULATIVE_ARGS; 170590075Sobrien 170690075Sobrien/* Define where to put the arguments to a function. 170790075Sobrien Value is zero to push the argument on the stack, 170890075Sobrien or a hard register in which to store the argument. 170990075Sobrien 171090075Sobrien MODE is the argument's machine mode. 171190075Sobrien TYPE is the data type of the argument (as a tree). 171290075Sobrien This is null for libcalls where that information may 171390075Sobrien not be available. 171490075Sobrien CUM is a variable of type CUMULATIVE_ARGS which gives info about 171590075Sobrien the preceding args and about the function being called. 171690075Sobrien NAMED is nonzero if this argument is a named parameter 171790075Sobrien (otherwise it is an extra parameter matching an ellipsis). 171890075Sobrien 171990075Sobrien On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 172090075Sobrien other arguments are passed on the stack. If (NAMED == 0) (which happens 172190075Sobrien only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is 172290075Sobrien passed in the stack (function_prologue will indeed make it pass in the 172390075Sobrien stack if necessary). */ 172490075Sobrien#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 172590075Sobrien arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 172690075Sobrien 172790075Sobrien/* For an arg passed partly in registers and partly in memory, 172890075Sobrien this is the number of registers used. 172990075Sobrien For args passed entirely in registers or entirely in memory, zero. */ 173090075Sobrien#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1731132718Skan (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \ 1732132718Skan NUM_ARG_REGS > (CUM).nregs \ 1733117395Skan && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \ 173490075Sobrien ? NUM_ARG_REGS - (CUM).nregs : 0) 173590075Sobrien 1736117395Skan/* A C expression that indicates when an argument must be passed by 1737117395Skan reference. If nonzero for an argument, a copy of that argument is 1738117395Skan made in memory and a pointer to the argument is passed instead of 1739117395Skan the argument itself. The pointer is passed in whatever way is 1740117395Skan appropriate for passing a pointer to that type. */ 1741117395Skan#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1742117395Skan arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) 1743117395Skan 174490075Sobrien/* Initialize a variable CUM of type CUMULATIVE_ARGS 174590075Sobrien for a call to a function whose data type is FNTYPE. 174690075Sobrien For a library call, FNTYPE is 0. 174790075Sobrien On the ARM, the offset starts at 0. */ 1748132718Skan#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1749132718Skan arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 175090075Sobrien 175190075Sobrien/* Update the data in CUM to advance over an argument 175290075Sobrien of mode MODE and data type TYPE. 175390075Sobrien (TYPE is null for libcalls where that information may not be available.) */ 175490075Sobrien#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1755132718Skan (CUM).nargs += 1; \ 1756132718Skan if (VECTOR_MODE_SUPPORTED_P (MODE)) \ 1757132718Skan if ((CUM).named_count <= (CUM).nargs) \ 1758132718Skan (CUM).nregs += 2; \ 1759132718Skan else \ 1760132718Skan (CUM).iwmmxt_nregs += 1; \ 1761132718Skan else \ 1762117395Skan (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) 176390075Sobrien 1764132718Skan/* If defined, a C expression that gives the alignment boundary, in bits, of an 1765132718Skan argument with the specified mode and type. If it is not defined, 1766132718Skan `PARM_BOUNDARY' is used for all arguments. */ 1767132718Skan#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ 1768132718Skan (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \ 1769132718Skan ? IWMMXT_ALIGNMENT : PARM_BOUNDARY) 1770132718Skan 177190075Sobrien/* 1 if N is a possible register number for function argument passing. 177290075Sobrien On the ARM, r0-r3 are used to pass args. */ 1773132718Skan#define FUNCTION_ARG_REGNO_P(REGNO) \ 1774132718Skan (IN_RANGE ((REGNO), 0, 3) \ 1775132718Skan || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 177690075Sobrien 1777117395Skan/* Implement `va_arg'. */ 1778117395Skan#define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1779117395Skan arm_va_arg (valist, type) 1780117395Skan 178190075Sobrien 178290075Sobrien/* Perform any actions needed for a function that is receiving a variable 178390075Sobrien number of arguments. CUM is as above. MODE and TYPE are the mode and type 178490075Sobrien of the current parameter. PRETEND_SIZE is a variable that should be set to 178590075Sobrien the amount of stack that must be pushed by the prolog to pretend that our 178690075Sobrien caller pushed it. 178790075Sobrien 178890075Sobrien Normally, this macro will push all remaining incoming registers on the 178990075Sobrien stack and set PRETEND_SIZE to the length of the registers pushed. 179090075Sobrien 179190075Sobrien On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 179290075Sobrien named arg and all anonymous args onto the stack. 179390075Sobrien XXX I know the prologue shouldn't be pushing registers, but it is faster 179490075Sobrien that way. */ 179590075Sobrien#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 179690075Sobrien{ \ 179796263Sobrien cfun->machine->uses_anonymous_args = 1; \ 179890075Sobrien if ((CUM).nregs < NUM_ARG_REGS) \ 179990075Sobrien (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ 180090075Sobrien} 180190075Sobrien 180290075Sobrien/* If your target environment doesn't prefix user functions with an 180390075Sobrien underscore, you may wish to re-define this to prevent any conflicts. 180490075Sobrien e.g. AOF may prefix mcount with an underscore. */ 180590075Sobrien#ifndef ARM_MCOUNT_NAME 180690075Sobrien#define ARM_MCOUNT_NAME "*mcount" 180790075Sobrien#endif 180890075Sobrien 180990075Sobrien/* Call the function profiler with a given profile label. The Acorn 181090075Sobrien compiler puts this BEFORE the prolog but gcc puts it afterwards. 181190075Sobrien On the ARM the full profile code will look like: 181290075Sobrien .data 181390075Sobrien LP1 181490075Sobrien .word 0 181590075Sobrien .text 181690075Sobrien mov ip, lr 181790075Sobrien bl mcount 181890075Sobrien .word LP1 181990075Sobrien 182090075Sobrien profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 182190075Sobrien will output the .text section. 182290075Sobrien 182390075Sobrien The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1824117395Skan ``prof'' doesn't seem to mind about this! 1825117395Skan 1826117395Skan Note - this version of the code is designed to work in both ARM and 1827117395Skan Thumb modes. */ 182890075Sobrien#ifndef ARM_FUNCTION_PROFILER 182990075Sobrien#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 183090075Sobrien{ \ 183190075Sobrien char temp[20]; \ 183290075Sobrien rtx sym; \ 183390075Sobrien \ 183490075Sobrien asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 183590075Sobrien IP_REGNUM, LR_REGNUM); \ 183690075Sobrien assemble_name (STREAM, ARM_MCOUNT_NAME); \ 183790075Sobrien fputc ('\n', STREAM); \ 183890075Sobrien ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 183990075Sobrien sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ 184090075Sobrien assemble_aligned_integer (UNITS_PER_WORD, sym); \ 184190075Sobrien} 184290075Sobrien#endif 184390075Sobrien 1844117395Skan#ifdef THUMB_FUNCTION_PROFILER 184590075Sobrien#define FUNCTION_PROFILER(STREAM, LABELNO) \ 184690075Sobrien if (TARGET_ARM) \ 184790075Sobrien ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 184890075Sobrien else \ 184990075Sobrien THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1850117395Skan#else 1851117395Skan#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1852117395Skan ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1853117395Skan#endif 185490075Sobrien 185590075Sobrien/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 185690075Sobrien the stack pointer does not matter. The value is tested only in 185790075Sobrien functions that have frame pointers. 185890075Sobrien No definition is equivalent to always zero. 185990075Sobrien 186090075Sobrien On the ARM, the function epilogue recovers the stack pointer from the 186190075Sobrien frame. */ 186290075Sobrien#define EXIT_IGNORE_STACK 1 186390075Sobrien 186490075Sobrien#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) 186590075Sobrien 186690075Sobrien/* Determine if the epilogue should be output as RTL. 186790075Sobrien You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 186890075Sobrien#define USE_RETURN_INSN(ISCOND) \ 1869132718Skan (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) 187090075Sobrien 187190075Sobrien/* Definitions for register eliminations. 187290075Sobrien 187390075Sobrien This is an array of structures. Each structure initializes one pair 187490075Sobrien of eliminable registers. The "from" register number is given first, 187590075Sobrien followed by "to". Eliminations of the same "from" register are listed 187690075Sobrien in order of preference. 187790075Sobrien 187890075Sobrien We have two registers that can be eliminated on the ARM. First, the 187990075Sobrien arg pointer register can often be eliminated in favor of the stack 188090075Sobrien pointer register. Secondly, the pseudo frame pointer register can always 188190075Sobrien be eliminated; it is replaced with either the stack or the real frame 188290075Sobrien pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 188390075Sobrien because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 188490075Sobrien 188590075Sobrien#define ELIMINABLE_REGS \ 188690075Sobrien{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 188790075Sobrien { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 188890075Sobrien { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 188990075Sobrien { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 189090075Sobrien { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 189190075Sobrien { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 189290075Sobrien { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 189390075Sobrien 189490075Sobrien/* Given FROM and TO register numbers, say whether this elimination is 189590075Sobrien allowed. Frame pointer elimination is automatically handled. 189690075Sobrien 189790075Sobrien All eliminations are permissible. Note that ARG_POINTER_REGNUM and 189890075Sobrien HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame 189990075Sobrien pointer, we must eliminate FRAME_POINTER_REGNUM into 190090075Sobrien HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or 190190075Sobrien ARG_POINTER_REGNUM. */ 190290075Sobrien#define CAN_ELIMINATE(FROM, TO) \ 190390075Sobrien (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ 190490075Sobrien ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ 190590075Sobrien ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ 190690075Sobrien ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ 190790075Sobrien 1) 1908117395Skan 1909117395Skan#define THUMB_REG_PUSHED_P(reg) \ 1910117395Skan (regs_ever_live [reg] \ 1911117395Skan && (! call_used_regs [reg] \ 1912117395Skan || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \ 1913117395Skan && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register))) 1914117395Skan 191590075Sobrien/* Define the offset between two registers, one to be eliminated, and the 191690075Sobrien other its replacement, at the start of a routine. */ 191790075Sobrien#define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 191890075Sobrien do \ 191990075Sobrien { \ 192090075Sobrien (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 192190075Sobrien } \ 192290075Sobrien while (0) 192390075Sobrien 192490075Sobrien/* Note: This macro must match the code in thumb_function_prologue(). */ 192590075Sobrien#define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 192690075Sobrien{ \ 192790075Sobrien (OFFSET) = 0; \ 192890075Sobrien if ((FROM) == ARG_POINTER_REGNUM) \ 192990075Sobrien { \ 193090075Sobrien int count_regs = 0; \ 193190075Sobrien int regno; \ 193290075Sobrien for (regno = 8; regno < 13; regno ++) \ 1933117395Skan if (THUMB_REG_PUSHED_P (regno)) \ 1934117395Skan count_regs ++; \ 193590075Sobrien if (count_regs) \ 193690075Sobrien (OFFSET) += 4 * count_regs; \ 193790075Sobrien count_regs = 0; \ 193890075Sobrien for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ 1939117395Skan if (THUMB_REG_PUSHED_P (regno)) \ 194090075Sobrien count_regs ++; \ 194190075Sobrien if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ 194290075Sobrien (OFFSET) += 4 * (count_regs + 1); \ 194390075Sobrien if (TARGET_BACKTRACE) \ 194490075Sobrien { \ 194590075Sobrien if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ 194690075Sobrien (OFFSET) += 20; \ 194790075Sobrien else \ 194890075Sobrien (OFFSET) += 16; \ 194990075Sobrien } \ 195090075Sobrien } \ 195190075Sobrien if ((TO) == STACK_POINTER_REGNUM) \ 195290075Sobrien { \ 195390075Sobrien (OFFSET) += current_function_outgoing_args_size; \ 1954117395Skan (OFFSET) += thumb_get_frame_size (); \ 195590075Sobrien } \ 195690075Sobrien} 195790075Sobrien 195890075Sobrien#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 195990075Sobrien if (TARGET_ARM) \ 196090075Sobrien ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \ 196190075Sobrien else \ 196290075Sobrien THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) 196390075Sobrien 196490075Sobrien/* Special case handling of the location of arguments passed on the stack. */ 196590075Sobrien#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 196690075Sobrien 196790075Sobrien/* Initialize data used by insn expanders. This is called from insn_emit, 196890075Sobrien once for every function before code is generated. */ 196990075Sobrien#define INIT_EXPANDERS arm_init_expanders () 197090075Sobrien 197190075Sobrien/* Output assembler code for a block containing the constant parts 197290075Sobrien of a trampoline, leaving space for the variable parts. 197390075Sobrien 197490075Sobrien On the ARM, (if r8 is the static chain regnum, and remembering that 197590075Sobrien referencing pc adds an offset of 8) the trampoline looks like: 197690075Sobrien ldr r8, [pc, #0] 197790075Sobrien ldr pc, [pc] 197890075Sobrien .word static chain value 197990075Sobrien .word function's address 1980132718Skan XXX FIXME: When the trampoline returns, r8 will be clobbered. */ 198190075Sobrien#define ARM_TRAMPOLINE_TEMPLATE(FILE) \ 198290075Sobrien{ \ 198390075Sobrien asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 198490075Sobrien STATIC_CHAIN_REGNUM, PC_REGNUM); \ 198590075Sobrien asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 198690075Sobrien PC_REGNUM, PC_REGNUM); \ 198790075Sobrien assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 198890075Sobrien assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 198990075Sobrien} 199090075Sobrien 199190075Sobrien/* On the Thumb we always switch into ARM mode to execute the trampoline. 199290075Sobrien Why - because it is easier. This code will always be branched to via 199390075Sobrien a BX instruction and since the compiler magically generates the address 199490075Sobrien of the function the linker has no opportunity to ensure that the 199590075Sobrien bottom bit is set. Thus the processor will be in ARM mode when it 199690075Sobrien reaches this code. So we duplicate the ARM trampoline code and add 199790075Sobrien a switch into Thumb mode as well. */ 199890075Sobrien#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ 199990075Sobrien{ \ 200090075Sobrien fprintf (FILE, "\t.code 32\n"); \ 200190075Sobrien fprintf (FILE, ".Ltrampoline_start:\n"); \ 200290075Sobrien asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ 200390075Sobrien STATIC_CHAIN_REGNUM, PC_REGNUM); \ 200490075Sobrien asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ 200590075Sobrien IP_REGNUM, PC_REGNUM); \ 200690075Sobrien asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ 200790075Sobrien IP_REGNUM, IP_REGNUM); \ 200890075Sobrien asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ 200990075Sobrien fprintf (FILE, "\t.word\t0\n"); \ 201090075Sobrien fprintf (FILE, "\t.word\t0\n"); \ 201190075Sobrien fprintf (FILE, "\t.code 16\n"); \ 201290075Sobrien} 201390075Sobrien 201490075Sobrien#define TRAMPOLINE_TEMPLATE(FILE) \ 201590075Sobrien if (TARGET_ARM) \ 201690075Sobrien ARM_TRAMPOLINE_TEMPLATE (FILE) \ 201790075Sobrien else \ 201890075Sobrien THUMB_TRAMPOLINE_TEMPLATE (FILE) 201990075Sobrien 202090075Sobrien/* Length in units of the trampoline for entering a nested function. */ 202190075Sobrien#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) 202290075Sobrien 202390075Sobrien/* Alignment required for a trampoline in bits. */ 202490075Sobrien#define TRAMPOLINE_ALIGNMENT 32 202590075Sobrien 202690075Sobrien/* Emit RTL insns to initialize the variable parts of a trampoline. 202790075Sobrien FNADDR is an RTX for the address of the function's pure code. 202890075Sobrien CXT is an RTX for the static chain value for the function. */ 2029132718Skan#ifndef INITIALIZE_TRAMPOLINE 2030132718Skan#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 2031132718Skan{ \ 2032132718Skan emit_move_insn (gen_rtx_MEM (SImode, \ 2033132718Skan plus_constant (TRAMP, \ 2034132718Skan TARGET_ARM ? 8 : 16)), \ 2035132718Skan CXT); \ 2036132718Skan emit_move_insn (gen_rtx_MEM (SImode, \ 2037132718Skan plus_constant (TRAMP, \ 2038132718Skan TARGET_ARM ? 12 : 20)), \ 2039132718Skan FNADDR); \ 204090075Sobrien} 2041132718Skan#endif 204290075Sobrien 204390075Sobrien 204490075Sobrien/* Addressing modes, and classification of registers for them. */ 2045132718Skan#define HAVE_POST_INCREMENT 1 2046132718Skan#define HAVE_PRE_INCREMENT TARGET_ARM 2047132718Skan#define HAVE_POST_DECREMENT TARGET_ARM 2048132718Skan#define HAVE_PRE_DECREMENT TARGET_ARM 2049132718Skan#define HAVE_PRE_MODIFY_DISP TARGET_ARM 2050132718Skan#define HAVE_POST_MODIFY_DISP TARGET_ARM 2051132718Skan#define HAVE_PRE_MODIFY_REG TARGET_ARM 2052132718Skan#define HAVE_POST_MODIFY_REG TARGET_ARM 205390075Sobrien 205490075Sobrien/* Macros to check register numbers against specific register classes. */ 205590075Sobrien 205690075Sobrien/* These assume that REGNO is a hard or pseudo reg number. 205790075Sobrien They give nonzero only if REGNO is a hard reg of the suitable class 205890075Sobrien or a pseudo reg currently allocated to a suitable hard reg. 205990075Sobrien Since they use reg_renumber, they are safe only once reg_renumber 2060132718Skan has been allocated, which happens in local-alloc.c. */ 206190075Sobrien#define TEST_REGNO(R, TEST, VALUE) \ 206290075Sobrien ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 206390075Sobrien 206490075Sobrien/* On the ARM, don't allow the pc to be used. */ 206590075Sobrien#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 206690075Sobrien (TEST_REGNO (REGNO, <, PC_REGNUM) \ 206790075Sobrien || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 206890075Sobrien || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 206990075Sobrien 207090075Sobrien#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 207190075Sobrien (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 207290075Sobrien || (GET_MODE_SIZE (MODE) >= 4 \ 207390075Sobrien && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 207490075Sobrien 207590075Sobrien#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 207690075Sobrien (TARGET_THUMB \ 207790075Sobrien ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 207890075Sobrien : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 207990075Sobrien 208090075Sobrien/* For ARM code, we don't care about the mode, but for Thumb, the index 208190075Sobrien must be suitable for use in a QImode load. */ 208290075Sobrien#define REGNO_OK_FOR_INDEX_P(REGNO) \ 208390075Sobrien REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) 208490075Sobrien 208590075Sobrien/* Maximum number of registers that can appear in a valid memory address. 2086132718Skan Shifts in addresses can't be by a register. */ 208790075Sobrien#define MAX_REGS_PER_ADDRESS 2 208890075Sobrien 208990075Sobrien/* Recognize any constant value that is a valid address. */ 209090075Sobrien/* XXX We can address any constant, eventually... */ 209190075Sobrien 209290075Sobrien#ifdef AOF_ASSEMBLER 209390075Sobrien 209490075Sobrien#define CONSTANT_ADDRESS_P(X) \ 209590075Sobrien (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) 209690075Sobrien 209790075Sobrien#else 209890075Sobrien 209990075Sobrien#define CONSTANT_ADDRESS_P(X) \ 210090075Sobrien (GET_CODE (X) == SYMBOL_REF \ 210190075Sobrien && (CONSTANT_POOL_ADDRESS_P (X) \ 210290075Sobrien || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 210390075Sobrien 210490075Sobrien#endif /* AOF_ASSEMBLER */ 210590075Sobrien 210690075Sobrien/* Nonzero if the constant value X is a legitimate general operand. 210790075Sobrien It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 210890075Sobrien 210990075Sobrien On the ARM, allow any integer (invalid ones are removed later by insn 211090075Sobrien patterns), nice doubles and symbol_refs which refer to the function's 211190075Sobrien constant pool XXX. 211290075Sobrien 211390075Sobrien When generating pic allow anything. */ 211490075Sobrien#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 211590075Sobrien 211690075Sobrien#define THUMB_LEGITIMATE_CONSTANT_P(X) \ 211790075Sobrien ( GET_CODE (X) == CONST_INT \ 211890075Sobrien || GET_CODE (X) == CONST_DOUBLE \ 211996263Sobrien || CONSTANT_ADDRESS_P (X) \ 212096263Sobrien || flag_pic) 212190075Sobrien 212290075Sobrien#define LEGITIMATE_CONSTANT_P(X) \ 212390075Sobrien (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) 212490075Sobrien 212590075Sobrien/* Special characters prefixed to function names 212690075Sobrien in order to encode attribute like information. 212790075Sobrien Note, '@' and '*' have already been taken. */ 212890075Sobrien#define SHORT_CALL_FLAG_CHAR '^' 212990075Sobrien#define LONG_CALL_FLAG_CHAR '#' 213090075Sobrien 213190075Sobrien#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ 213290075Sobrien (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) 213390075Sobrien 213490075Sobrien#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ 213590075Sobrien (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) 213690075Sobrien 213790075Sobrien#ifndef SUBTARGET_NAME_ENCODING_LENGTHS 213890075Sobrien#define SUBTARGET_NAME_ENCODING_LENGTHS 213990075Sobrien#endif 214090075Sobrien 2141132718Skan/* This is a C fragment for the inside of a switch statement. 214290075Sobrien Each case label should return the number of characters to 214390075Sobrien be stripped from the start of a function's name, if that 214490075Sobrien name starts with the indicated character. */ 214590075Sobrien#define ARM_NAME_ENCODING_LENGTHS \ 214690075Sobrien case SHORT_CALL_FLAG_CHAR: return 1; \ 214790075Sobrien case LONG_CALL_FLAG_CHAR: return 1; \ 214890075Sobrien case '*': return 1; \ 214990075Sobrien SUBTARGET_NAME_ENCODING_LENGTHS 215090075Sobrien 215190075Sobrien/* This is how to output a reference to a user-level label named NAME. 215290075Sobrien `assemble_name' uses this. */ 215390075Sobrien#undef ASM_OUTPUT_LABELREF 215490075Sobrien#define ASM_OUTPUT_LABELREF(FILE, NAME) \ 2155117395Skan arm_asm_output_labelref (FILE, NAME) 215690075Sobrien 215790075Sobrien#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ 215890075Sobrien arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) 215990075Sobrien 216090075Sobrien/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 216190075Sobrien and check its validity for a certain class. 216290075Sobrien We have two alternate definitions for each of them. 216390075Sobrien The usual definition accepts all pseudo regs; the other rejects 216490075Sobrien them unless they have been allocated suitable hard regs. 216590075Sobrien The symbol REG_OK_STRICT causes the latter definition to be used. */ 216690075Sobrien#ifndef REG_OK_STRICT 216790075Sobrien 216890075Sobrien#define ARM_REG_OK_FOR_BASE_P(X) \ 216990075Sobrien (REGNO (X) <= LAST_ARM_REGNUM \ 217090075Sobrien || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 217190075Sobrien || REGNO (X) == FRAME_POINTER_REGNUM \ 217290075Sobrien || REGNO (X) == ARG_POINTER_REGNUM) 217390075Sobrien 217490075Sobrien#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 217590075Sobrien (REGNO (X) <= LAST_LO_REGNUM \ 217690075Sobrien || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 217790075Sobrien || (GET_MODE_SIZE (MODE) >= 4 \ 217890075Sobrien && (REGNO (X) == STACK_POINTER_REGNUM \ 217990075Sobrien || (X) == hard_frame_pointer_rtx \ 218090075Sobrien || (X) == arg_pointer_rtx))) 218190075Sobrien 2182132718Skan#define REG_STRICT_P 0 2183132718Skan 218490075Sobrien#else /* REG_OK_STRICT */ 218590075Sobrien 218690075Sobrien#define ARM_REG_OK_FOR_BASE_P(X) \ 218790075Sobrien ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 218890075Sobrien 218990075Sobrien#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 219090075Sobrien THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 219190075Sobrien 2192132718Skan#define REG_STRICT_P 1 2193132718Skan 219490075Sobrien#endif /* REG_OK_STRICT */ 219590075Sobrien 219690075Sobrien/* Now define some helpers in terms of the above. */ 219790075Sobrien 219890075Sobrien#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 219990075Sobrien (TARGET_THUMB \ 220090075Sobrien ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 220190075Sobrien : ARM_REG_OK_FOR_BASE_P (X)) 220290075Sobrien 220390075Sobrien#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) 220490075Sobrien 220590075Sobrien/* For Thumb, a valid index register is anything that can be used in 220690075Sobrien a byte load instruction. */ 220790075Sobrien#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) 220890075Sobrien 220990075Sobrien/* Nonzero if X is a hard reg that can be used as an index 221090075Sobrien or if it is a pseudo reg. On the Thumb, the stack pointer 221190075Sobrien is not suitable. */ 221290075Sobrien#define REG_OK_FOR_INDEX_P(X) \ 221390075Sobrien (TARGET_THUMB \ 221490075Sobrien ? THUMB_REG_OK_FOR_INDEX_P (X) \ 221590075Sobrien : ARM_REG_OK_FOR_INDEX_P (X)) 221690075Sobrien 221790075Sobrien 221890075Sobrien/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 221990075Sobrien that is a valid memory address for an instruction. 222090075Sobrien The MODE argument is the machine mode for the MEM expression 2221132718Skan that wants to use this address. */ 222290075Sobrien 222390075Sobrien#define ARM_BASE_REGISTER_RTX_P(X) \ 222490075Sobrien (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 222590075Sobrien 222690075Sobrien#define ARM_INDEX_REGISTER_RTX_P(X) \ 222790075Sobrien (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 222890075Sobrien 2229132718Skan#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2230132718Skan { \ 2231132718Skan if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \ 2232132718Skan goto WIN; \ 2233132718Skan } 223490075Sobrien 2235132718Skan#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2236132718Skan { \ 2237132718Skan if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \ 2238132718Skan goto WIN; \ 2239132718Skan } 224090075Sobrien 224190075Sobrien#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 224290075Sobrien if (TARGET_ARM) \ 224390075Sobrien ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ 224490075Sobrien else /* if (TARGET_THUMB) */ \ 224590075Sobrien THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) 2246132718Skan 224790075Sobrien 224890075Sobrien/* Try machine-dependent ways of modifying an illegitimate address 2249132718Skan to be legitimate. If we find one, return the new, valid address. */ 2250132718Skan#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2251132718Skando { \ 2252132718Skan X = arm_legitimize_address (X, OLDX, MODE); \ 2253132718Skan \ 2254132718Skan if (memory_address_p (MODE, X)) \ 2255132718Skan goto WIN; \ 2256132718Skan} while (0) 225790075Sobrien 2258132718Skan#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2259132718Skando { \ 2260132718Skan if (flag_pic) \ 2261132718Skan (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 2262132718Skan} while (0) 226390075Sobrien 2264132718Skan#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2265132718Skando { \ 2266132718Skan if (TARGET_ARM) \ 2267132718Skan ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2268132718Skan else \ 2269132718Skan THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2270132718Skan} while (0) 227190075Sobrien 227290075Sobrien/* Go to LABEL if ADDR (a legitimate address expression) 227390075Sobrien has an effect that depends on the machine mode it is used for. */ 227490075Sobrien#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 227590075Sobrien{ \ 227690075Sobrien if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 227790075Sobrien || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 227890075Sobrien goto LABEL; \ 227990075Sobrien} 228090075Sobrien 228190075Sobrien/* Nothing helpful to do for the Thumb */ 228290075Sobrien#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 228390075Sobrien if (TARGET_ARM) \ 228490075Sobrien ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) 228590075Sobrien 228690075Sobrien 228790075Sobrien/* Specify the machine mode that this machine uses 228890075Sobrien for the index in the tablejump instruction. */ 228990075Sobrien#define CASE_VECTOR_MODE Pmode 229090075Sobrien 229190075Sobrien/* Define as C expression which evaluates to nonzero if the tablejump 229290075Sobrien instruction expects the table to contain offsets from the address of the 229390075Sobrien table. 2294132718Skan Do not define this if the table should contain absolute addresses. */ 229590075Sobrien/* #define CASE_VECTOR_PC_RELATIVE 1 */ 229690075Sobrien 229790075Sobrien/* signed 'char' is most compatible, but RISC OS wants it unsigned. 229890075Sobrien unsigned is probably best, but may break some code. */ 229990075Sobrien#ifndef DEFAULT_SIGNED_CHAR 230090075Sobrien#define DEFAULT_SIGNED_CHAR 0 230190075Sobrien#endif 230290075Sobrien 230390075Sobrien/* Don't cse the address of the function being compiled. */ 230490075Sobrien#define NO_RECURSIVE_FUNCTION_CSE 1 230590075Sobrien 230690075Sobrien/* Max number of bytes we can move from memory to memory 230790075Sobrien in one reasonably fast instruction. */ 230890075Sobrien#define MOVE_MAX 4 230990075Sobrien 231090075Sobrien#undef MOVE_RATIO 2311132718Skan#define MOVE_RATIO (arm_tune_xscale ? 4 : 2) 231290075Sobrien 231390075Sobrien/* Define if operations between registers always perform the operation 231490075Sobrien on the full register even if a narrower mode is specified. */ 231590075Sobrien#define WORD_REGISTER_OPERATIONS 231690075Sobrien 231790075Sobrien/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 231890075Sobrien will either zero-extend or sign-extend. The value of this macro should 231990075Sobrien be the code that says which one of the two operations is implicitly 232090075Sobrien done, NIL if none. */ 232190075Sobrien#define LOAD_EXTEND_OP(MODE) \ 232290075Sobrien (TARGET_THUMB ? ZERO_EXTEND : \ 232390075Sobrien ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 232490075Sobrien : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) 232590075Sobrien 232690075Sobrien/* Nonzero if access to memory by bytes is slow and undesirable. */ 232790075Sobrien#define SLOW_BYTE_ACCESS 0 232890075Sobrien 232990075Sobrien#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 233090075Sobrien 233190075Sobrien/* Immediate shift counts are truncated by the output routines (or was it 233290075Sobrien the assembler?). Shift counts in a register are truncated by ARM. Note 233390075Sobrien that the native compiler puts too large (> 32) immediate shift counts 233490075Sobrien into a register and shifts by the register, letting the ARM decide what 233590075Sobrien to do instead of doing that itself. */ 233690075Sobrien/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 233790075Sobrien code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 233890075Sobrien On the arm, Y in a register is used modulo 256 for the shift. Only for 2339132718Skan rotates is modulo 32 used. */ 234090075Sobrien/* #define SHIFT_COUNT_TRUNCATED 1 */ 234190075Sobrien 234290075Sobrien/* All integers have the same format so truncation is easy. */ 234390075Sobrien#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 234490075Sobrien 234590075Sobrien/* Calling from registers is a massive pain. */ 234690075Sobrien#define NO_FUNCTION_CSE 1 234790075Sobrien 234890075Sobrien/* Chars and shorts should be passed as ints. */ 234990075Sobrien#define PROMOTE_PROTOTYPES 1 235090075Sobrien 235190075Sobrien/* The machine modes of pointers and functions */ 235290075Sobrien#define Pmode SImode 235390075Sobrien#define FUNCTION_MODE Pmode 235490075Sobrien 235590075Sobrien#define ARM_FRAME_RTX(X) \ 235690075Sobrien ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 235790075Sobrien || (X) == arg_pointer_rtx) 235890075Sobrien 235990075Sobrien/* Moves to and from memory are quite expensive */ 236090075Sobrien#define MEMORY_MOVE_COST(M, CLASS, IN) \ 236190075Sobrien (TARGET_ARM ? 10 : \ 236290075Sobrien ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 236390075Sobrien * (CLASS == LO_REGS ? 1 : 2))) 236490075Sobrien 236590075Sobrien/* Try to generate sequences that don't involve branches, we can then use 236690075Sobrien conditional instructions */ 236790075Sobrien#define BRANCH_COST \ 236890075Sobrien (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) 236990075Sobrien 237090075Sobrien/* Position Independent Code. */ 237190075Sobrien/* We decide which register to use based on the compilation options and 237290075Sobrien the assembler in use; this is more general than the APCS restriction of 237390075Sobrien using sb (r9) all the time. */ 237490075Sobrienextern int arm_pic_register; 237590075Sobrien 237690075Sobrien/* Used when parsing command line option -mpic-register=. */ 237790075Sobrienextern const char * arm_pic_register_string; 237890075Sobrien 237990075Sobrien/* The register number of the register used to address a table of static 238090075Sobrien data addresses in memory. */ 238190075Sobrien#define PIC_OFFSET_TABLE_REGNUM arm_pic_register 238290075Sobrien 238390075Sobrien#define FINALIZE_PIC arm_finalize_pic (1) 238490075Sobrien 238590075Sobrien/* We can't directly access anything that contains a symbol, 238690075Sobrien nor can we indirect via the constant pool. */ 238790075Sobrien#define LEGITIMATE_PIC_OPERAND_P(X) \ 2388117395Skan (!(symbol_mentioned_p (X) \ 2389117395Skan || label_mentioned_p (X) \ 2390117395Skan || (GET_CODE (X) == SYMBOL_REF \ 2391117395Skan && CONSTANT_POOL_ADDRESS_P (X) \ 2392117395Skan && (symbol_mentioned_p (get_pool_constant (X)) \ 2393117395Skan || label_mentioned_p (get_pool_constant (X)))))) 2394117395Skan 239590075Sobrien/* We need to know when we are making a constant pool; this determines 239690075Sobrien whether data needs to be in the GOT or can be referenced via a GOT 239790075Sobrien offset. */ 239890075Sobrienextern int making_const_table; 239990075Sobrien 240090075Sobrien/* Handle pragmas for compatibility with Intel's compilers. */ 2401132718Skan#define REGISTER_TARGET_PRAGMAS() do { \ 2402132718Skan c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2403132718Skan c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2404132718Skan c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 240590075Sobrien} while (0) 240690075Sobrien 2407132718Skan/* Condition code information. */ 240890075Sobrien/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2409117395Skan return the mode to be used for the comparison. */ 241090075Sobrien 241190075Sobrien#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 241290075Sobrien 241390075Sobrien#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 241490075Sobrien 241590075Sobrien#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 241690075Sobrien do \ 241790075Sobrien { \ 241890075Sobrien if (GET_CODE (OP1) == CONST_INT \ 241990075Sobrien && ! (const_ok_for_arm (INTVAL (OP1)) \ 242090075Sobrien || (const_ok_for_arm (- INTVAL (OP1))))) \ 242190075Sobrien { \ 242290075Sobrien rtx const_op = OP1; \ 242390075Sobrien CODE = arm_canonicalize_comparison ((CODE), &const_op); \ 242490075Sobrien OP1 = const_op; \ 242590075Sobrien } \ 242690075Sobrien } \ 242790075Sobrien while (0) 242890075Sobrien 2429132718Skan/* The arm5 clz instruction returns 32. */ 2430132718Skan#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 243190075Sobrien 243290075Sobrien#undef ASM_APP_OFF 243390075Sobrien#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") 243490075Sobrien 243590075Sobrien/* Output a push or a pop instruction (only used when profiling). */ 243690075Sobrien#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2437132718Skan do \ 2438132718Skan { \ 2439132718Skan if (TARGET_ARM) \ 2440132718Skan asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2441132718Skan STACK_POINTER_REGNUM, REGNO); \ 2442132718Skan else \ 2443132718Skan asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2444132718Skan } while (0) 244590075Sobrien 244690075Sobrien 244790075Sobrien#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2448132718Skan do \ 2449132718Skan { \ 2450132718Skan if (TARGET_ARM) \ 2451132718Skan asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2452132718Skan STACK_POINTER_REGNUM, REGNO); \ 2453132718Skan else \ 2454132718Skan asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2455132718Skan } while (0) 245690075Sobrien 245790075Sobrien/* This is how to output a label which precedes a jumptable. Since 245890075Sobrien Thumb instructions are 2 bytes, we may need explicit alignment here. */ 245990075Sobrien#undef ASM_OUTPUT_CASE_LABEL 246090075Sobrien#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 246190075Sobrien do \ 246290075Sobrien { \ 246390075Sobrien if (TARGET_THUMB) \ 246490075Sobrien ASM_OUTPUT_ALIGN (FILE, 2); \ 2465132718Skan (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 246690075Sobrien } \ 246790075Sobrien while (0) 246890075Sobrien 246990075Sobrien#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 247090075Sobrien do \ 247190075Sobrien { \ 247290075Sobrien if (TARGET_THUMB) \ 247390075Sobrien { \ 2474132718Skan if (is_called_in_ARM_mode (DECL) \ 2475132718Skan || current_function_is_thunk) \ 247690075Sobrien fprintf (STREAM, "\t.code 32\n") ; \ 247790075Sobrien else \ 2478132718Skan fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \ 247990075Sobrien } \ 248090075Sobrien if (TARGET_POKE_FUNCTION_NAME) \ 248190075Sobrien arm_poke_function_name (STREAM, (char *) NAME); \ 248290075Sobrien } \ 248390075Sobrien while (0) 248490075Sobrien 248590075Sobrien/* For aliases of functions we use .thumb_set instead. */ 248690075Sobrien#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 248790075Sobrien do \ 248890075Sobrien { \ 248990075Sobrien const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 249090075Sobrien const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 249190075Sobrien \ 249290075Sobrien if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 249390075Sobrien { \ 249490075Sobrien fprintf (FILE, "\t.thumb_set "); \ 249590075Sobrien assemble_name (FILE, LABEL1); \ 249690075Sobrien fprintf (FILE, ","); \ 249790075Sobrien assemble_name (FILE, LABEL2); \ 249890075Sobrien fprintf (FILE, "\n"); \ 249990075Sobrien } \ 250090075Sobrien else \ 250190075Sobrien ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 250290075Sobrien } \ 250390075Sobrien while (0) 250490075Sobrien 250590075Sobrien#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 250690075Sobrien/* To support -falign-* switches we need to use .p2align so 250790075Sobrien that alignment directives in code sections will be padded 250890075Sobrien with no-op instructions, rather than zeroes. */ 2509132718Skan#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 251090075Sobrien if ((LOG) != 0) \ 251190075Sobrien { \ 251290075Sobrien if ((MAX_SKIP) == 0) \ 2513132718Skan fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 251490075Sobrien else \ 251590075Sobrien fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2516132718Skan (int) (LOG), (int) (MAX_SKIP)); \ 251790075Sobrien } 251890075Sobrien#endif 251990075Sobrien 252090075Sobrien/* Only perform branch elimination (by making instructions conditional) if 2521132718Skan we're optimizing. Otherwise it's of no use anyway. */ 252290075Sobrien#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 252390075Sobrien if (TARGET_ARM && optimize) \ 252490075Sobrien arm_final_prescan_insn (INSN); \ 252590075Sobrien else if (TARGET_THUMB) \ 252690075Sobrien thumb_final_prescan_insn (INSN) 252790075Sobrien 252890075Sobrien#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 252990075Sobrien (CODE == '@' || CODE == '|' \ 253090075Sobrien || (TARGET_ARM && (CODE == '?')) \ 253190075Sobrien || (TARGET_THUMB && (CODE == '_'))) 253290075Sobrien 253390075Sobrien/* Output an operand of an instruction. */ 253490075Sobrien#define PRINT_OPERAND(STREAM, X, CODE) \ 253590075Sobrien arm_print_operand (STREAM, X, CODE) 253690075Sobrien 253790075Sobrien#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 253890075Sobrien (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 253990075Sobrien : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 254090075Sobrien ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 254190075Sobrien ? ((~ (unsigned HOST_WIDE_INT) 0) \ 254290075Sobrien & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 254390075Sobrien : 0)))) 254490075Sobrien 254590075Sobrien/* Output the address of an operand. */ 2546132718Skan#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2547132718Skan{ \ 2548132718Skan int is_minus = GET_CODE (X) == MINUS; \ 2549132718Skan \ 2550132718Skan if (GET_CODE (X) == REG) \ 2551132718Skan asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2552132718Skan else if (GET_CODE (X) == PLUS || is_minus) \ 2553132718Skan { \ 2554132718Skan rtx base = XEXP (X, 0); \ 2555132718Skan rtx index = XEXP (X, 1); \ 2556132718Skan HOST_WIDE_INT offset = 0; \ 2557132718Skan if (GET_CODE (base) != REG) \ 2558132718Skan { \ 2559132718Skan /* Ensure that BASE is a register. */ \ 2560132718Skan /* (one of them must be). */ \ 2561132718Skan rtx temp = base; \ 2562132718Skan base = index; \ 2563132718Skan index = temp; \ 2564132718Skan } \ 2565132718Skan switch (GET_CODE (index)) \ 2566132718Skan { \ 2567132718Skan case CONST_INT: \ 2568132718Skan offset = INTVAL (index); \ 2569132718Skan if (is_minus) \ 2570132718Skan offset = -offset; \ 2571132718Skan asm_fprintf (STREAM, "[%r, #%wd]", \ 2572132718Skan REGNO (base), offset); \ 2573132718Skan break; \ 2574132718Skan \ 2575132718Skan case REG: \ 2576132718Skan asm_fprintf (STREAM, "[%r, %s%r]", \ 2577132718Skan REGNO (base), is_minus ? "-" : "", \ 2578132718Skan REGNO (index)); \ 2579132718Skan break; \ 2580132718Skan \ 2581132718Skan case MULT: \ 2582132718Skan case ASHIFTRT: \ 2583132718Skan case LSHIFTRT: \ 2584132718Skan case ASHIFT: \ 2585132718Skan case ROTATERT: \ 2586132718Skan { \ 2587132718Skan asm_fprintf (STREAM, "[%r, %s%r", \ 2588132718Skan REGNO (base), is_minus ? "-" : "", \ 2589132718Skan REGNO (XEXP (index, 0))); \ 2590132718Skan arm_print_operand (STREAM, index, 'S'); \ 2591132718Skan fputs ("]", STREAM); \ 2592132718Skan break; \ 2593132718Skan } \ 2594132718Skan \ 2595132718Skan default: \ 2596132718Skan abort(); \ 2597132718Skan } \ 2598132718Skan } \ 2599132718Skan else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2600132718Skan || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2601132718Skan { \ 2602132718Skan extern enum machine_mode output_memory_reference_mode; \ 2603132718Skan \ 2604132718Skan if (GET_CODE (XEXP (X, 0)) != REG) \ 2605132718Skan abort (); \ 2606132718Skan \ 2607132718Skan if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2608132718Skan asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2609132718Skan REGNO (XEXP (X, 0)), \ 2610132718Skan GET_CODE (X) == PRE_DEC ? "-" : "", \ 2611132718Skan GET_MODE_SIZE (output_memory_reference_mode)); \ 2612132718Skan else \ 2613132718Skan asm_fprintf (STREAM, "[%r], #%s%d", \ 2614132718Skan REGNO (XEXP (X, 0)), \ 2615132718Skan GET_CODE (X) == POST_DEC ? "-" : "", \ 2616132718Skan GET_MODE_SIZE (output_memory_reference_mode)); \ 2617132718Skan } \ 2618132718Skan else if (GET_CODE (X) == PRE_MODIFY) \ 2619132718Skan { \ 2620132718Skan asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ 2621132718Skan if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2622132718Skan asm_fprintf (STREAM, "#%wd]!", \ 2623132718Skan INTVAL (XEXP (XEXP (X, 1), 1))); \ 2624132718Skan else \ 2625132718Skan asm_fprintf (STREAM, "%r]!", \ 2626132718Skan REGNO (XEXP (XEXP (X, 1), 1))); \ 2627132718Skan } \ 2628132718Skan else if (GET_CODE (X) == POST_MODIFY) \ 2629132718Skan { \ 2630132718Skan asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ 2631132718Skan if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2632132718Skan asm_fprintf (STREAM, "#%wd", \ 2633132718Skan INTVAL (XEXP (XEXP (X, 1), 1))); \ 2634132718Skan else \ 2635132718Skan asm_fprintf (STREAM, "%r", \ 2636132718Skan REGNO (XEXP (XEXP (X, 1), 1))); \ 2637132718Skan } \ 2638132718Skan else output_addr_const (STREAM, X); \ 263990075Sobrien} 264090075Sobrien 264190075Sobrien#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 264290075Sobrien{ \ 264390075Sobrien if (GET_CODE (X) == REG) \ 264490075Sobrien asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 264590075Sobrien else if (GET_CODE (X) == POST_INC) \ 264690075Sobrien asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 264790075Sobrien else if (GET_CODE (X) == PLUS) \ 264890075Sobrien { \ 2649132718Skan if (GET_CODE (XEXP (X, 0)) != REG) \ 2650132718Skan abort (); \ 265190075Sobrien if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2652132718Skan asm_fprintf (STREAM, "[%r, #%wd]", \ 265390075Sobrien REGNO (XEXP (X, 0)), \ 2654132718Skan INTVAL (XEXP (X, 1))); \ 265590075Sobrien else \ 265690075Sobrien asm_fprintf (STREAM, "[%r, %r]", \ 265790075Sobrien REGNO (XEXP (X, 0)), \ 265890075Sobrien REGNO (XEXP (X, 1))); \ 265990075Sobrien } \ 266090075Sobrien else \ 266190075Sobrien output_addr_const (STREAM, X); \ 266290075Sobrien} 266390075Sobrien 266490075Sobrien#define PRINT_OPERAND_ADDRESS(STREAM, X) \ 266590075Sobrien if (TARGET_ARM) \ 266690075Sobrien ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 266790075Sobrien else \ 266890075Sobrien THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2669132718Skan 2670132718Skan#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2671132718Skan if (GET_CODE (X) != CONST_VECTOR \ 2672132718Skan || ! arm_emit_vector_const (FILE, X)) \ 2673132718Skan goto FAIL; 2674132718Skan 267590075Sobrien/* A C expression whose value is RTL representing the value of the return 267690075Sobrien address for the frame COUNT steps up from the current frame. */ 267790075Sobrien 267890075Sobrien#define RETURN_ADDR_RTX(COUNT, FRAME) \ 267990075Sobrien arm_return_addr (COUNT, FRAME) 268090075Sobrien 268190075Sobrien/* Mask of the bits in the PC that contain the real return address 268290075Sobrien when running in 26-bit mode. */ 268390075Sobrien#define RETURN_ADDR_MASK26 (0x03fffffc) 268490075Sobrien 268590075Sobrien/* Pick up the return address upon entry to a procedure. Used for 268690075Sobrien dwarf2 unwind information. This also enables the table driven 268790075Sobrien mechanism. */ 268890075Sobrien#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 268990075Sobrien#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 269090075Sobrien 269190075Sobrien/* Used to mask out junk bits from the return address, such as 269290075Sobrien processor state, interrupt status, condition codes and the like. */ 269390075Sobrien#define MASK_RETURN_ADDR \ 269490075Sobrien /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 269590075Sobrien in 26 bit mode, the condition codes must be masked out of the \ 269690075Sobrien return address. This does not apply to ARM6 and later processors \ 269790075Sobrien when running in 32 bit mode. */ \ 2698117395Skan ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \ 2699117395Skan : (arm_arch4 || TARGET_THUMB) ? \ 2700117395Skan (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2701117395Skan : arm_gen_return_addr_mask ()) 270290075Sobrien 270390075Sobrien 270490075Sobrien/* Define the codes that are matched by predicates in arm.c */ 270590075Sobrien#define PREDICATE_CODES \ 270690075Sobrien {"s_register_operand", {SUBREG, REG}}, \ 270790075Sobrien {"arm_hard_register_operand", {REG}}, \ 270890075Sobrien {"f_register_operand", {SUBREG, REG}}, \ 270990075Sobrien {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ 2710132718Skan {"arm_addimm_operand", {CONST_INT}}, \ 2711132718Skan {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2712132718Skan {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 271390075Sobrien {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ 271490075Sobrien {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ 271590075Sobrien {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ 271690075Sobrien {"index_operand", {SUBREG, REG, CONST_INT}}, \ 271790075Sobrien {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ 2718132718Skan {"thumb_cmpneg_operand", {CONST_INT}}, \ 2719132718Skan {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \ 272090075Sobrien {"offsettable_memory_operand", {MEM}}, \ 272190075Sobrien {"bad_signed_byte_operand", {MEM}}, \ 272290075Sobrien {"alignable_memory_operand", {MEM}}, \ 272390075Sobrien {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ 272490075Sobrien {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ 272590075Sobrien {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ 272690075Sobrien {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 272790075Sobrien {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ 272890075Sobrien {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ 272990075Sobrien {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ 273090075Sobrien {"load_multiple_operation", {PARALLEL}}, \ 273190075Sobrien {"store_multiple_operation", {PARALLEL}}, \ 273290075Sobrien {"equality_operator", {EQ, NE}}, \ 273390075Sobrien {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ 273490075Sobrien LTU, UNORDERED, ORDERED, UNLT, UNLE, \ 273590075Sobrien UNGE, UNGT}}, \ 273690075Sobrien {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 273790075Sobrien {"const_shift_operand", {CONST_INT}}, \ 273890075Sobrien {"multi_register_push", {PARALLEL}}, \ 273990075Sobrien {"cc_register", {REG}}, \ 274090075Sobrien {"logical_binary_operator", {AND, IOR, XOR}}, \ 2741132718Skan {"cirrus_register_operand", {REG}}, \ 2742132718Skan {"cirrus_fp_register", {REG}}, \ 2743132718Skan {"cirrus_shift_const", {CONST_INT}}, \ 274490075Sobrien {"dominant_cc_register", {REG}}, 274590075Sobrien 274690075Sobrien/* Define this if you have special predicates that know special things 274790075Sobrien about modes. Genrecog will warn about certain forms of 274890075Sobrien match_operand without a mode; if the operand predicate is listed in 2749132718Skan SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ 275090075Sobrien#define SPECIAL_MODE_PREDICATES \ 275190075Sobrien "cc_register", "dominant_cc_register", 275290075Sobrien 275390075Sobrienenum arm_builtins 275490075Sobrien{ 2755132718Skan ARM_BUILTIN_GETWCX, 2756132718Skan ARM_BUILTIN_SETWCX, 2757132718Skan 2758132718Skan ARM_BUILTIN_WZERO, 2759132718Skan 2760132718Skan ARM_BUILTIN_WAVG2BR, 2761132718Skan ARM_BUILTIN_WAVG2HR, 2762132718Skan ARM_BUILTIN_WAVG2B, 2763132718Skan ARM_BUILTIN_WAVG2H, 2764132718Skan 2765132718Skan ARM_BUILTIN_WACCB, 2766132718Skan ARM_BUILTIN_WACCH, 2767132718Skan ARM_BUILTIN_WACCW, 2768132718Skan 2769132718Skan ARM_BUILTIN_WMACS, 2770132718Skan ARM_BUILTIN_WMACSZ, 2771132718Skan ARM_BUILTIN_WMACU, 2772132718Skan ARM_BUILTIN_WMACUZ, 2773132718Skan 2774132718Skan ARM_BUILTIN_WSADB, 2775132718Skan ARM_BUILTIN_WSADBZ, 2776132718Skan ARM_BUILTIN_WSADH, 2777132718Skan ARM_BUILTIN_WSADHZ, 2778132718Skan 2779132718Skan ARM_BUILTIN_WALIGN, 2780132718Skan 2781132718Skan ARM_BUILTIN_TMIA, 2782132718Skan ARM_BUILTIN_TMIAPH, 2783132718Skan ARM_BUILTIN_TMIABB, 2784132718Skan ARM_BUILTIN_TMIABT, 2785132718Skan ARM_BUILTIN_TMIATB, 2786132718Skan ARM_BUILTIN_TMIATT, 2787132718Skan 2788132718Skan ARM_BUILTIN_TMOVMSKB, 2789132718Skan ARM_BUILTIN_TMOVMSKH, 2790132718Skan ARM_BUILTIN_TMOVMSKW, 2791132718Skan 2792132718Skan ARM_BUILTIN_TBCSTB, 2793132718Skan ARM_BUILTIN_TBCSTH, 2794132718Skan ARM_BUILTIN_TBCSTW, 2795132718Skan 2796132718Skan ARM_BUILTIN_WMADDS, 2797132718Skan ARM_BUILTIN_WMADDU, 2798132718Skan 2799132718Skan ARM_BUILTIN_WPACKHSS, 2800132718Skan ARM_BUILTIN_WPACKWSS, 2801132718Skan ARM_BUILTIN_WPACKDSS, 2802132718Skan ARM_BUILTIN_WPACKHUS, 2803132718Skan ARM_BUILTIN_WPACKWUS, 2804132718Skan ARM_BUILTIN_WPACKDUS, 2805132718Skan 2806132718Skan ARM_BUILTIN_WADDB, 2807132718Skan ARM_BUILTIN_WADDH, 2808132718Skan ARM_BUILTIN_WADDW, 2809132718Skan ARM_BUILTIN_WADDSSB, 2810132718Skan ARM_BUILTIN_WADDSSH, 2811132718Skan ARM_BUILTIN_WADDSSW, 2812132718Skan ARM_BUILTIN_WADDUSB, 2813132718Skan ARM_BUILTIN_WADDUSH, 2814132718Skan ARM_BUILTIN_WADDUSW, 2815132718Skan ARM_BUILTIN_WSUBB, 2816132718Skan ARM_BUILTIN_WSUBH, 2817132718Skan ARM_BUILTIN_WSUBW, 2818132718Skan ARM_BUILTIN_WSUBSSB, 2819132718Skan ARM_BUILTIN_WSUBSSH, 2820132718Skan ARM_BUILTIN_WSUBSSW, 2821132718Skan ARM_BUILTIN_WSUBUSB, 2822132718Skan ARM_BUILTIN_WSUBUSH, 2823132718Skan ARM_BUILTIN_WSUBUSW, 2824132718Skan 2825132718Skan ARM_BUILTIN_WAND, 2826132718Skan ARM_BUILTIN_WANDN, 2827132718Skan ARM_BUILTIN_WOR, 2828132718Skan ARM_BUILTIN_WXOR, 2829132718Skan 2830132718Skan ARM_BUILTIN_WCMPEQB, 2831132718Skan ARM_BUILTIN_WCMPEQH, 2832132718Skan ARM_BUILTIN_WCMPEQW, 2833132718Skan ARM_BUILTIN_WCMPGTUB, 2834132718Skan ARM_BUILTIN_WCMPGTUH, 2835132718Skan ARM_BUILTIN_WCMPGTUW, 2836132718Skan ARM_BUILTIN_WCMPGTSB, 2837132718Skan ARM_BUILTIN_WCMPGTSH, 2838132718Skan ARM_BUILTIN_WCMPGTSW, 2839132718Skan 2840132718Skan ARM_BUILTIN_TEXTRMSB, 2841132718Skan ARM_BUILTIN_TEXTRMSH, 2842132718Skan ARM_BUILTIN_TEXTRMSW, 2843132718Skan ARM_BUILTIN_TEXTRMUB, 2844132718Skan ARM_BUILTIN_TEXTRMUH, 2845132718Skan ARM_BUILTIN_TEXTRMUW, 2846132718Skan ARM_BUILTIN_TINSRB, 2847132718Skan ARM_BUILTIN_TINSRH, 2848132718Skan ARM_BUILTIN_TINSRW, 2849132718Skan 2850132718Skan ARM_BUILTIN_WMAXSW, 2851132718Skan ARM_BUILTIN_WMAXSH, 2852132718Skan ARM_BUILTIN_WMAXSB, 2853132718Skan ARM_BUILTIN_WMAXUW, 2854132718Skan ARM_BUILTIN_WMAXUH, 2855132718Skan ARM_BUILTIN_WMAXUB, 2856132718Skan ARM_BUILTIN_WMINSW, 2857132718Skan ARM_BUILTIN_WMINSH, 2858132718Skan ARM_BUILTIN_WMINSB, 2859132718Skan ARM_BUILTIN_WMINUW, 2860132718Skan ARM_BUILTIN_WMINUH, 2861132718Skan ARM_BUILTIN_WMINUB, 2862132718Skan 2863132718Skan ARM_BUILTIN_WMULUH, 2864132718Skan ARM_BUILTIN_WMULSH, 2865132718Skan ARM_BUILTIN_WMULUL, 2866132718Skan 2867132718Skan ARM_BUILTIN_PSADBH, 2868132718Skan ARM_BUILTIN_WSHUFH, 2869132718Skan 2870132718Skan ARM_BUILTIN_WSLLH, 2871132718Skan ARM_BUILTIN_WSLLW, 2872132718Skan ARM_BUILTIN_WSLLD, 2873132718Skan ARM_BUILTIN_WSRAH, 2874132718Skan ARM_BUILTIN_WSRAW, 2875132718Skan ARM_BUILTIN_WSRAD, 2876132718Skan ARM_BUILTIN_WSRLH, 2877132718Skan ARM_BUILTIN_WSRLW, 2878132718Skan ARM_BUILTIN_WSRLD, 2879132718Skan ARM_BUILTIN_WRORH, 2880132718Skan ARM_BUILTIN_WRORW, 2881132718Skan ARM_BUILTIN_WRORD, 2882132718Skan ARM_BUILTIN_WSLLHI, 2883132718Skan ARM_BUILTIN_WSLLWI, 2884132718Skan ARM_BUILTIN_WSLLDI, 2885132718Skan ARM_BUILTIN_WSRAHI, 2886132718Skan ARM_BUILTIN_WSRAWI, 2887132718Skan ARM_BUILTIN_WSRADI, 2888132718Skan ARM_BUILTIN_WSRLHI, 2889132718Skan ARM_BUILTIN_WSRLWI, 2890132718Skan ARM_BUILTIN_WSRLDI, 2891132718Skan ARM_BUILTIN_WRORHI, 2892132718Skan ARM_BUILTIN_WRORWI, 2893132718Skan ARM_BUILTIN_WRORDI, 2894132718Skan 2895132718Skan ARM_BUILTIN_WUNPCKIHB, 2896132718Skan ARM_BUILTIN_WUNPCKIHH, 2897132718Skan ARM_BUILTIN_WUNPCKIHW, 2898132718Skan ARM_BUILTIN_WUNPCKILB, 2899132718Skan ARM_BUILTIN_WUNPCKILH, 2900132718Skan ARM_BUILTIN_WUNPCKILW, 2901132718Skan 2902132718Skan ARM_BUILTIN_WUNPCKEHSB, 2903132718Skan ARM_BUILTIN_WUNPCKEHSH, 2904132718Skan ARM_BUILTIN_WUNPCKEHSW, 2905132718Skan ARM_BUILTIN_WUNPCKEHUB, 2906132718Skan ARM_BUILTIN_WUNPCKEHUH, 2907132718Skan ARM_BUILTIN_WUNPCKEHUW, 2908132718Skan ARM_BUILTIN_WUNPCKELSB, 2909132718Skan ARM_BUILTIN_WUNPCKELSH, 2910132718Skan ARM_BUILTIN_WUNPCKELSW, 2911132718Skan ARM_BUILTIN_WUNPCKELUB, 2912132718Skan ARM_BUILTIN_WUNPCKELUH, 2913132718Skan ARM_BUILTIN_WUNPCKELUW, 2914132718Skan 291590075Sobrien ARM_BUILTIN_MAX 291690075Sobrien}; 291790075Sobrien#endif /* ! GCC_ARM_H */ 2918