arm.h revision 132718
1/* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004 Free Software Foundation, Inc. 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5 and Martin Simmons (@harleqn.co.uk). 6 More major hacks by Richard Earnshaw (rearnsha@arm.com) 7 Minor hacks by Nick Clifton (nickc@cygnus.com) 8 9 This file is part of GCC. 10 11 GCC is free software; you can redistribute it and/or modify it 12 under the terms of the GNU General Public License as published 13 by the Free Software Foundation; either version 2, or (at your 14 option) any later version. 15 16 GCC is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GCC; see the file COPYING. If not, write to 23 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, 24 MA 02111-1307, USA. */ 25 26#ifndef GCC_ARM_H 27#define GCC_ARM_H 28 29/* Target CPU builtins. */ 30#define TARGET_CPU_CPP_BUILTINS() \ 31 do \ 32 { \ 33 if (TARGET_ARM) \ 34 builtin_define ("__arm__"); \ 35 else \ 36 builtin_define ("__thumb__"); \ 37 \ 38 if (TARGET_BIG_END) \ 39 { \ 40 builtin_define ("__ARMEB__"); \ 41 if (TARGET_THUMB) \ 42 builtin_define ("__THUMBEB__"); \ 43 if (TARGET_LITTLE_WORDS) \ 44 builtin_define ("__ARMWEL__"); \ 45 } \ 46 else \ 47 { \ 48 builtin_define ("__ARMEL__"); \ 49 if (TARGET_THUMB) \ 50 builtin_define ("__THUMBEL__"); \ 51 } \ 52 \ 53 if (TARGET_APCS_32) \ 54 builtin_define ("__APCS_32__"); \ 55 else \ 56 builtin_define ("__APCS_26__"); \ 57 \ 58 if (TARGET_SOFT_FLOAT) \ 59 builtin_define ("__SOFTFP__"); \ 60 \ 61 /* FIXME: TARGET_HARD_FLOAT currently implies \ 62 FPA. */ \ 63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \ 64 builtin_define ("__VFP_FP__"); \ 65 \ 66 /* Add a define for interworking. \ 67 Needed when building libgcc.a. */ \ 68 if (TARGET_INTERWORK) \ 69 builtin_define ("__THUMB_INTERWORK__"); \ 70 \ 71 builtin_assert ("cpu=arm"); \ 72 builtin_assert ("machine=arm"); \ 73 } while (0) 74 75#define TARGET_CPU_arm2 0x0000 76#define TARGET_CPU_arm250 0x0000 77#define TARGET_CPU_arm3 0x0000 78#define TARGET_CPU_arm6 0x0001 79#define TARGET_CPU_arm600 0x0001 80#define TARGET_CPU_arm610 0x0002 81#define TARGET_CPU_arm7 0x0001 82#define TARGET_CPU_arm7m 0x0004 83#define TARGET_CPU_arm7dm 0x0004 84#define TARGET_CPU_arm7dmi 0x0004 85#define TARGET_CPU_arm700 0x0001 86#define TARGET_CPU_arm710 0x0002 87#define TARGET_CPU_arm7100 0x0002 88#define TARGET_CPU_arm7500 0x0002 89#define TARGET_CPU_arm7500fe 0x1001 90#define TARGET_CPU_arm7tdmi 0x0008 91#define TARGET_CPU_arm8 0x0010 92#define TARGET_CPU_arm810 0x0020 93#define TARGET_CPU_strongarm 0x0040 94#define TARGET_CPU_strongarm110 0x0040 95#define TARGET_CPU_strongarm1100 0x0040 96#define TARGET_CPU_arm9 0x0080 97#define TARGET_CPU_arm9tdmi 0x0080 98#define TARGET_CPU_xscale 0x0100 99#define TARGET_CPU_ep9312 0x0200 100#define TARGET_CPU_iwmmxt 0x0400 101#define TARGET_CPU_arm926ej_s 0x0800 102#define TARGET_CPU_arm1026ej_s 0x1000 103#define TARGET_CPU_arm1136j_s 0x2000 104#define TARGET_CPU_arm1136jf_s 0x4000 105/* Configure didn't specify. */ 106#define TARGET_CPU_generic 0x8000 107 108typedef enum arm_cond_code 109{ 110 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 111 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 112} 113arm_cc; 114 115extern arm_cc arm_current_cc; 116 117#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 118 119extern int arm_target_label; 120extern int arm_ccfsm_state; 121extern GTY(()) rtx arm_target_insn; 122/* Run-time compilation parameters selecting different hardware subsets. */ 123extern int target_flags; 124/* The floating point instruction architecture, can be 2 or 3 */ 125extern const char * target_fp_name; 126/* Define the information needed to generate branch insns. This is 127 stored from the compare operation. */ 128extern GTY(()) rtx arm_compare_op0; 129extern GTY(()) rtx arm_compare_op1; 130/* The label of the current constant pool. */ 131extern rtx pool_vector_label; 132/* Set to 1 when a return insn is output, this means that the epilogue 133 is not needed. */ 134extern int return_used_this_function; 135/* Used to produce AOF syntax assembler. */ 136extern GTY(()) rtx aof_pic_label; 137 138/* Just in case configure has failed to define anything. */ 139#ifndef TARGET_CPU_DEFAULT 140#define TARGET_CPU_DEFAULT TARGET_CPU_generic 141#endif 142 143/* If the configuration file doesn't specify the cpu, the subtarget may 144 override it. If it doesn't, then default to an ARM6. */ 145#if TARGET_CPU_DEFAULT == TARGET_CPU_generic 146#undef TARGET_CPU_DEFAULT 147 148#ifdef SUBTARGET_CPU_DEFAULT 149#define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT 150#else 151#define TARGET_CPU_DEFAULT TARGET_CPU_arm6 152#endif 153#endif 154 155#if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 156#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" 157#else 158#if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe 159#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" 160#else 161#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m 162#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" 163#else 164#if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi 165#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" 166#else 167#if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 168#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" 169#else 170#if TARGET_CPU_DEFAULT == TARGET_CPU_xscale 171#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" 172#else 173#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 174#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__" 175/* Set TARGET_DEFAULT to the default, but without soft-float. */ 176#ifdef TARGET_DEFAULT 177#undef TARGET_DEFAULT 178#define TARGET_DEFAULT \ 179 (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS | ARM_FLAG_APCS_FRAME) 180#endif 181#else 182#if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt 183#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__" 184#else 185#error Unrecognized value in TARGET_CPU_DEFAULT. 186#endif 187#endif 188#endif 189#endif 190#endif 191#endif 192#endif 193#endif 194 195#undef CPP_SPEC 196#define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ 197%{mapcs-32:%{mapcs-26: \ 198 %e-mapcs-26 and -mapcs-32 may not be used together}} \ 199%{msoft-float:%{mhard-float: \ 200 %e-msoft-float and -mhard_float may not be used together}} \ 201%{mbig-endian:%{mlittle-endian: \ 202 %e-mbig-endian and -mlittle-endian may not be used together}}" 203 204/* Set the architecture define -- if -march= is set, then it overrides 205 the -mcpu= setting. */ 206#define CPP_CPU_ARCH_SPEC "\ 207%{march=arm2:-D__ARM_ARCH_2__} \ 208%{march=arm250:-D__ARM_ARCH_2__} \ 209%{march=arm3:-D__ARM_ARCH_2__} \ 210%{march=arm6:-D__ARM_ARCH_3__} \ 211%{march=arm600:-D__ARM_ARCH_3__} \ 212%{march=arm610:-D__ARM_ARCH_3__} \ 213%{march=arm7:-D__ARM_ARCH_3__} \ 214%{march=arm700:-D__ARM_ARCH_3__} \ 215%{march=arm710:-D__ARM_ARCH_3__} \ 216%{march=arm720:-D__ARM_ARCH_3__} \ 217%{march=arm7100:-D__ARM_ARCH_3__} \ 218%{march=arm7500:-D__ARM_ARCH_3__} \ 219%{march=arm7500fe:-D__ARM_ARCH_3__} \ 220%{march=arm7m:-D__ARM_ARCH_3M__} \ 221%{march=arm7dm:-D__ARM_ARCH_3M__} \ 222%{march=arm7dmi:-D__ARM_ARCH_3M__} \ 223%{march=arm7tdmi:-D__ARM_ARCH_4T__} \ 224%{march=arm8:-D__ARM_ARCH_4__} \ 225%{march=arm810:-D__ARM_ARCH_4__} \ 226%{march=arm9:-D__ARM_ARCH_4T__} \ 227%{march=arm920:-D__ARM_ARCH_4__} \ 228%{march=arm920t:-D__ARM_ARCH_4T__} \ 229%{march=arm9tdmi:-D__ARM_ARCH_4T__} \ 230%{march=strongarm:-D__ARM_ARCH_4__} \ 231%{march=strongarm110:-D__ARM_ARCH_4__} \ 232%{march=strongarm1100:-D__ARM_ARCH_4__} \ 233%{march=xscale:-D__ARM_ARCH_5TE__} \ 234%{march=xscale:-D__XSCALE__} \ 235%{march=ep9312:-D__ARM_ARCH_4T__} \ 236%{march=ep9312:-D__MAVERICK__} \ 237%{march=armv2:-D__ARM_ARCH_2__} \ 238%{march=armv2a:-D__ARM_ARCH_2__} \ 239%{march=armv3:-D__ARM_ARCH_3__} \ 240%{march=armv3m:-D__ARM_ARCH_3M__} \ 241%{march=armv4:-D__ARM_ARCH_4__} \ 242%{march=armv4t:-D__ARM_ARCH_4T__} \ 243%{march=armv5:-D__ARM_ARCH_5__} \ 244%{march=armv5t:-D__ARM_ARCH_5T__} \ 245%{march=armv5e:-D__ARM_ARCH_5E__} \ 246%{march=armv5te:-D__ARM_ARCH_5TE__} \ 247%{!march=*: \ 248 %{mcpu=arm2:-D__ARM_ARCH_2__} \ 249 %{mcpu=arm250:-D__ARM_ARCH_2__} \ 250 %{mcpu=arm3:-D__ARM_ARCH_2__} \ 251 %{mcpu=arm6:-D__ARM_ARCH_3__} \ 252 %{mcpu=arm600:-D__ARM_ARCH_3__} \ 253 %{mcpu=arm610:-D__ARM_ARCH_3__} \ 254 %{mcpu=arm7:-D__ARM_ARCH_3__} \ 255 %{mcpu=arm700:-D__ARM_ARCH_3__} \ 256 %{mcpu=arm710:-D__ARM_ARCH_3__} \ 257 %{mcpu=arm720:-D__ARM_ARCH_3__} \ 258 %{mcpu=arm7100:-D__ARM_ARCH_3__} \ 259 %{mcpu=arm7500:-D__ARM_ARCH_3__} \ 260 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ 261 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ 262 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ 263 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ 264 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ 265 %{mcpu=arm8:-D__ARM_ARCH_4__} \ 266 %{mcpu=arm810:-D__ARM_ARCH_4__} \ 267 %{mcpu=arm9:-D__ARM_ARCH_4T__} \ 268 %{mcpu=arm920:-D__ARM_ARCH_4__} \ 269 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ 270 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ 271 %{mcpu=strongarm:-D__ARM_ARCH_4__} \ 272 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ 273 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ 274 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ 275 %{mcpu=xscale:-D__XSCALE__} \ 276 %{mcpu=ep9312:-D__ARM_ARCH_4T__} \ 277 %{mcpu=ep9312:-D__MAVERICK__} \ 278 %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \ 279 %{mcpu=iwmmxt:-D__XSCALE__} \ 280 %{mcpu=iwmmxt:-D__IWMMXT__} \ 281 %{!mcpu*:%(cpp_cpu_arch_default)}} \ 282" 283 284#ifndef CC1_SPEC 285#define CC1_SPEC "" 286#endif 287 288/* This macro defines names of additional specifications to put in the specs 289 that can be used in various specifications like CC1_SPEC. Its definition 290 is an initializer with a subgrouping for each command option. 291 292 Each subgrouping contains a string constant, that defines the 293 specification name, and a string constant that used by the GCC driver 294 program. 295 296 Do not define this macro if it does not need to do anything. */ 297#define EXTRA_SPECS \ 298 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ 299 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ 300 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 301 SUBTARGET_EXTRA_SPECS 302 303#ifndef SUBTARGET_EXTRA_SPECS 304#define SUBTARGET_EXTRA_SPECS 305#endif 306 307#ifndef SUBTARGET_CPP_SPEC 308#define SUBTARGET_CPP_SPEC "" 309#endif 310 311/* Run-time Target Specification. */ 312#ifndef TARGET_VERSION 313#define TARGET_VERSION fputs (" (ARM/generic)", stderr); 314#endif 315 316/* Nonzero if the function prologue (and epilogue) should obey 317 the ARM Procedure Call Standard. */ 318#define ARM_FLAG_APCS_FRAME (1 << 0) 319 320/* Nonzero if the function prologue should output the function name to enable 321 the post mortem debugger to print a backtrace (very useful on RISCOS, 322 unused on RISCiX). Specifying this flag also enables 323 -fno-omit-frame-pointer. 324 XXX Must still be implemented in the prologue. */ 325#define ARM_FLAG_POKE (1 << 1) 326 327/* Nonzero if floating point instructions are emulated by the FPE, in which 328 case instruction scheduling becomes very uninteresting. */ 329#define ARM_FLAG_FPE (1 << 2) 330 331/* Nonzero if destined for a processor in 32-bit program mode. Takes out bit 332 that assume restoration of the condition flags when returning from a 333 branch and link (ie a function). */ 334#define ARM_FLAG_APCS_32 (1 << 3) 335 336/* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ 337 338/* Nonzero if stack checking should be performed on entry to each function 339 which allocates temporary variables on the stack. */ 340#define ARM_FLAG_APCS_STACK (1 << 4) 341 342/* Nonzero if floating point parameters should be passed to functions in 343 floating point registers. */ 344#define ARM_FLAG_APCS_FLOAT (1 << 5) 345 346/* Nonzero if re-entrant, position independent code should be generated. 347 This is equivalent to -fpic. */ 348#define ARM_FLAG_APCS_REENT (1 << 6) 349 350/* Nonzero if the MMU will trap unaligned word accesses, so shorts must 351 be loaded using either LDRH or LDRB instructions. */ 352#define ARM_FLAG_MMU_TRAPS (1 << 7) 353 354/* Nonzero if all floating point instructions are missing (and there is no 355 emulator either). Generate function calls for all ops in this case. */ 356#define ARM_FLAG_SOFT_FLOAT (1 << 8) 357 358/* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ 359#define ARM_FLAG_BIG_END (1 << 9) 360 361/* Nonzero if we should compile for Thumb interworking. */ 362#define ARM_FLAG_INTERWORK (1 << 10) 363 364/* Nonzero if we should have little-endian words even when compiling for 365 big-endian (for backwards compatibility with older versions of GCC). */ 366#define ARM_FLAG_LITTLE_WORDS (1 << 11) 367 368/* Nonzero if we need to protect the prolog from scheduling */ 369#define ARM_FLAG_NO_SCHED_PRO (1 << 12) 370 371/* Nonzero if a call to abort should be generated if a noreturn 372 function tries to return. */ 373#define ARM_FLAG_ABORT_NORETURN (1 << 13) 374 375/* Nonzero if function prologues should not load the PIC register. */ 376#define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) 377 378/* Nonzero if all call instructions should be indirect. */ 379#define ARM_FLAG_LONG_CALLS (1 << 15) 380 381/* Nonzero means that the target ISA is the THUMB, not the ARM. */ 382#define ARM_FLAG_THUMB (1 << 16) 383 384/* Set if a TPCS style stack frame should be generated, for non-leaf 385 functions, even if they do not need one. */ 386#define THUMB_FLAG_BACKTRACE (1 << 17) 387 388/* Set if a TPCS style stack frame should be generated, for leaf 389 functions, even if they do not need one. */ 390#define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) 391 392/* Set if externally visible functions should assume that they 393 might be called in ARM mode, from a non-thumb aware code. */ 394#define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) 395 396/* Set if calls via function pointers should assume that their 397 destination is non-Thumb aware. */ 398#define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) 399 400/* Nonzero means target uses VFP FP. */ 401#define ARM_FLAG_VFP (1 << 21) 402 403/* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */ 404#define ARM_FLAG_ATPCS (1 << 22) 405 406/* Fix invalid Cirrus instruction combinations by inserting NOPs. */ 407#define CIRRUS_FIX_INVALID_INSNS (1 << 23) 408 409#define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) 410#define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) 411#define TARGET_FPE (target_flags & ARM_FLAG_FPE) 412#define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) 413#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) 414#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) 415#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) 416#define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS) 417#define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) 418#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) 419#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) 420#define TARGET_CIRRUS (arm_is_cirrus) 421#define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS) 422#define TARGET_IWMMXT (arm_arch_iwmmxt) 423#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM) 424#define TARGET_VFP (target_flags & ARM_FLAG_VFP) 425#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) 426#define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) 427#define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) 428#define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) 429#define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) 430#define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) 431#define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) 432#define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) 433#define TARGET_ARM (! TARGET_THUMB) 434#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 435#define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) 436#define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) 437#define TARGET_BACKTRACE (leaf_function_p () \ 438 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ 439 : (target_flags & THUMB_FLAG_BACKTRACE)) 440#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS) 441 442/* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ 443#ifndef SUBTARGET_SWITCHES 444#define SUBTARGET_SWITCHES 445#endif 446 447#define TARGET_SWITCHES \ 448{ \ 449 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ 450 {"apcs-frame", ARM_FLAG_APCS_FRAME, \ 451 N_("Generate APCS conformant stack frames") }, \ 452 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ 453 {"poke-function-name", ARM_FLAG_POKE, \ 454 N_("Store function names in object code") }, \ 455 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ 456 {"fpe", ARM_FLAG_FPE, "" }, \ 457 {"apcs-32", ARM_FLAG_APCS_32, \ 458 N_("Use the 32-bit version of the APCS") }, \ 459 {"apcs-26", -ARM_FLAG_APCS_32, ""}, \ 460 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ 461 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ 462 {"apcs-float", ARM_FLAG_APCS_FLOAT, \ 463 N_("Pass FP arguments in FP registers") }, \ 464 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ 465 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ 466 N_("Generate re-entrant, PIC code") }, \ 467 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ 468 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ 469 N_("The MMU will trap on unaligned accesses") }, \ 470 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ 471 {"soft-float", ARM_FLAG_SOFT_FLOAT, \ 472 N_("Use library calls to perform FP operations") }, \ 473 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ 474 N_("Use hardware floating point instructions") }, \ 475 {"big-endian", ARM_FLAG_BIG_END, \ 476 N_("Assume target CPU is configured as big endian") }, \ 477 {"little-endian", -ARM_FLAG_BIG_END, \ 478 N_("Assume target CPU is configured as little endian") }, \ 479 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ 480 N_("Assume big endian bytes, little endian words") }, \ 481 {"thumb-interwork", ARM_FLAG_INTERWORK, \ 482 N_("Support calls between Thumb and ARM instruction sets") }, \ 483 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ 484 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ 485 N_("Generate a call to abort if a noreturn function returns")}, \ 486 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ 487 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ 488 N_("Do not move instructions into a function's prologue") }, \ 489 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ 490 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ 491 N_("Do not load the PIC register in function prologues") }, \ 492 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ 493 {"long-calls", ARM_FLAG_LONG_CALLS, \ 494 N_("Generate call insns as indirect calls, if necessary") }, \ 495 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ 496 {"thumb", ARM_FLAG_THUMB, \ 497 N_("Compile for the Thumb not the ARM") }, \ 498 {"no-thumb", -ARM_FLAG_THUMB, "" }, \ 499 {"arm", -ARM_FLAG_THUMB, "" }, \ 500 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ 501 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ 502 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ 503 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ 504 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ 505 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ 506 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ 507 N_("Thumb: Assume non-static functions may be called from ARM code") }, \ 508 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ 509 "" }, \ 510 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ 511 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ 512 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ 513 "" }, \ 514 {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \ 515 N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \ 516 {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \ 517 N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\ 518 SUBTARGET_SWITCHES \ 519 {"", TARGET_DEFAULT, "" } \ 520} 521 522#define TARGET_OPTIONS \ 523{ \ 524 {"cpu=", & arm_select[0].string, \ 525 N_("Specify the name of the target CPU"), 0}, \ 526 {"arch=", & arm_select[1].string, \ 527 N_("Specify the name of the target architecture"), 0}, \ 528 {"tune=", & arm_select[2].string, "", 0}, \ 529 {"fpe=", & target_fp_name, "" , 0}, \ 530 {"fp=", & target_fp_name, \ 531 N_("Specify the version of the floating point emulator"), 0},\ 532 {"structure-size-boundary=", & structure_size_string, \ 533 N_("Specify the minimum bit alignment of structures"), 0}, \ 534 {"pic-register=", & arm_pic_register_string, \ 535 N_("Specify the register to be used for PIC addressing"), 0} \ 536} 537 538/* Support for a compile-time default CPU, et cetera. The rules are: 539 --with-arch is ignored if -march or -mcpu are specified. 540 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 541 by --with-arch. 542 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 543 by -march). 544 --with-float is ignored if -mhard-float or -msoft-float are 545 specified. */ 546#define OPTION_DEFAULT_SPECS \ 547 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 548 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 549 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 550 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } 551 552struct arm_cpu_select 553{ 554 const char * string; 555 const char * name; 556 const struct processors * processors; 557}; 558 559/* This is a magic array. If the user specifies a command line switch 560 which matches one of the entries in TARGET_OPTIONS then the corresponding 561 string pointer will be set to the value specified by the user. */ 562extern struct arm_cpu_select arm_select[]; 563 564enum prog_mode_type 565{ 566 prog_mode26, 567 prog_mode32 568}; 569 570/* Recast the program mode class to be the prog_mode attribute. */ 571#define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) 572 573extern enum prog_mode_type arm_prgmode; 574 575/* What sort of floating point unit do we have? Hardware or software. 576 If software, is it issue 2 or issue 3? */ 577enum fputype 578{ 579 /* Software floating point, FPA style double fmt. */ 580 FPUTYPE_SOFT_FPA, 581 /* Full FPA support. */ 582 FPUTYPE_FPA, 583 /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */ 584 FPUTYPE_FPA_EMU2, 585 /* Emulated FPA hardware, Issue 3 emulator. */ 586 FPUTYPE_FPA_EMU3, 587 /* Cirrus Maverick floating point co-processor. */ 588 FPUTYPE_MAVERICK 589}; 590 591/* Recast the floating point class to be the floating point attribute. */ 592#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune) 593 594/* What type of floating point to tune for */ 595extern enum fputype arm_fpu_tune; 596 597/* What type of floating point instructions are available */ 598extern enum fputype arm_fpu_arch; 599 600/* Default floating point architecture. Override in sub-target if 601 necessary. */ 602#ifndef FPUTYPE_DEFAULT 603#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2 604#endif 605 606#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 607#undef FPUTYPE_DEFAULT 608#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK 609#endif 610 611/* Nonzero if the processor has a fast multiply insn, and one that does 612 a 64-bit multiply of two 32-bit values. */ 613extern int arm_fast_multiply; 614 615/* Nonzero if this chip supports the ARM Architecture 4 extensions */ 616extern int arm_arch4; 617 618/* Nonzero if this chip supports the ARM Architecture 5 extensions */ 619extern int arm_arch5; 620 621/* Nonzero if this chip supports the ARM Architecture 5E extensions */ 622extern int arm_arch5e; 623 624/* Nonzero if this chip can benefit from load scheduling. */ 625extern int arm_ld_sched; 626 627/* Nonzero if generating thumb code. */ 628extern int thumb_code; 629 630/* Nonzero if this chip is a StrongARM. */ 631extern int arm_is_strong; 632 633/* Nonzero if this chip is a Cirrus variant. */ 634extern int arm_is_cirrus; 635 636/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 637extern int arm_arch_iwmmxt; 638 639/* Nonzero if this chip is an XScale. */ 640extern int arm_arch_xscale; 641 642/* Nonzero if tuning for XScale */ 643extern int arm_tune_xscale; 644 645/* Nonzero if this chip is an ARM6 or an ARM7. */ 646extern int arm_is_6_or_7; 647 648#ifndef TARGET_DEFAULT 649#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) 650#endif 651 652/* The frame pointer register used in gcc has nothing to do with debugging; 653 that is controlled by the APCS-FRAME option. */ 654#define CAN_DEBUG_WITHOUT_FP 655 656#undef TARGET_MEM_FUNCTIONS 657#define TARGET_MEM_FUNCTIONS 1 658 659#define OVERRIDE_OPTIONS arm_override_options () 660 661/* Nonzero if PIC code requires explicit qualifiers to generate 662 PLT and GOT relocs rather than the assembler doing so implicitly. 663 Subtargets can override these if required. */ 664#ifndef NEED_GOT_RELOC 665#define NEED_GOT_RELOC 0 666#endif 667#ifndef NEED_PLT_RELOC 668#define NEED_PLT_RELOC 0 669#endif 670 671/* Nonzero if we need to refer to the GOT with a PC-relative 672 offset. In other words, generate 673 674 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 675 676 rather than 677 678 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 679 680 The default is true, which matches NetBSD. Subtargets can 681 override this if required. */ 682#ifndef GOT_PCREL 683#define GOT_PCREL 1 684#endif 685 686/* Target machine storage Layout. */ 687 688 689/* Define this macro if it is advisable to hold scalars in registers 690 in a wider mode than that declared by the program. In such cases, 691 the value is constrained to be within the bounds of the declared 692 type, but kept valid in the wider mode. The signedness of the 693 extension may differ from that of the type. */ 694 695/* It is far faster to zero extend chars than to sign extend them */ 696 697#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 698 if (GET_MODE_CLASS (MODE) == MODE_INT \ 699 && GET_MODE_SIZE (MODE) < 4) \ 700 { \ 701 if (MODE == QImode) \ 702 UNSIGNEDP = 1; \ 703 else if (MODE == HImode) \ 704 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ 705 (MODE) = SImode; \ 706 } 707 708/* Define this macro if the promotion described by `PROMOTE_MODE' 709 should also be done for outgoing function arguments. */ 710/* This is required to ensure that push insns always push a word. */ 711#define PROMOTE_FUNCTION_ARGS 712 713/* Define this if most significant bit is lowest numbered 714 in instructions that operate on numbered bit-fields. */ 715#define BITS_BIG_ENDIAN 0 716 717/* Define this if most significant byte of a word is the lowest numbered. 718 Most ARM processors are run in little endian mode, so that is the default. 719 If you want to have it run-time selectable, change the definition in a 720 cover file to be TARGET_BIG_ENDIAN. */ 721#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 722 723/* Define this if most significant word of a multiword number is the lowest 724 numbered. 725 This is always false, even when in big-endian mode. */ 726#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 727 728/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 729 on processor pre-defineds when compiling libgcc2.c. */ 730#if defined(__ARMEB__) && !defined(__ARMWEL__) 731#define LIBGCC2_WORDS_BIG_ENDIAN 1 732#else 733#define LIBGCC2_WORDS_BIG_ENDIAN 0 734#endif 735 736/* Define this if most significant word of doubles is the lowest numbered. 737 The rules are different based on whether or not we use FPA-format, 738 VFP-format or some other floating point co-processor's format doubles. */ 739#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 740 741#define UNITS_PER_WORD 4 742 743#define PARM_BOUNDARY 32 744 745#define IWMMXT_ALIGNMENT 64 746 747#define STACK_BOUNDARY 32 748 749#define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32) 750 751#define FUNCTION_BOUNDARY 32 752 753/* The lowest bit is used to indicate Thumb-mode functions, so the 754 vbit must go into the delta field of pointers to member 755 functions. */ 756#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 757 758#define EMPTY_FIELD_BOUNDARY 32 759 760#define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32) 761 762#define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \ 763 (TARGET_REALLY_IWMMXT \ 764 && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode))) 765 766/* XXX Blah -- this macro is used directly by libobjc. Since it 767 supports no vector modes, cut out the complexity and fall back 768 on BIGGEST_FIELD_ALIGNMENT. */ 769#ifdef IN_TARGET_LIBS 770#define BIGGEST_FIELD_ALIGNMENT 64 771#else 772/* An expression for the alignment of a structure field FIELD if the 773 alignment computed in the usual way is COMPUTED. GCC uses this 774 value instead of the value in `BIGGEST_ALIGNMENT' or 775 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ 776#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 777 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \ 778 ? IWMMXT_ALIGNMENT \ 779 : (COMPUTED)) 780#endif 781 782/* If defined, a C expression to compute the alignment for a static variable. 783 TYPE is the data type, and ALIGN is the alignment that the object 784 would ordinarily have. The value of this macro is used instead of that 785 alignment to align the object. 786 787 If this macro is not defined, then ALIGN is used. */ 788#define DATA_ALIGNMENT(TYPE, ALIGN) \ 789 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN) 790 791/* If defined, a C expression to compute the alignment for a 792 variables in the local store. TYPE is the data type, and 793 BASIC-ALIGN is the alignment that the object would ordinarily 794 have. The value of this macro is used instead of that alignment 795 to align the object. 796 797 If this macro is not defined, then BASIC-ALIGN is used. */ 798#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 799 (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN) 800 801/* Make strings word-aligned so strcpy from constants will be faster. */ 802#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 803 804#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 805 ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \ 806 (TREE_CODE (EXP) == STRING_CST \ 807 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 808 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 809 810/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 811 value set in previous versions of this toolchain was 8, which produces more 812 compact structures. The command line option -mstructure_size_boundary=<n> 813 can be used to change this value. For compatibility with the ARM SDK 814 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 815 0020D) page 2-20 says "Structures are aligned on word boundaries". */ 816#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 817extern int arm_structure_size_boundary; 818 819/* This is the value used to initialize arm_structure_size_boundary. If a 820 particular arm target wants to change the default value it should change 821 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 822 for an example of this. */ 823#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 824#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 825#endif 826 827/* Used when parsing command line option -mstructure_size_boundary. */ 828extern const char * structure_size_string; 829 830/* Nonzero if move instructions will actually fail to work 831 when given unaligned data. */ 832#define STRICT_ALIGNMENT 1 833 834/* Standard register usage. */ 835 836/* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 837 (S - saved over call). 838 839 r0 * argument word/integer result 840 r1-r3 argument word 841 842 r4-r8 S register variable 843 r9 S (rfp) register variable (real frame pointer) 844 845 r10 F S (sl) stack limit (used by -mapcs-stack-check) 846 r11 F S (fp) argument pointer 847 r12 (ip) temp workspace 848 r13 F S (sp) lower end of current stack frame 849 r14 (lr) link address/workspace 850 r15 F (pc) program counter 851 852 f0 floating point result 853 f1-f3 floating point scratch 854 855 f4-f7 S floating point variable 856 857 cc This is NOT a real register, but is used internally 858 to represent things that use or set the condition 859 codes. 860 sfp This isn't either. It is used during rtl generation 861 since the offset between the frame pointer and the 862 auto's isn't known until after register allocation. 863 afp Nor this, we only need this because of non-local 864 goto. Without it fp appears to be used and the 865 elimination code won't get rid of sfp. It tracks 866 fp exactly at all times. 867 868 *: See CONDITIONAL_REGISTER_USAGE */ 869 870/* 871 mvf0 Cirrus floating point result 872 mvf1-mvf3 Cirrus floating point scratch 873 mvf4-mvf15 S Cirrus floating point variable. */ 874 875/* The stack backtrace structure is as follows: 876 fp points to here: | save code pointer | [fp] 877 | return link value | [fp, #-4] 878 | return sp value | [fp, #-8] 879 | return fp value | [fp, #-12] 880 [| saved r10 value |] 881 [| saved r9 value |] 882 [| saved r8 value |] 883 [| saved r7 value |] 884 [| saved r6 value |] 885 [| saved r5 value |] 886 [| saved r4 value |] 887 [| saved r3 value |] 888 [| saved r2 value |] 889 [| saved r1 value |] 890 [| saved r0 value |] 891 [| saved f7 value |] three words 892 [| saved f6 value |] three words 893 [| saved f5 value |] three words 894 [| saved f4 value |] three words 895 r0-r3 are not normally saved in a C function. */ 896 897/* 1 for registers that have pervasive standard uses 898 and are not available for the register allocator. */ 899#define FIXED_REGISTERS \ 900{ \ 901 0,0,0,0,0,0,0,0, \ 902 0,0,0,0,0,1,0,1, \ 903 0,0,0,0,0,0,0,0, \ 904 1,1,1, \ 905 1,1,1,1,1,1,1,1, \ 906 1,1,1,1,1,1,1,1, \ 907 1,1,1,1,1,1,1,1, \ 908 1,1,1,1,1,1,1,1, \ 909 1,1,1,1 \ 910} 911 912/* 1 for registers not available across function calls. 913 These must include the FIXED_REGISTERS and also any 914 registers that can be used without being saved. 915 The latter must include the registers where values are returned 916 and the register where structure-value addresses are passed. 917 Aside from that, you can include as many other registers as you like. 918 The CC is not preserved over function calls on the ARM 6, so it is 919 easier to assume this for all. SFP is preserved, since FP is. */ 920#define CALL_USED_REGISTERS \ 921{ \ 922 1,1,1,1,0,0,0,0, \ 923 0,0,0,0,1,1,1,1, \ 924 1,1,1,1,0,0,0,0, \ 925 1,1,1, \ 926 1,1,1,1,1,1,1,1, \ 927 1,1,1,1,1,1,1,1, \ 928 1,1,1,1,1,1,1,1, \ 929 1,1,1,1,1,1,1,1, \ 930 1,1,1,1 \ 931} 932 933#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 934#define SUBTARGET_CONDITIONAL_REGISTER_USAGE 935#endif 936 937#define CONDITIONAL_REGISTER_USAGE \ 938{ \ 939 int regno; \ 940 \ 941 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ 942 { \ 943 for (regno = FIRST_ARM_FP_REGNUM; \ 944 regno <= LAST_ARM_FP_REGNUM; ++regno) \ 945 fixed_regs[regno] = call_used_regs[regno] = 1; \ 946 } \ 947 \ 948 if (TARGET_THUMB && optimize_size) \ 949 { \ 950 /* When optimizing for size, it's better not to use \ 951 the HI regs, because of the overhead of stacking \ 952 them. */ \ 953 for (regno = FIRST_HI_REGNUM; \ 954 regno <= LAST_HI_REGNUM; ++regno) \ 955 fixed_regs[regno] = call_used_regs[regno] = 1; \ 956 } \ 957 \ 958 /* The link register can be clobbered by any branch insn, \ 959 but we have no way to track that at present, so mark \ 960 it as unavailable. */ \ 961 if (TARGET_THUMB) \ 962 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ 963 \ 964 if (TARGET_CIRRUS) \ 965 { \ 966 for (regno = FIRST_ARM_FP_REGNUM; \ 967 regno <= LAST_ARM_FP_REGNUM; ++ regno) \ 968 fixed_regs[regno] = call_used_regs[regno] = 1; \ 969 for (regno = FIRST_CIRRUS_FP_REGNUM; \ 970 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ 971 { \ 972 fixed_regs[regno] = 0; \ 973 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ 974 } \ 975 } \ 976 \ 977 if (TARGET_REALLY_IWMMXT) \ 978 { \ 979 regno = FIRST_IWMMXT_GR_REGNUM; \ 980 /* The 2002/10/09 revision of the XScale ABI has wCG0 \ 981 and wCG1 as call-preserved registers. The 2002/11/21 \ 982 revision changed this so that all wCG registers are \ 983 scratch registers. */ \ 984 for (regno = FIRST_IWMMXT_GR_REGNUM; \ 985 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ 986 fixed_regs[regno] = call_used_regs[regno] = 0; \ 987 /* The XScale ABI has wR0 - wR9 as scratch registers, \ 988 the rest as call-preserved registers. */ \ 989 for (regno = FIRST_IWMMXT_REGNUM; \ 990 regno <= LAST_IWMMXT_REGNUM; ++ regno) \ 991 { \ 992 fixed_regs[regno] = 0; \ 993 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ 994 } \ 995 } \ 996 \ 997 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 998 { \ 999 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 1000 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 1001 } \ 1002 else if (TARGET_APCS_STACK) \ 1003 { \ 1004 fixed_regs[10] = 1; \ 1005 call_used_regs[10] = 1; \ 1006 } \ 1007 if (TARGET_APCS_FRAME) \ 1008 { \ 1009 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 1010 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 1011 } \ 1012 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 1013} 1014 1015/* These are a couple of extensions to the formats accepted 1016 by asm_fprintf: 1017 %@ prints out ASM_COMMENT_START 1018 %r prints out REGISTER_PREFIX reg_names[arg] */ 1019#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 1020 case '@': \ 1021 fputs (ASM_COMMENT_START, FILE); \ 1022 break; \ 1023 \ 1024 case 'r': \ 1025 fputs (REGISTER_PREFIX, FILE); \ 1026 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 1027 break; 1028 1029/* Round X up to the nearest word. */ 1030#define ROUND_UP_WORD(X) (((X) + 3) & ~3) 1031 1032/* Convert fron bytes to ints. */ 1033#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1034 1035/* The number of (integer) registers required to hold a quantity of type MODE. */ 1036#define ARM_NUM_REGS(MODE) \ 1037 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 1038 1039/* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 1040#define ARM_NUM_REGS2(MODE, TYPE) \ 1041 ARM_NUM_INTS ((MODE) == BLKmode ? \ 1042 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 1043 1044/* The number of (integer) argument register available. */ 1045#define NUM_ARG_REGS 4 1046 1047/* Return the register number of the N'th (integer) argument. */ 1048#define ARG_REGISTER(N) (N - 1) 1049 1050#if 0 /* FIXME: The ARM backend has special code to handle structure 1051 returns, and will reserve its own hidden first argument. So 1052 if this macro is enabled a *second* hidden argument will be 1053 reserved, which will break binary compatibility with old 1054 toolchains and also thunk handling. One day this should be 1055 fixed. */ 1056/* RTX for structure returns. NULL means use a hidden first argument. */ 1057#define STRUCT_VALUE 0 1058#else 1059/* Register in which address to store a structure value 1060 is passed to a function. */ 1061#define STRUCT_VALUE_REGNUM ARG_REGISTER (1) 1062#endif 1063 1064/* Specify the registers used for certain standard purposes. 1065 The values of these macros are register numbers. */ 1066 1067/* The number of the last argument register. */ 1068#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 1069 1070/* The numbers of the Thumb register ranges. */ 1071#define FIRST_LO_REGNUM 0 1072#define LAST_LO_REGNUM 7 1073#define FIRST_HI_REGNUM 8 1074#define LAST_HI_REGNUM 11 1075 1076/* The register that holds the return address in exception handlers. */ 1077#define EXCEPTION_LR_REGNUM 2 1078 1079/* The native (Norcroft) Pascal compiler for the ARM passes the static chain 1080 as an invisible last argument (possible since varargs don't exist in 1081 Pascal), so the following is not true. */ 1082#define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) 1083 1084/* Define this to be where the real frame pointer is if it is not possible to 1085 work out the offset between the frame pointer and the automatic variables 1086 until after register allocation has taken place. FRAME_POINTER_REGNUM 1087 should point to a special register that we will make sure is eliminated. 1088 1089 For the Thumb we have another problem. The TPCS defines the frame pointer 1090 as r11, and GCC believes that it is always possible to use the frame pointer 1091 as base register for addressing purposes. (See comments in 1092 find_reloads_address()). But - the Thumb does not allow high registers, 1093 including r11, to be used as base address registers. Hence our problem. 1094 1095 The solution used here, and in the old thumb port is to use r7 instead of 1096 r11 as the hard frame pointer and to have special code to generate 1097 backtrace structures on the stack (if required to do so via a command line 1098 option) using r11. This is the only 'user visible' use of r11 as a frame 1099 pointer. */ 1100#define ARM_HARD_FRAME_POINTER_REGNUM 11 1101#define THUMB_HARD_FRAME_POINTER_REGNUM 7 1102 1103#define HARD_FRAME_POINTER_REGNUM \ 1104 (TARGET_ARM \ 1105 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1106 : THUMB_HARD_FRAME_POINTER_REGNUM) 1107 1108#define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1109 1110/* Register to use for pushing function arguments. */ 1111#define STACK_POINTER_REGNUM SP_REGNUM 1112 1113/* ARM floating pointer registers. */ 1114#define FIRST_ARM_FP_REGNUM 16 1115#define LAST_ARM_FP_REGNUM 23 1116 1117#define FIRST_IWMMXT_GR_REGNUM 43 1118#define LAST_IWMMXT_GR_REGNUM 46 1119#define FIRST_IWMMXT_REGNUM 47 1120#define LAST_IWMMXT_REGNUM 62 1121#define IS_IWMMXT_REGNUM(REGNUM) \ 1122 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1123#define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1124 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1125 1126/* Base register for access to local variables of the function. */ 1127#define FRAME_POINTER_REGNUM 25 1128 1129/* Base register for access to arguments of the function. */ 1130#define ARG_POINTER_REGNUM 26 1131 1132#define FIRST_CIRRUS_FP_REGNUM 27 1133#define LAST_CIRRUS_FP_REGNUM 42 1134#define IS_CIRRUS_REGNUM(REGNUM) \ 1135 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 1136 1137/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 1138/* + 16 Cirrus registers take us up to 43. */ 1139/* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1140#define FIRST_PSEUDO_REGISTER 63 1141 1142/* Value should be nonzero if functions must have frame pointers. 1143 Zero means the frame pointer need not be set up (and parms may be accessed 1144 via the stack pointer) in functions that seem suitable. 1145 If we have to have a frame pointer we might as well make use of it. 1146 APCS says that the frame pointer does not need to be pushed in leaf 1147 functions, or simple tail call functions. */ 1148#define FRAME_POINTER_REQUIRED \ 1149 (current_function_has_nonlocal_label \ 1150 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) 1151 1152/* Return number of consecutive hard regs needed starting at reg REGNO 1153 to hold something of mode MODE. 1154 This is ordinarily the length in words of a value of mode MODE 1155 but can be less for certain modes in special long registers. 1156 1157 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 1158 mode. */ 1159#define HARD_REGNO_NREGS(REGNO, MODE) \ 1160 ((TARGET_ARM \ 1161 && REGNO >= FIRST_ARM_FP_REGNUM \ 1162 && REGNO != FRAME_POINTER_REGNUM \ 1163 && REGNO != ARG_POINTER_REGNUM) \ 1164 ? 1 : ARM_NUM_REGS (MODE)) 1165 1166/* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1167#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1168 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1169 1170/* Value is 1 if it is a good idea to tie two pseudo registers 1171 when one has mode MODE1 and one has mode MODE2. 1172 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1173 for any hard reg, then this must be 0 for correct output. */ 1174#define MODES_TIEABLE_P(MODE1, MODE2) \ 1175 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1176 1177#define VECTOR_MODE_SUPPORTED_P(MODE) \ 1178 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode) 1179 1180#define VALID_IWMMXT_REG_MODE(MODE) \ 1181 (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode) 1182 1183/* The order in which register should be allocated. It is good to use ip 1184 since no saving is required (though calls clobber it) and it never contains 1185 function parameters. It is quite good to use lr since other calls may 1186 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1187 least likely to contain a function parameter; in addition results are 1188 returned in r0. */ 1189#define REG_ALLOC_ORDER \ 1190{ \ 1191 3, 2, 1, 0, 12, 14, 4, 5, \ 1192 6, 7, 8, 10, 9, 11, 13, 15, \ 1193 16, 17, 18, 19, 20, 21, 22, 23, \ 1194 27, 28, 29, 30, 31, 32, 33, 34, \ 1195 35, 36, 37, 38, 39, 40, 41, 42, \ 1196 43, 44, 45, 46, 47, 48, 49, 50, \ 1197 51, 52, 53, 54, 55, 56, 57, 58, \ 1198 59, 60, 61, 62, \ 1199 24, 25, 26 \ 1200} 1201 1202/* Interrupt functions can only use registers that have already been 1203 saved by the prologue, even if they would normally be 1204 call-clobbered. */ 1205#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1206 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1207 regs_ever_live[DST]) 1208 1209/* Register and constant classes. */ 1210 1211/* Register classes: used to be simple, just all ARM regs or all FPA regs 1212 Now that the Thumb is involved it has become more complicated. */ 1213enum reg_class 1214{ 1215 NO_REGS, 1216 FPA_REGS, 1217 CIRRUS_REGS, 1218 IWMMXT_GR_REGS, 1219 IWMMXT_REGS, 1220 LO_REGS, 1221 STACK_REG, 1222 BASE_REGS, 1223 HI_REGS, 1224 CC_REG, 1225 GENERAL_REGS, 1226 ALL_REGS, 1227 LIM_REG_CLASSES 1228}; 1229 1230#define N_REG_CLASSES (int) LIM_REG_CLASSES 1231 1232/* Give names of register classes as strings for dump file. */ 1233#define REG_CLASS_NAMES \ 1234{ \ 1235 "NO_REGS", \ 1236 "FPA_REGS", \ 1237 "CIRRUS_REGS", \ 1238 "IWMMXT_GR_REGS", \ 1239 "IWMMXT_REGS", \ 1240 "LO_REGS", \ 1241 "STACK_REG", \ 1242 "BASE_REGS", \ 1243 "HI_REGS", \ 1244 "CC_REG", \ 1245 "GENERAL_REGS", \ 1246 "ALL_REGS", \ 1247} 1248 1249/* Define which registers fit in which classes. 1250 This is an initializer for a vector of HARD_REG_SET 1251 of length N_REG_CLASSES. */ 1252#define REG_CLASS_CONTENTS \ 1253{ \ 1254 { 0x00000000, 0x0 }, /* NO_REGS */ \ 1255 { 0x00FF0000, 0x0 }, /* FPA_REGS */ \ 1256 { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \ 1257 { 0x00000000, 0x00007800 }, /* IWMMXT_GR_REGS */\ 1258 { 0x00000000, 0x7FFF8000 }, /* IWMMXT_REGS */ \ 1259 { 0x000000FF, 0x0 }, /* LO_REGS */ \ 1260 { 0x00002000, 0x0 }, /* STACK_REG */ \ 1261 { 0x000020FF, 0x0 }, /* BASE_REGS */ \ 1262 { 0x0000FF00, 0x0 }, /* HI_REGS */ \ 1263 { 0x01000000, 0x0 }, /* CC_REG */ \ 1264 { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\ 1265 { 0xFAFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 1266} 1267 1268/* The same information, inverted: 1269 Return the class number of the smallest class containing 1270 reg number REGNO. This could be a conditional expression 1271 or could index an array. */ 1272#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1273 1274/* FPA registers can't do dubreg as all values are reformatted to internal 1275 precision. */ 1276#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1277 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1278 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0) 1279 1280/* The class value for index registers, and the one for base regs. */ 1281#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) 1282#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) 1283 1284/* For the Thumb the high registers cannot be used as base registers 1285 when addressing quantities in QI or HI mode; if we don't know the 1286 mode, then we must be conservative. After reload we must also be 1287 conservative, since we can't support SP+reg addressing, and we 1288 can't fix up any bad substitutions. */ 1289#define MODE_BASE_REG_CLASS(MODE) \ 1290 (TARGET_ARM ? GENERAL_REGS : \ 1291 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS)) 1292 1293/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1294 registers explicitly used in the rtl to be used as spill registers 1295 but prevents the compiler from extending the lifetime of these 1296 registers. */ 1297#define SMALL_REGISTER_CLASSES TARGET_THUMB 1298 1299/* Get reg_class from a letter such as appears in the machine description. 1300 We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the 1301 ARM, but several more letters for the Thumb. */ 1302#define REG_CLASS_FROM_LETTER(C) \ 1303 ( (C) == 'f' ? FPA_REGS \ 1304 : (C) == 'v' ? CIRRUS_REGS \ 1305 : (C) == 'y' ? IWMMXT_REGS \ 1306 : (C) == 'z' ? IWMMXT_GR_REGS \ 1307 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ 1308 : TARGET_ARM ? NO_REGS \ 1309 : (C) == 'h' ? HI_REGS \ 1310 : (C) == 'b' ? BASE_REGS \ 1311 : (C) == 'k' ? STACK_REG \ 1312 : (C) == 'c' ? CC_REG \ 1313 : NO_REGS) 1314 1315/* The letters I, J, K, L and M in a register constraint string 1316 can be used to stand for particular ranges of immediate operands. 1317 This macro defines what the ranges are. 1318 C is the letter, and VALUE is a constant value. 1319 Return 1 if VALUE is in the range specified by C. 1320 I: immediate arithmetic operand (i.e. 8 bits shifted as required). 1321 J: valid indexing constants. 1322 K: ~value ok in rhs argument of data operand. 1323 L: -value ok in rhs argument of data operand. 1324 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ 1325#define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ 1326 ((C) == 'I' ? const_ok_for_arm (VALUE) : \ 1327 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ 1328 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ 1329 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ 1330 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ 1331 || (((VALUE) & ((VALUE) - 1)) == 0)) \ 1332 : 0) 1333 1334#define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ 1335 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ 1336 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ 1337 (C) == 'K' ? thumb_shiftable_const (VAL) : \ 1338 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ 1339 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ 1340 && ((VAL) & 3) == 0) : \ 1341 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ 1342 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ 1343 : 0) 1344 1345#define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1346 (TARGET_ARM ? \ 1347 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) 1348 1349/* Constant letter 'G' for the FPA immediate constants. 1350 'H' means the same constant negated. */ 1351#define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ 1352 ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \ 1353 (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0) 1354 1355#define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ 1356 (TARGET_ARM ? \ 1357 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) 1358 1359/* For the ARM, `Q' means that this is a memory operand that is just 1360 an offset from a register. 1361 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL 1362 address. This means that the symbol is in the text segment and can be 1363 accessed without using a load. */ 1364 1365#define EXTRA_CONSTRAINT_ARM(OP, C) \ 1366 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ 1367 (C) == 'R' ? (GET_CODE (OP) == MEM \ 1368 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 1369 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ 1370 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \ 1371 (C) == 'T' ? cirrus_memory_offset (OP) : \ 1372 0) 1373 1374#define EXTRA_CONSTRAINT_THUMB(X, C) \ 1375 ((C) == 'Q' ? (GET_CODE (X) == MEM \ 1376 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) 1377 1378#define EXTRA_CONSTRAINT(X, C) \ 1379 (TARGET_ARM ? \ 1380 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) 1381 1382/* Given an rtx X being reloaded into a reg required to be 1383 in class CLASS, return the class of reg to actually use. 1384 In general this is just CLASS, but for the Thumb we prefer 1385 a LO_REGS class or a subset. */ 1386#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1387 (TARGET_ARM ? (CLASS) : \ 1388 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) 1389 1390/* Must leave BASE_REGS reloads alone */ 1391#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1392 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1393 ? ((true_regnum (X) == -1 ? LO_REGS \ 1394 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1395 : NO_REGS)) \ 1396 : NO_REGS) 1397 1398#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1399 ((CLASS) != LO_REGS \ 1400 ? ((true_regnum (X) == -1 ? LO_REGS \ 1401 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1402 : NO_REGS)) \ 1403 : NO_REGS) 1404 1405/* Return the register class of a scratch register needed to copy IN into 1406 or out of a register in CLASS in MODE. If it can be done directly, 1407 NO_REGS is returned. */ 1408#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1409 (TARGET_ARM ? \ 1410 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1411 ? GENERAL_REGS : NO_REGS) \ 1412 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1413 1414/* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1415#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1416 /* Cannot load constants into Cirrus registers. */ \ 1417 ((TARGET_CIRRUS \ 1418 && (CLASS) == CIRRUS_REGS \ 1419 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1420 ? GENERAL_REGS : \ 1421 (TARGET_ARM ? \ 1422 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1423 && CONSTANT_P (X)) \ 1424 ? GENERAL_REGS : \ 1425 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ 1426 && (GET_CODE (X) == MEM \ 1427 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1428 && true_regnum (X) == -1))) \ 1429 ? GENERAL_REGS : NO_REGS) \ 1430 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1431 1432/* Try a machine-dependent way of reloading an illegitimate address 1433 operand. If we find one, push the reload and jump to WIN. This 1434 macro is used in only one place: `find_reloads_address' in reload.c. 1435 1436 For the ARM, we wish to handle large displacements off a base 1437 register by splitting the addend across a MOV and the mem insn. 1438 This can cut the number of reloads needed. */ 1439#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1440 do \ 1441 { \ 1442 if (GET_CODE (X) == PLUS \ 1443 && GET_CODE (XEXP (X, 0)) == REG \ 1444 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 1445 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 1446 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1447 { \ 1448 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1449 HOST_WIDE_INT low, high; \ 1450 \ 1451 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ 1452 low = ((val & 0xf) ^ 0x8) - 0x8; \ 1453 else if (TARGET_CIRRUS) \ 1454 /* Need to be careful, -256 is not a valid offset. */ \ 1455 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1456 else if (MODE == SImode \ 1457 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 1458 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 1459 /* Need to be careful, -4096 is not a valid offset. */ \ 1460 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 1461 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 1462 /* Need to be careful, -256 is not a valid offset. */ \ 1463 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1464 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1465 && TARGET_HARD_FLOAT) \ 1466 /* Need to be careful, -1024 is not a valid offset. */ \ 1467 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 1468 else \ 1469 break; \ 1470 \ 1471 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 1472 ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 1473 - (unsigned HOST_WIDE_INT) 0x80000000); \ 1474 /* Check for overflow or zero */ \ 1475 if (low == 0 || high == 0 || (high + low != val)) \ 1476 break; \ 1477 \ 1478 /* Reload the high part into a base reg; leave the low part \ 1479 in the mem. */ \ 1480 X = gen_rtx_PLUS (GET_MODE (X), \ 1481 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 1482 GEN_INT (high)), \ 1483 GEN_INT (low)); \ 1484 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1485 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 1486 VOIDmode, 0, 0, OPNUM, TYPE); \ 1487 goto WIN; \ 1488 } \ 1489 } \ 1490 while (0) 1491 1492/* XXX If an HImode FP+large_offset address is converted to an HImode 1493 SP+large_offset address, then reload won't know how to fix it. It sees 1494 only that SP isn't valid for HImode, and so reloads the SP into an index 1495 register, but the resulting address is still invalid because the offset 1496 is too big. We fix it here instead by reloading the entire address. */ 1497/* We could probably achieve better results by defining PROMOTE_MODE to help 1498 cope with the variances between the Thumb's signed and unsigned byte and 1499 halfword load instructions. */ 1500#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1501{ \ 1502 if (GET_CODE (X) == PLUS \ 1503 && GET_MODE_SIZE (MODE) < 4 \ 1504 && GET_CODE (XEXP (X, 0)) == REG \ 1505 && XEXP (X, 0) == stack_pointer_rtx \ 1506 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1507 && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \ 1508 { \ 1509 rtx orig_X = X; \ 1510 X = copy_rtx (X); \ 1511 push_reload (orig_X, NULL_RTX, &X, NULL, \ 1512 MODE_BASE_REG_CLASS (MODE), \ 1513 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ 1514 goto WIN; \ 1515 } \ 1516} 1517 1518#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1519 if (TARGET_ARM) \ 1520 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1521 else \ 1522 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1523 1524/* Return the maximum number of consecutive registers 1525 needed to represent mode MODE in a register of class CLASS. 1526 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 1527#define CLASS_MAX_NREGS(CLASS, MODE) \ 1528 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 1529 1530/* If defined, gives a class of registers that cannot be used as the 1531 operand of a SUBREG that changes the mode of the object illegally. */ 1532 1533/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */ 1534#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1535 (TARGET_ARM ? \ 1536 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1537 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1538 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1539 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1540 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1541 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1542 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1543 2) \ 1544 : \ 1545 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1546 1547/* Stack layout; function entry, exit and calling. */ 1548 1549/* Define this if pushing a word on the stack 1550 makes the stack pointer a smaller address. */ 1551#define STACK_GROWS_DOWNWARD 1 1552 1553/* Define this if the nominal address of the stack frame 1554 is at the high-address end of the local variables; 1555 that is, each additional local variable allocated 1556 goes at a more negative offset in the frame. */ 1557#define FRAME_GROWS_DOWNWARD 1 1558 1559/* Offset within stack frame to start allocating local variables at. 1560 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1561 first local allocated. Otherwise, it is the offset to the BEGINNING 1562 of the first local allocated. */ 1563#define STARTING_FRAME_OFFSET 0 1564 1565/* If we generate an insn to push BYTES bytes, 1566 this says how many the stack pointer really advances by. */ 1567/* The push insns do not do this rounding implicitly. 1568 So don't define this. */ 1569/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1570 1571/* Define this if the maximum size of all the outgoing args is to be 1572 accumulated and pushed during the prologue. The amount can be 1573 found in the variable current_function_outgoing_args_size. */ 1574#define ACCUMULATE_OUTGOING_ARGS 1 1575 1576/* Offset of first parameter from the argument pointer register value. */ 1577#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1578 1579/* Value is the number of byte of arguments automatically 1580 popped when returning from a subroutine call. 1581 FUNDECL is the declaration node of the function (as a tree), 1582 FUNTYPE is the data type of the function (as a tree), 1583 or for a library call it is an identifier node for the subroutine name. 1584 SIZE is the number of bytes of arguments passed on the stack. 1585 1586 On the ARM, the caller does not pop any of its arguments that were passed 1587 on the stack. */ 1588#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 1589 1590/* Define how to find the value returned by a library function 1591 assuming the value has mode MODE. */ 1592#define LIBCALL_VALUE(MODE) \ 1593 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1594 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ 1595 : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1596 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1597 : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \ 1598 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 1599 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1600 1601/* Define how to find the value returned by a function. 1602 VALTYPE is the data type of the value (as a tree). 1603 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1604 otherwise, FUNC is 0. */ 1605#define FUNCTION_VALUE(VALTYPE, FUNC) \ 1606 LIBCALL_VALUE (TYPE_MODE (VALTYPE)) 1607 1608/* 1 if N is a possible register number for a function value. 1609 On the ARM, only r0 and f0 can return results. */ 1610/* On a Cirrus chip, mvf0 can return results. */ 1611#define FUNCTION_VALUE_REGNO_P(REGNO) \ 1612 ((REGNO) == ARG_REGISTER (1) \ 1613 || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \ 1614 || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \ 1615 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) 1616 1617/* How large values are returned */ 1618/* A C expression which can inhibit the returning of certain function values 1619 in registers, based on the type of value. */ 1620#define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) 1621 1622/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1623 values must be in memory. On the ARM, they need only do so if larger 1624 than a word, or if they contain elements offset from zero in the struct. */ 1625#define DEFAULT_PCC_STRUCT_RETURN 0 1626 1627/* Flags for the call/call_value rtl operations set up by function_arg. */ 1628#define CALL_NORMAL 0x00000000 /* No special processing. */ 1629#define CALL_LONG 0x00000001 /* Always call indirect. */ 1630#define CALL_SHORT 0x00000002 /* Never call indirect. */ 1631 1632/* These bits describe the different types of function supported 1633 by the ARM backend. They are exclusive. ie a function cannot be both a 1634 normal function and an interworked function, for example. Knowing the 1635 type of a function is important for determining its prologue and 1636 epilogue sequences. 1637 Note value 7 is currently unassigned. Also note that the interrupt 1638 function types all have bit 2 set, so that they can be tested for easily. 1639 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1640 machine_function structure is initialized (to zero) func_type will 1641 default to unknown. This will force the first use of arm_current_func_type 1642 to call arm_compute_func_type. */ 1643#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1644#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1645#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1646#define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ 1647#define ARM_FT_ISR 4 /* An interrupt service routine. */ 1648#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1649#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1650 1651#define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1652 1653/* In addition functions can have several type modifiers, 1654 outlined by these bit masks: */ 1655#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1656#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1657#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1658#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1659 1660/* Some macros to test these flags. */ 1661#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1662#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1663#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1664#define IS_NAKED(t) (t & ARM_FT_NAKED) 1665#define IS_NESTED(t) (t & ARM_FT_NESTED) 1666 1667/* A C structure for machine-specific, per-function data. 1668 This is added to the cfun structure. */ 1669typedef struct machine_function GTY(()) 1670{ 1671 /* Additional stack adjustment in __builtin_eh_throw. */ 1672 rtx eh_epilogue_sp_ofs; 1673 /* Records if LR has to be saved for far jumps. */ 1674 int far_jump_used; 1675 /* Records if ARG_POINTER was ever live. */ 1676 int arg_pointer_live; 1677 /* Records if the save of LR has been eliminated. */ 1678 int lr_save_eliminated; 1679 /* The size of the stack frame. Only valid after reload. */ 1680 int frame_size; 1681 /* Records the type of the current function. */ 1682 unsigned long func_type; 1683 /* Record if the function has a variable argument list. */ 1684 int uses_anonymous_args; 1685 /* Records if sibcalls are blocked because an argument 1686 register is needed to preserve stack alignment. */ 1687 int sibcall_blocked; 1688} 1689machine_function; 1690 1691/* A C type for declaring a variable that is used as the first argument of 1692 `FUNCTION_ARG' and other related values. For some target machines, the 1693 type `int' suffices and can hold the number of bytes of argument so far. */ 1694typedef struct 1695{ 1696 /* This is the number of registers of arguments scanned so far. */ 1697 int nregs; 1698 /* This is the number of iWMMXt register arguments scanned so far. */ 1699 int iwmmxt_nregs; 1700 int named_count; 1701 int nargs; 1702 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */ 1703 int call_cookie; 1704} CUMULATIVE_ARGS; 1705 1706/* Define where to put the arguments to a function. 1707 Value is zero to push the argument on the stack, 1708 or a hard register in which to store the argument. 1709 1710 MODE is the argument's machine mode. 1711 TYPE is the data type of the argument (as a tree). 1712 This is null for libcalls where that information may 1713 not be available. 1714 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1715 the preceding args and about the function being called. 1716 NAMED is nonzero if this argument is a named parameter 1717 (otherwise it is an extra parameter matching an ellipsis). 1718 1719 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1720 other arguments are passed on the stack. If (NAMED == 0) (which happens 1721 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is 1722 passed in the stack (function_prologue will indeed make it pass in the 1723 stack if necessary). */ 1724#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1725 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1726 1727/* For an arg passed partly in registers and partly in memory, 1728 this is the number of registers used. 1729 For args passed entirely in registers or entirely in memory, zero. */ 1730#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1731 (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \ 1732 NUM_ARG_REGS > (CUM).nregs \ 1733 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \ 1734 ? NUM_ARG_REGS - (CUM).nregs : 0) 1735 1736/* A C expression that indicates when an argument must be passed by 1737 reference. If nonzero for an argument, a copy of that argument is 1738 made in memory and a pointer to the argument is passed instead of 1739 the argument itself. The pointer is passed in whatever way is 1740 appropriate for passing a pointer to that type. */ 1741#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1742 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) 1743 1744/* Initialize a variable CUM of type CUMULATIVE_ARGS 1745 for a call to a function whose data type is FNTYPE. 1746 For a library call, FNTYPE is 0. 1747 On the ARM, the offset starts at 0. */ 1748#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1749 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1750 1751/* Update the data in CUM to advance over an argument 1752 of mode MODE and data type TYPE. 1753 (TYPE is null for libcalls where that information may not be available.) */ 1754#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1755 (CUM).nargs += 1; \ 1756 if (VECTOR_MODE_SUPPORTED_P (MODE)) \ 1757 if ((CUM).named_count <= (CUM).nargs) \ 1758 (CUM).nregs += 2; \ 1759 else \ 1760 (CUM).iwmmxt_nregs += 1; \ 1761 else \ 1762 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) 1763 1764/* If defined, a C expression that gives the alignment boundary, in bits, of an 1765 argument with the specified mode and type. If it is not defined, 1766 `PARM_BOUNDARY' is used for all arguments. */ 1767#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ 1768 (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \ 1769 ? IWMMXT_ALIGNMENT : PARM_BOUNDARY) 1770 1771/* 1 if N is a possible register number for function argument passing. 1772 On the ARM, r0-r3 are used to pass args. */ 1773#define FUNCTION_ARG_REGNO_P(REGNO) \ 1774 (IN_RANGE ((REGNO), 0, 3) \ 1775 || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1776 1777/* Implement `va_arg'. */ 1778#define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1779 arm_va_arg (valist, type) 1780 1781 1782/* Perform any actions needed for a function that is receiving a variable 1783 number of arguments. CUM is as above. MODE and TYPE are the mode and type 1784 of the current parameter. PRETEND_SIZE is a variable that should be set to 1785 the amount of stack that must be pushed by the prolog to pretend that our 1786 caller pushed it. 1787 1788 Normally, this macro will push all remaining incoming registers on the 1789 stack and set PRETEND_SIZE to the length of the registers pushed. 1790 1791 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 1792 named arg and all anonymous args onto the stack. 1793 XXX I know the prologue shouldn't be pushing registers, but it is faster 1794 that way. */ 1795#define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1796{ \ 1797 cfun->machine->uses_anonymous_args = 1; \ 1798 if ((CUM).nregs < NUM_ARG_REGS) \ 1799 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ 1800} 1801 1802/* If your target environment doesn't prefix user functions with an 1803 underscore, you may wish to re-define this to prevent any conflicts. 1804 e.g. AOF may prefix mcount with an underscore. */ 1805#ifndef ARM_MCOUNT_NAME 1806#define ARM_MCOUNT_NAME "*mcount" 1807#endif 1808 1809/* Call the function profiler with a given profile label. The Acorn 1810 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1811 On the ARM the full profile code will look like: 1812 .data 1813 LP1 1814 .word 0 1815 .text 1816 mov ip, lr 1817 bl mcount 1818 .word LP1 1819 1820 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1821 will output the .text section. 1822 1823 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1824 ``prof'' doesn't seem to mind about this! 1825 1826 Note - this version of the code is designed to work in both ARM and 1827 Thumb modes. */ 1828#ifndef ARM_FUNCTION_PROFILER 1829#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1830{ \ 1831 char temp[20]; \ 1832 rtx sym; \ 1833 \ 1834 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1835 IP_REGNUM, LR_REGNUM); \ 1836 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1837 fputc ('\n', STREAM); \ 1838 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1839 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ 1840 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1841} 1842#endif 1843 1844#ifdef THUMB_FUNCTION_PROFILER 1845#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1846 if (TARGET_ARM) \ 1847 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1848 else \ 1849 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1850#else 1851#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1852 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1853#endif 1854 1855/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1856 the stack pointer does not matter. The value is tested only in 1857 functions that have frame pointers. 1858 No definition is equivalent to always zero. 1859 1860 On the ARM, the function epilogue recovers the stack pointer from the 1861 frame. */ 1862#define EXIT_IGNORE_STACK 1 1863 1864#define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) 1865 1866/* Determine if the epilogue should be output as RTL. 1867 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1868#define USE_RETURN_INSN(ISCOND) \ 1869 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) 1870 1871/* Definitions for register eliminations. 1872 1873 This is an array of structures. Each structure initializes one pair 1874 of eliminable registers. The "from" register number is given first, 1875 followed by "to". Eliminations of the same "from" register are listed 1876 in order of preference. 1877 1878 We have two registers that can be eliminated on the ARM. First, the 1879 arg pointer register can often be eliminated in favor of the stack 1880 pointer register. Secondly, the pseudo frame pointer register can always 1881 be eliminated; it is replaced with either the stack or the real frame 1882 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1883 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1884 1885#define ELIMINABLE_REGS \ 1886{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1887 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1888 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1889 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1890 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1891 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1892 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1893 1894/* Given FROM and TO register numbers, say whether this elimination is 1895 allowed. Frame pointer elimination is automatically handled. 1896 1897 All eliminations are permissible. Note that ARG_POINTER_REGNUM and 1898 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame 1899 pointer, we must eliminate FRAME_POINTER_REGNUM into 1900 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or 1901 ARG_POINTER_REGNUM. */ 1902#define CAN_ELIMINATE(FROM, TO) \ 1903 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ 1904 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ 1905 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ 1906 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ 1907 1) 1908 1909#define THUMB_REG_PUSHED_P(reg) \ 1910 (regs_ever_live [reg] \ 1911 && (! call_used_regs [reg] \ 1912 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \ 1913 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register))) 1914 1915/* Define the offset between two registers, one to be eliminated, and the 1916 other its replacement, at the start of a routine. */ 1917#define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1918 do \ 1919 { \ 1920 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1921 } \ 1922 while (0) 1923 1924/* Note: This macro must match the code in thumb_function_prologue(). */ 1925#define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1926{ \ 1927 (OFFSET) = 0; \ 1928 if ((FROM) == ARG_POINTER_REGNUM) \ 1929 { \ 1930 int count_regs = 0; \ 1931 int regno; \ 1932 for (regno = 8; regno < 13; regno ++) \ 1933 if (THUMB_REG_PUSHED_P (regno)) \ 1934 count_regs ++; \ 1935 if (count_regs) \ 1936 (OFFSET) += 4 * count_regs; \ 1937 count_regs = 0; \ 1938 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ 1939 if (THUMB_REG_PUSHED_P (regno)) \ 1940 count_regs ++; \ 1941 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ 1942 (OFFSET) += 4 * (count_regs + 1); \ 1943 if (TARGET_BACKTRACE) \ 1944 { \ 1945 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ 1946 (OFFSET) += 20; \ 1947 else \ 1948 (OFFSET) += 16; \ 1949 } \ 1950 } \ 1951 if ((TO) == STACK_POINTER_REGNUM) \ 1952 { \ 1953 (OFFSET) += current_function_outgoing_args_size; \ 1954 (OFFSET) += thumb_get_frame_size (); \ 1955 } \ 1956} 1957 1958#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1959 if (TARGET_ARM) \ 1960 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \ 1961 else \ 1962 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) 1963 1964/* Special case handling of the location of arguments passed on the stack. */ 1965#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1966 1967/* Initialize data used by insn expanders. This is called from insn_emit, 1968 once for every function before code is generated. */ 1969#define INIT_EXPANDERS arm_init_expanders () 1970 1971/* Output assembler code for a block containing the constant parts 1972 of a trampoline, leaving space for the variable parts. 1973 1974 On the ARM, (if r8 is the static chain regnum, and remembering that 1975 referencing pc adds an offset of 8) the trampoline looks like: 1976 ldr r8, [pc, #0] 1977 ldr pc, [pc] 1978 .word static chain value 1979 .word function's address 1980 XXX FIXME: When the trampoline returns, r8 will be clobbered. */ 1981#define ARM_TRAMPOLINE_TEMPLATE(FILE) \ 1982{ \ 1983 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 1984 STATIC_CHAIN_REGNUM, PC_REGNUM); \ 1985 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 1986 PC_REGNUM, PC_REGNUM); \ 1987 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1988 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1989} 1990 1991/* On the Thumb we always switch into ARM mode to execute the trampoline. 1992 Why - because it is easier. This code will always be branched to via 1993 a BX instruction and since the compiler magically generates the address 1994 of the function the linker has no opportunity to ensure that the 1995 bottom bit is set. Thus the processor will be in ARM mode when it 1996 reaches this code. So we duplicate the ARM trampoline code and add 1997 a switch into Thumb mode as well. */ 1998#define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ 1999{ \ 2000 fprintf (FILE, "\t.code 32\n"); \ 2001 fprintf (FILE, ".Ltrampoline_start:\n"); \ 2002 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ 2003 STATIC_CHAIN_REGNUM, PC_REGNUM); \ 2004 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ 2005 IP_REGNUM, PC_REGNUM); \ 2006 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ 2007 IP_REGNUM, IP_REGNUM); \ 2008 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ 2009 fprintf (FILE, "\t.word\t0\n"); \ 2010 fprintf (FILE, "\t.word\t0\n"); \ 2011 fprintf (FILE, "\t.code 16\n"); \ 2012} 2013 2014#define TRAMPOLINE_TEMPLATE(FILE) \ 2015 if (TARGET_ARM) \ 2016 ARM_TRAMPOLINE_TEMPLATE (FILE) \ 2017 else \ 2018 THUMB_TRAMPOLINE_TEMPLATE (FILE) 2019 2020/* Length in units of the trampoline for entering a nested function. */ 2021#define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) 2022 2023/* Alignment required for a trampoline in bits. */ 2024#define TRAMPOLINE_ALIGNMENT 32 2025 2026/* Emit RTL insns to initialize the variable parts of a trampoline. 2027 FNADDR is an RTX for the address of the function's pure code. 2028 CXT is an RTX for the static chain value for the function. */ 2029#ifndef INITIALIZE_TRAMPOLINE 2030#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 2031{ \ 2032 emit_move_insn (gen_rtx_MEM (SImode, \ 2033 plus_constant (TRAMP, \ 2034 TARGET_ARM ? 8 : 16)), \ 2035 CXT); \ 2036 emit_move_insn (gen_rtx_MEM (SImode, \ 2037 plus_constant (TRAMP, \ 2038 TARGET_ARM ? 12 : 20)), \ 2039 FNADDR); \ 2040} 2041#endif 2042 2043 2044/* Addressing modes, and classification of registers for them. */ 2045#define HAVE_POST_INCREMENT 1 2046#define HAVE_PRE_INCREMENT TARGET_ARM 2047#define HAVE_POST_DECREMENT TARGET_ARM 2048#define HAVE_PRE_DECREMENT TARGET_ARM 2049#define HAVE_PRE_MODIFY_DISP TARGET_ARM 2050#define HAVE_POST_MODIFY_DISP TARGET_ARM 2051#define HAVE_PRE_MODIFY_REG TARGET_ARM 2052#define HAVE_POST_MODIFY_REG TARGET_ARM 2053 2054/* Macros to check register numbers against specific register classes. */ 2055 2056/* These assume that REGNO is a hard or pseudo reg number. 2057 They give nonzero only if REGNO is a hard reg of the suitable class 2058 or a pseudo reg currently allocated to a suitable hard reg. 2059 Since they use reg_renumber, they are safe only once reg_renumber 2060 has been allocated, which happens in local-alloc.c. */ 2061#define TEST_REGNO(R, TEST, VALUE) \ 2062 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 2063 2064/* On the ARM, don't allow the pc to be used. */ 2065#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 2066 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 2067 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 2068 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 2069 2070#define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2071 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 2072 || (GET_MODE_SIZE (MODE) >= 4 \ 2073 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 2074 2075#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 2076 (TARGET_THUMB \ 2077 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 2078 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 2079 2080/* For ARM code, we don't care about the mode, but for Thumb, the index 2081 must be suitable for use in a QImode load. */ 2082#define REGNO_OK_FOR_INDEX_P(REGNO) \ 2083 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) 2084 2085/* Maximum number of registers that can appear in a valid memory address. 2086 Shifts in addresses can't be by a register. */ 2087#define MAX_REGS_PER_ADDRESS 2 2088 2089/* Recognize any constant value that is a valid address. */ 2090/* XXX We can address any constant, eventually... */ 2091 2092#ifdef AOF_ASSEMBLER 2093 2094#define CONSTANT_ADDRESS_P(X) \ 2095 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) 2096 2097#else 2098 2099#define CONSTANT_ADDRESS_P(X) \ 2100 (GET_CODE (X) == SYMBOL_REF \ 2101 && (CONSTANT_POOL_ADDRESS_P (X) \ 2102 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 2103 2104#endif /* AOF_ASSEMBLER */ 2105 2106/* Nonzero if the constant value X is a legitimate general operand. 2107 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 2108 2109 On the ARM, allow any integer (invalid ones are removed later by insn 2110 patterns), nice doubles and symbol_refs which refer to the function's 2111 constant pool XXX. 2112 2113 When generating pic allow anything. */ 2114#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 2115 2116#define THUMB_LEGITIMATE_CONSTANT_P(X) \ 2117 ( GET_CODE (X) == CONST_INT \ 2118 || GET_CODE (X) == CONST_DOUBLE \ 2119 || CONSTANT_ADDRESS_P (X) \ 2120 || flag_pic) 2121 2122#define LEGITIMATE_CONSTANT_P(X) \ 2123 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) 2124 2125/* Special characters prefixed to function names 2126 in order to encode attribute like information. 2127 Note, '@' and '*' have already been taken. */ 2128#define SHORT_CALL_FLAG_CHAR '^' 2129#define LONG_CALL_FLAG_CHAR '#' 2130 2131#define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ 2132 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) 2133 2134#define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ 2135 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) 2136 2137#ifndef SUBTARGET_NAME_ENCODING_LENGTHS 2138#define SUBTARGET_NAME_ENCODING_LENGTHS 2139#endif 2140 2141/* This is a C fragment for the inside of a switch statement. 2142 Each case label should return the number of characters to 2143 be stripped from the start of a function's name, if that 2144 name starts with the indicated character. */ 2145#define ARM_NAME_ENCODING_LENGTHS \ 2146 case SHORT_CALL_FLAG_CHAR: return 1; \ 2147 case LONG_CALL_FLAG_CHAR: return 1; \ 2148 case '*': return 1; \ 2149 SUBTARGET_NAME_ENCODING_LENGTHS 2150 2151/* This is how to output a reference to a user-level label named NAME. 2152 `assemble_name' uses this. */ 2153#undef ASM_OUTPUT_LABELREF 2154#define ASM_OUTPUT_LABELREF(FILE, NAME) \ 2155 arm_asm_output_labelref (FILE, NAME) 2156 2157#define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ 2158 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) 2159 2160/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2161 and check its validity for a certain class. 2162 We have two alternate definitions for each of them. 2163 The usual definition accepts all pseudo regs; the other rejects 2164 them unless they have been allocated suitable hard regs. 2165 The symbol REG_OK_STRICT causes the latter definition to be used. */ 2166#ifndef REG_OK_STRICT 2167 2168#define ARM_REG_OK_FOR_BASE_P(X) \ 2169 (REGNO (X) <= LAST_ARM_REGNUM \ 2170 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2171 || REGNO (X) == FRAME_POINTER_REGNUM \ 2172 || REGNO (X) == ARG_POINTER_REGNUM) 2173 2174#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2175 (REGNO (X) <= LAST_LO_REGNUM \ 2176 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2177 || (GET_MODE_SIZE (MODE) >= 4 \ 2178 && (REGNO (X) == STACK_POINTER_REGNUM \ 2179 || (X) == hard_frame_pointer_rtx \ 2180 || (X) == arg_pointer_rtx))) 2181 2182#define REG_STRICT_P 0 2183 2184#else /* REG_OK_STRICT */ 2185 2186#define ARM_REG_OK_FOR_BASE_P(X) \ 2187 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2188 2189#define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2190 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2191 2192#define REG_STRICT_P 1 2193 2194#endif /* REG_OK_STRICT */ 2195 2196/* Now define some helpers in terms of the above. */ 2197 2198#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2199 (TARGET_THUMB \ 2200 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2201 : ARM_REG_OK_FOR_BASE_P (X)) 2202 2203#define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) 2204 2205/* For Thumb, a valid index register is anything that can be used in 2206 a byte load instruction. */ 2207#define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) 2208 2209/* Nonzero if X is a hard reg that can be used as an index 2210 or if it is a pseudo reg. On the Thumb, the stack pointer 2211 is not suitable. */ 2212#define REG_OK_FOR_INDEX_P(X) \ 2213 (TARGET_THUMB \ 2214 ? THUMB_REG_OK_FOR_INDEX_P (X) \ 2215 : ARM_REG_OK_FOR_INDEX_P (X)) 2216 2217 2218/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2219 that is a valid memory address for an instruction. 2220 The MODE argument is the machine mode for the MEM expression 2221 that wants to use this address. */ 2222 2223#define ARM_BASE_REGISTER_RTX_P(X) \ 2224 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 2225 2226#define ARM_INDEX_REGISTER_RTX_P(X) \ 2227 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 2228 2229#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2230 { \ 2231 if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \ 2232 goto WIN; \ 2233 } 2234 2235#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ 2236 { \ 2237 if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \ 2238 goto WIN; \ 2239 } 2240 2241#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 2242 if (TARGET_ARM) \ 2243 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ 2244 else /* if (TARGET_THUMB) */ \ 2245 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) 2246 2247 2248/* Try machine-dependent ways of modifying an illegitimate address 2249 to be legitimate. If we find one, return the new, valid address. */ 2250#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2251do { \ 2252 X = arm_legitimize_address (X, OLDX, MODE); \ 2253 \ 2254 if (memory_address_p (MODE, X)) \ 2255 goto WIN; \ 2256} while (0) 2257 2258#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2259do { \ 2260 if (flag_pic) \ 2261 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 2262} while (0) 2263 2264#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2265do { \ 2266 if (TARGET_ARM) \ 2267 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2268 else \ 2269 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ 2270} while (0) 2271 2272/* Go to LABEL if ADDR (a legitimate address expression) 2273 has an effect that depends on the machine mode it is used for. */ 2274#define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2275{ \ 2276 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 2277 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 2278 goto LABEL; \ 2279} 2280 2281/* Nothing helpful to do for the Thumb */ 2282#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2283 if (TARGET_ARM) \ 2284 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) 2285 2286 2287/* Specify the machine mode that this machine uses 2288 for the index in the tablejump instruction. */ 2289#define CASE_VECTOR_MODE Pmode 2290 2291/* Define as C expression which evaluates to nonzero if the tablejump 2292 instruction expects the table to contain offsets from the address of the 2293 table. 2294 Do not define this if the table should contain absolute addresses. */ 2295/* #define CASE_VECTOR_PC_RELATIVE 1 */ 2296 2297/* signed 'char' is most compatible, but RISC OS wants it unsigned. 2298 unsigned is probably best, but may break some code. */ 2299#ifndef DEFAULT_SIGNED_CHAR 2300#define DEFAULT_SIGNED_CHAR 0 2301#endif 2302 2303/* Don't cse the address of the function being compiled. */ 2304#define NO_RECURSIVE_FUNCTION_CSE 1 2305 2306/* Max number of bytes we can move from memory to memory 2307 in one reasonably fast instruction. */ 2308#define MOVE_MAX 4 2309 2310#undef MOVE_RATIO 2311#define MOVE_RATIO (arm_tune_xscale ? 4 : 2) 2312 2313/* Define if operations between registers always perform the operation 2314 on the full register even if a narrower mode is specified. */ 2315#define WORD_REGISTER_OPERATIONS 2316 2317/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2318 will either zero-extend or sign-extend. The value of this macro should 2319 be the code that says which one of the two operations is implicitly 2320 done, NIL if none. */ 2321#define LOAD_EXTEND_OP(MODE) \ 2322 (TARGET_THUMB ? ZERO_EXTEND : \ 2323 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2324 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) 2325 2326/* Nonzero if access to memory by bytes is slow and undesirable. */ 2327#define SLOW_BYTE_ACCESS 0 2328 2329#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2330 2331/* Immediate shift counts are truncated by the output routines (or was it 2332 the assembler?). Shift counts in a register are truncated by ARM. Note 2333 that the native compiler puts too large (> 32) immediate shift counts 2334 into a register and shifts by the register, letting the ARM decide what 2335 to do instead of doing that itself. */ 2336/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2337 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2338 On the arm, Y in a register is used modulo 256 for the shift. Only for 2339 rotates is modulo 32 used. */ 2340/* #define SHIFT_COUNT_TRUNCATED 1 */ 2341 2342/* All integers have the same format so truncation is easy. */ 2343#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2344 2345/* Calling from registers is a massive pain. */ 2346#define NO_FUNCTION_CSE 1 2347 2348/* Chars and shorts should be passed as ints. */ 2349#define PROMOTE_PROTOTYPES 1 2350 2351/* The machine modes of pointers and functions */ 2352#define Pmode SImode 2353#define FUNCTION_MODE Pmode 2354 2355#define ARM_FRAME_RTX(X) \ 2356 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2357 || (X) == arg_pointer_rtx) 2358 2359/* Moves to and from memory are quite expensive */ 2360#define MEMORY_MOVE_COST(M, CLASS, IN) \ 2361 (TARGET_ARM ? 10 : \ 2362 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2363 * (CLASS == LO_REGS ? 1 : 2))) 2364 2365/* Try to generate sequences that don't involve branches, we can then use 2366 conditional instructions */ 2367#define BRANCH_COST \ 2368 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) 2369 2370/* Position Independent Code. */ 2371/* We decide which register to use based on the compilation options and 2372 the assembler in use; this is more general than the APCS restriction of 2373 using sb (r9) all the time. */ 2374extern int arm_pic_register; 2375 2376/* Used when parsing command line option -mpic-register=. */ 2377extern const char * arm_pic_register_string; 2378 2379/* The register number of the register used to address a table of static 2380 data addresses in memory. */ 2381#define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2382 2383#define FINALIZE_PIC arm_finalize_pic (1) 2384 2385/* We can't directly access anything that contains a symbol, 2386 nor can we indirect via the constant pool. */ 2387#define LEGITIMATE_PIC_OPERAND_P(X) \ 2388 (!(symbol_mentioned_p (X) \ 2389 || label_mentioned_p (X) \ 2390 || (GET_CODE (X) == SYMBOL_REF \ 2391 && CONSTANT_POOL_ADDRESS_P (X) \ 2392 && (symbol_mentioned_p (get_pool_constant (X)) \ 2393 || label_mentioned_p (get_pool_constant (X)))))) 2394 2395/* We need to know when we are making a constant pool; this determines 2396 whether data needs to be in the GOT or can be referenced via a GOT 2397 offset. */ 2398extern int making_const_table; 2399 2400/* Handle pragmas for compatibility with Intel's compilers. */ 2401#define REGISTER_TARGET_PRAGMAS() do { \ 2402 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2403 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2404 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2405} while (0) 2406 2407/* Condition code information. */ 2408/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2409 return the mode to be used for the comparison. */ 2410 2411#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2412 2413#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 2414 2415#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2416 do \ 2417 { \ 2418 if (GET_CODE (OP1) == CONST_INT \ 2419 && ! (const_ok_for_arm (INTVAL (OP1)) \ 2420 || (const_ok_for_arm (- INTVAL (OP1))))) \ 2421 { \ 2422 rtx const_op = OP1; \ 2423 CODE = arm_canonicalize_comparison ((CODE), &const_op); \ 2424 OP1 = const_op; \ 2425 } \ 2426 } \ 2427 while (0) 2428 2429/* The arm5 clz instruction returns 32. */ 2430#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2431 2432#undef ASM_APP_OFF 2433#define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") 2434 2435/* Output a push or a pop instruction (only used when profiling). */ 2436#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2437 do \ 2438 { \ 2439 if (TARGET_ARM) \ 2440 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2441 STACK_POINTER_REGNUM, REGNO); \ 2442 else \ 2443 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2444 } while (0) 2445 2446 2447#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2448 do \ 2449 { \ 2450 if (TARGET_ARM) \ 2451 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2452 STACK_POINTER_REGNUM, REGNO); \ 2453 else \ 2454 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2455 } while (0) 2456 2457/* This is how to output a label which precedes a jumptable. Since 2458 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2459#undef ASM_OUTPUT_CASE_LABEL 2460#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2461 do \ 2462 { \ 2463 if (TARGET_THUMB) \ 2464 ASM_OUTPUT_ALIGN (FILE, 2); \ 2465 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 2466 } \ 2467 while (0) 2468 2469#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2470 do \ 2471 { \ 2472 if (TARGET_THUMB) \ 2473 { \ 2474 if (is_called_in_ARM_mode (DECL) \ 2475 || current_function_is_thunk) \ 2476 fprintf (STREAM, "\t.code 32\n") ; \ 2477 else \ 2478 fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \ 2479 } \ 2480 if (TARGET_POKE_FUNCTION_NAME) \ 2481 arm_poke_function_name (STREAM, (char *) NAME); \ 2482 } \ 2483 while (0) 2484 2485/* For aliases of functions we use .thumb_set instead. */ 2486#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2487 do \ 2488 { \ 2489 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2490 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2491 \ 2492 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2493 { \ 2494 fprintf (FILE, "\t.thumb_set "); \ 2495 assemble_name (FILE, LABEL1); \ 2496 fprintf (FILE, ","); \ 2497 assemble_name (FILE, LABEL2); \ 2498 fprintf (FILE, "\n"); \ 2499 } \ 2500 else \ 2501 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2502 } \ 2503 while (0) 2504 2505#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2506/* To support -falign-* switches we need to use .p2align so 2507 that alignment directives in code sections will be padded 2508 with no-op instructions, rather than zeroes. */ 2509#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2510 if ((LOG) != 0) \ 2511 { \ 2512 if ((MAX_SKIP) == 0) \ 2513 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2514 else \ 2515 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2516 (int) (LOG), (int) (MAX_SKIP)); \ 2517 } 2518#endif 2519 2520/* Only perform branch elimination (by making instructions conditional) if 2521 we're optimizing. Otherwise it's of no use anyway. */ 2522#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2523 if (TARGET_ARM && optimize) \ 2524 arm_final_prescan_insn (INSN); \ 2525 else if (TARGET_THUMB) \ 2526 thumb_final_prescan_insn (INSN) 2527 2528#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2529 (CODE == '@' || CODE == '|' \ 2530 || (TARGET_ARM && (CODE == '?')) \ 2531 || (TARGET_THUMB && (CODE == '_'))) 2532 2533/* Output an operand of an instruction. */ 2534#define PRINT_OPERAND(STREAM, X, CODE) \ 2535 arm_print_operand (STREAM, X, CODE) 2536 2537#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2538 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2539 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2540 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2541 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2542 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2543 : 0)))) 2544 2545/* Output the address of an operand. */ 2546#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2547{ \ 2548 int is_minus = GET_CODE (X) == MINUS; \ 2549 \ 2550 if (GET_CODE (X) == REG) \ 2551 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2552 else if (GET_CODE (X) == PLUS || is_minus) \ 2553 { \ 2554 rtx base = XEXP (X, 0); \ 2555 rtx index = XEXP (X, 1); \ 2556 HOST_WIDE_INT offset = 0; \ 2557 if (GET_CODE (base) != REG) \ 2558 { \ 2559 /* Ensure that BASE is a register. */ \ 2560 /* (one of them must be). */ \ 2561 rtx temp = base; \ 2562 base = index; \ 2563 index = temp; \ 2564 } \ 2565 switch (GET_CODE (index)) \ 2566 { \ 2567 case CONST_INT: \ 2568 offset = INTVAL (index); \ 2569 if (is_minus) \ 2570 offset = -offset; \ 2571 asm_fprintf (STREAM, "[%r, #%wd]", \ 2572 REGNO (base), offset); \ 2573 break; \ 2574 \ 2575 case REG: \ 2576 asm_fprintf (STREAM, "[%r, %s%r]", \ 2577 REGNO (base), is_minus ? "-" : "", \ 2578 REGNO (index)); \ 2579 break; \ 2580 \ 2581 case MULT: \ 2582 case ASHIFTRT: \ 2583 case LSHIFTRT: \ 2584 case ASHIFT: \ 2585 case ROTATERT: \ 2586 { \ 2587 asm_fprintf (STREAM, "[%r, %s%r", \ 2588 REGNO (base), is_minus ? "-" : "", \ 2589 REGNO (XEXP (index, 0))); \ 2590 arm_print_operand (STREAM, index, 'S'); \ 2591 fputs ("]", STREAM); \ 2592 break; \ 2593 } \ 2594 \ 2595 default: \ 2596 abort(); \ 2597 } \ 2598 } \ 2599 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2600 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2601 { \ 2602 extern enum machine_mode output_memory_reference_mode; \ 2603 \ 2604 if (GET_CODE (XEXP (X, 0)) != REG) \ 2605 abort (); \ 2606 \ 2607 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2608 asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2609 REGNO (XEXP (X, 0)), \ 2610 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2611 GET_MODE_SIZE (output_memory_reference_mode)); \ 2612 else \ 2613 asm_fprintf (STREAM, "[%r], #%s%d", \ 2614 REGNO (XEXP (X, 0)), \ 2615 GET_CODE (X) == POST_DEC ? "-" : "", \ 2616 GET_MODE_SIZE (output_memory_reference_mode)); \ 2617 } \ 2618 else if (GET_CODE (X) == PRE_MODIFY) \ 2619 { \ 2620 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ 2621 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2622 asm_fprintf (STREAM, "#%wd]!", \ 2623 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2624 else \ 2625 asm_fprintf (STREAM, "%r]!", \ 2626 REGNO (XEXP (XEXP (X, 1), 1))); \ 2627 } \ 2628 else if (GET_CODE (X) == POST_MODIFY) \ 2629 { \ 2630 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ 2631 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2632 asm_fprintf (STREAM, "#%wd", \ 2633 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2634 else \ 2635 asm_fprintf (STREAM, "%r", \ 2636 REGNO (XEXP (XEXP (X, 1), 1))); \ 2637 } \ 2638 else output_addr_const (STREAM, X); \ 2639} 2640 2641#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2642{ \ 2643 if (GET_CODE (X) == REG) \ 2644 asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 2645 else if (GET_CODE (X) == POST_INC) \ 2646 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 2647 else if (GET_CODE (X) == PLUS) \ 2648 { \ 2649 if (GET_CODE (XEXP (X, 0)) != REG) \ 2650 abort (); \ 2651 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2652 asm_fprintf (STREAM, "[%r, #%wd]", \ 2653 REGNO (XEXP (X, 0)), \ 2654 INTVAL (XEXP (X, 1))); \ 2655 else \ 2656 asm_fprintf (STREAM, "[%r, %r]", \ 2657 REGNO (XEXP (X, 0)), \ 2658 REGNO (XEXP (X, 1))); \ 2659 } \ 2660 else \ 2661 output_addr_const (STREAM, X); \ 2662} 2663 2664#define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2665 if (TARGET_ARM) \ 2666 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 2667 else \ 2668 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2669 2670#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2671 if (GET_CODE (X) != CONST_VECTOR \ 2672 || ! arm_emit_vector_const (FILE, X)) \ 2673 goto FAIL; 2674 2675/* A C expression whose value is RTL representing the value of the return 2676 address for the frame COUNT steps up from the current frame. */ 2677 2678#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2679 arm_return_addr (COUNT, FRAME) 2680 2681/* Mask of the bits in the PC that contain the real return address 2682 when running in 26-bit mode. */ 2683#define RETURN_ADDR_MASK26 (0x03fffffc) 2684 2685/* Pick up the return address upon entry to a procedure. Used for 2686 dwarf2 unwind information. This also enables the table driven 2687 mechanism. */ 2688#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2689#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2690 2691/* Used to mask out junk bits from the return address, such as 2692 processor state, interrupt status, condition codes and the like. */ 2693#define MASK_RETURN_ADDR \ 2694 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2695 in 26 bit mode, the condition codes must be masked out of the \ 2696 return address. This does not apply to ARM6 and later processors \ 2697 when running in 32 bit mode. */ \ 2698 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \ 2699 : (arm_arch4 || TARGET_THUMB) ? \ 2700 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2701 : arm_gen_return_addr_mask ()) 2702 2703 2704/* Define the codes that are matched by predicates in arm.c */ 2705#define PREDICATE_CODES \ 2706 {"s_register_operand", {SUBREG, REG}}, \ 2707 {"arm_hard_register_operand", {REG}}, \ 2708 {"f_register_operand", {SUBREG, REG}}, \ 2709 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ 2710 {"arm_addimm_operand", {CONST_INT}}, \ 2711 {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2712 {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2713 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ 2714 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ 2715 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ 2716 {"index_operand", {SUBREG, REG, CONST_INT}}, \ 2717 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ 2718 {"thumb_cmpneg_operand", {CONST_INT}}, \ 2719 {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \ 2720 {"offsettable_memory_operand", {MEM}}, \ 2721 {"bad_signed_byte_operand", {MEM}}, \ 2722 {"alignable_memory_operand", {MEM}}, \ 2723 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ 2724 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ 2725 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ 2726 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 2727 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ 2728 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ 2729 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ 2730 {"load_multiple_operation", {PARALLEL}}, \ 2731 {"store_multiple_operation", {PARALLEL}}, \ 2732 {"equality_operator", {EQ, NE}}, \ 2733 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ 2734 LTU, UNORDERED, ORDERED, UNLT, UNLE, \ 2735 UNGE, UNGT}}, \ 2736 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 2737 {"const_shift_operand", {CONST_INT}}, \ 2738 {"multi_register_push", {PARALLEL}}, \ 2739 {"cc_register", {REG}}, \ 2740 {"logical_binary_operator", {AND, IOR, XOR}}, \ 2741 {"cirrus_register_operand", {REG}}, \ 2742 {"cirrus_fp_register", {REG}}, \ 2743 {"cirrus_shift_const", {CONST_INT}}, \ 2744 {"dominant_cc_register", {REG}}, 2745 2746/* Define this if you have special predicates that know special things 2747 about modes. Genrecog will warn about certain forms of 2748 match_operand without a mode; if the operand predicate is listed in 2749 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ 2750#define SPECIAL_MODE_PREDICATES \ 2751 "cc_register", "dominant_cc_register", 2752 2753enum arm_builtins 2754{ 2755 ARM_BUILTIN_GETWCX, 2756 ARM_BUILTIN_SETWCX, 2757 2758 ARM_BUILTIN_WZERO, 2759 2760 ARM_BUILTIN_WAVG2BR, 2761 ARM_BUILTIN_WAVG2HR, 2762 ARM_BUILTIN_WAVG2B, 2763 ARM_BUILTIN_WAVG2H, 2764 2765 ARM_BUILTIN_WACCB, 2766 ARM_BUILTIN_WACCH, 2767 ARM_BUILTIN_WACCW, 2768 2769 ARM_BUILTIN_WMACS, 2770 ARM_BUILTIN_WMACSZ, 2771 ARM_BUILTIN_WMACU, 2772 ARM_BUILTIN_WMACUZ, 2773 2774 ARM_BUILTIN_WSADB, 2775 ARM_BUILTIN_WSADBZ, 2776 ARM_BUILTIN_WSADH, 2777 ARM_BUILTIN_WSADHZ, 2778 2779 ARM_BUILTIN_WALIGN, 2780 2781 ARM_BUILTIN_TMIA, 2782 ARM_BUILTIN_TMIAPH, 2783 ARM_BUILTIN_TMIABB, 2784 ARM_BUILTIN_TMIABT, 2785 ARM_BUILTIN_TMIATB, 2786 ARM_BUILTIN_TMIATT, 2787 2788 ARM_BUILTIN_TMOVMSKB, 2789 ARM_BUILTIN_TMOVMSKH, 2790 ARM_BUILTIN_TMOVMSKW, 2791 2792 ARM_BUILTIN_TBCSTB, 2793 ARM_BUILTIN_TBCSTH, 2794 ARM_BUILTIN_TBCSTW, 2795 2796 ARM_BUILTIN_WMADDS, 2797 ARM_BUILTIN_WMADDU, 2798 2799 ARM_BUILTIN_WPACKHSS, 2800 ARM_BUILTIN_WPACKWSS, 2801 ARM_BUILTIN_WPACKDSS, 2802 ARM_BUILTIN_WPACKHUS, 2803 ARM_BUILTIN_WPACKWUS, 2804 ARM_BUILTIN_WPACKDUS, 2805 2806 ARM_BUILTIN_WADDB, 2807 ARM_BUILTIN_WADDH, 2808 ARM_BUILTIN_WADDW, 2809 ARM_BUILTIN_WADDSSB, 2810 ARM_BUILTIN_WADDSSH, 2811 ARM_BUILTIN_WADDSSW, 2812 ARM_BUILTIN_WADDUSB, 2813 ARM_BUILTIN_WADDUSH, 2814 ARM_BUILTIN_WADDUSW, 2815 ARM_BUILTIN_WSUBB, 2816 ARM_BUILTIN_WSUBH, 2817 ARM_BUILTIN_WSUBW, 2818 ARM_BUILTIN_WSUBSSB, 2819 ARM_BUILTIN_WSUBSSH, 2820 ARM_BUILTIN_WSUBSSW, 2821 ARM_BUILTIN_WSUBUSB, 2822 ARM_BUILTIN_WSUBUSH, 2823 ARM_BUILTIN_WSUBUSW, 2824 2825 ARM_BUILTIN_WAND, 2826 ARM_BUILTIN_WANDN, 2827 ARM_BUILTIN_WOR, 2828 ARM_BUILTIN_WXOR, 2829 2830 ARM_BUILTIN_WCMPEQB, 2831 ARM_BUILTIN_WCMPEQH, 2832 ARM_BUILTIN_WCMPEQW, 2833 ARM_BUILTIN_WCMPGTUB, 2834 ARM_BUILTIN_WCMPGTUH, 2835 ARM_BUILTIN_WCMPGTUW, 2836 ARM_BUILTIN_WCMPGTSB, 2837 ARM_BUILTIN_WCMPGTSH, 2838 ARM_BUILTIN_WCMPGTSW, 2839 2840 ARM_BUILTIN_TEXTRMSB, 2841 ARM_BUILTIN_TEXTRMSH, 2842 ARM_BUILTIN_TEXTRMSW, 2843 ARM_BUILTIN_TEXTRMUB, 2844 ARM_BUILTIN_TEXTRMUH, 2845 ARM_BUILTIN_TEXTRMUW, 2846 ARM_BUILTIN_TINSRB, 2847 ARM_BUILTIN_TINSRH, 2848 ARM_BUILTIN_TINSRW, 2849 2850 ARM_BUILTIN_WMAXSW, 2851 ARM_BUILTIN_WMAXSH, 2852 ARM_BUILTIN_WMAXSB, 2853 ARM_BUILTIN_WMAXUW, 2854 ARM_BUILTIN_WMAXUH, 2855 ARM_BUILTIN_WMAXUB, 2856 ARM_BUILTIN_WMINSW, 2857 ARM_BUILTIN_WMINSH, 2858 ARM_BUILTIN_WMINSB, 2859 ARM_BUILTIN_WMINUW, 2860 ARM_BUILTIN_WMINUH, 2861 ARM_BUILTIN_WMINUB, 2862 2863 ARM_BUILTIN_WMULUH, 2864 ARM_BUILTIN_WMULSH, 2865 ARM_BUILTIN_WMULUL, 2866 2867 ARM_BUILTIN_PSADBH, 2868 ARM_BUILTIN_WSHUFH, 2869 2870 ARM_BUILTIN_WSLLH, 2871 ARM_BUILTIN_WSLLW, 2872 ARM_BUILTIN_WSLLD, 2873 ARM_BUILTIN_WSRAH, 2874 ARM_BUILTIN_WSRAW, 2875 ARM_BUILTIN_WSRAD, 2876 ARM_BUILTIN_WSRLH, 2877 ARM_BUILTIN_WSRLW, 2878 ARM_BUILTIN_WSRLD, 2879 ARM_BUILTIN_WRORH, 2880 ARM_BUILTIN_WRORW, 2881 ARM_BUILTIN_WRORD, 2882 ARM_BUILTIN_WSLLHI, 2883 ARM_BUILTIN_WSLLWI, 2884 ARM_BUILTIN_WSLLDI, 2885 ARM_BUILTIN_WSRAHI, 2886 ARM_BUILTIN_WSRAWI, 2887 ARM_BUILTIN_WSRADI, 2888 ARM_BUILTIN_WSRLHI, 2889 ARM_BUILTIN_WSRLWI, 2890 ARM_BUILTIN_WSRLDI, 2891 ARM_BUILTIN_WRORHI, 2892 ARM_BUILTIN_WRORWI, 2893 ARM_BUILTIN_WRORDI, 2894 2895 ARM_BUILTIN_WUNPCKIHB, 2896 ARM_BUILTIN_WUNPCKIHH, 2897 ARM_BUILTIN_WUNPCKIHW, 2898 ARM_BUILTIN_WUNPCKILB, 2899 ARM_BUILTIN_WUNPCKILH, 2900 ARM_BUILTIN_WUNPCKILW, 2901 2902 ARM_BUILTIN_WUNPCKEHSB, 2903 ARM_BUILTIN_WUNPCKEHSH, 2904 ARM_BUILTIN_WUNPCKEHSW, 2905 ARM_BUILTIN_WUNPCKEHUB, 2906 ARM_BUILTIN_WUNPCKEHUH, 2907 ARM_BUILTIN_WUNPCKEHUW, 2908 ARM_BUILTIN_WUNPCKELSB, 2909 ARM_BUILTIN_WUNPCKELSH, 2910 ARM_BUILTIN_WUNPCKELSW, 2911 ARM_BUILTIN_WUNPCKELUB, 2912 ARM_BUILTIN_WUNPCKELUH, 2913 ARM_BUILTIN_WUNPCKELUW, 2914 2915 ARM_BUILTIN_MAX 2916}; 2917#endif /* ! GCC_ARM_H */ 2918