1169689Skan;; Generic ARM Pipeline Description 2169689Skan;; Copyright (C) 2003 Free Software Foundation, Inc. 3169689Skan;; 4169689Skan;; This file is part of GCC. 5169689Skan;; 6169689Skan;; GCC is free software; you can redistribute it and/or modify it 7169689Skan;; under the terms of the GNU General Public License as published by 8169689Skan;; the Free Software Foundation; either version 2, or (at your option) 9169689Skan;; any later version. 10169689Skan;; 11169689Skan;; GCC is distributed in the hope that it will be useful, but 12169689Skan;; WITHOUT ANY WARRANTY; without even the implied warranty of 13169689Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14169689Skan;; General Public License for more details. 15169689Skan;; 16169689Skan;; You should have received a copy of the GNU General Public License 17169689Skan;; along with GCC; see the file COPYING. If not, write to the Free 18169689Skan;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 19169689Skan;; 02110-1301, USA. */ 20169689Skan 21169689Skan(define_automaton "arm") 22169689Skan 23169689Skan;; Write buffer 24169689Skan; 25169689Skan; Strictly, we should model a 4-deep write buffer for ARM7xx based chips 26169689Skan; 27169689Skan; The write buffer on some of the arm6 processors is hard to model exactly. 28169689Skan; There is room in the buffer for up to two addresses and up to eight words 29169689Skan; of memory, but the two needn't be split evenly. When writing the two 30169689Skan; addresses are fully pipelined. However, a read from memory that is not 31169689Skan; currently in the cache will block until the writes have completed. 32169689Skan; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so 33169689Skan; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous 34169689Skan; (they aren't allowed to be at present) then there is a startup cost of 1MCLK 35169689Skan; cycle to add as well. 36169689Skan(define_cpu_unit "write_buf" "arm") 37169689Skan 38169689Skan;; Write blockage unit 39169689Skan; 40169689Skan; The write_blockage unit models (partially), the fact that reads will stall 41169689Skan; until the write buffer empties. 42169689Skan; The f_mem_r and r_mem_f could also block, but they are to the stack, 43169689Skan; so we don't model them here 44169689Skan(define_cpu_unit "write_blockage" "arm") 45169689Skan 46169689Skan;; Core 47169689Skan; 48169689Skan(define_cpu_unit "core" "arm") 49169689Skan 50169689Skan(define_insn_reservation "r_mem_f_wbuf" 5 51169689Skan (and (eq_attr "generic_sched" "yes") 52169689Skan (and (eq_attr "model_wbuf" "yes") 53169689Skan (eq_attr "type" "r_mem_f"))) 54169689Skan "core+write_buf*3") 55169689Skan 56169689Skan(define_insn_reservation "store_wbuf" 5 57169689Skan (and (eq_attr "generic_sched" "yes") 58169689Skan (and (eq_attr "model_wbuf" "yes") 59169689Skan (eq_attr "type" "store1"))) 60169689Skan "core+write_buf*3+write_blockage*5") 61169689Skan 62169689Skan(define_insn_reservation "store2_wbuf" 7 63169689Skan (and (eq_attr "generic_sched" "yes") 64169689Skan (and (eq_attr "model_wbuf" "yes") 65169689Skan (eq_attr "type" "store2"))) 66169689Skan "core+write_buf*4+write_blockage*7") 67169689Skan 68169689Skan(define_insn_reservation "store3_wbuf" 9 69169689Skan (and (eq_attr "generic_sched" "yes") 70169689Skan (and (eq_attr "model_wbuf" "yes") 71169689Skan (eq_attr "type" "store3"))) 72169689Skan "core+write_buf*5+write_blockage*9") 73169689Skan 74169689Skan(define_insn_reservation "store4_wbuf" 11 75169689Skan (and (eq_attr "generic_sched" "yes") 76169689Skan (and (eq_attr "model_wbuf" "yes") 77169689Skan (eq_attr "type" "store4"))) 78169689Skan "core+write_buf*6+write_blockage*11") 79169689Skan 80169689Skan(define_insn_reservation "store2" 3 81169689Skan (and (eq_attr "generic_sched" "yes") 82169689Skan (and (eq_attr "model_wbuf" "no") 83169689Skan (eq_attr "type" "store2"))) 84169689Skan "core*3") 85169689Skan 86169689Skan(define_insn_reservation "store3" 4 87169689Skan (and (eq_attr "generic_sched" "yes") 88169689Skan (and (eq_attr "model_wbuf" "no") 89169689Skan (eq_attr "type" "store3"))) 90169689Skan "core*4") 91169689Skan 92169689Skan(define_insn_reservation "store4" 5 93169689Skan (and (eq_attr "generic_sched" "yes") 94169689Skan (and (eq_attr "model_wbuf" "no") 95169689Skan (eq_attr "type" "store4"))) 96169689Skan "core*5") 97169689Skan 98169689Skan(define_insn_reservation "store_ldsched" 1 99169689Skan (and (eq_attr "generic_sched" "yes") 100169689Skan (and (eq_attr "ldsched" "yes") 101169689Skan (eq_attr "type" "store1"))) 102169689Skan "core") 103169689Skan 104169689Skan(define_insn_reservation "load_ldsched_xscale" 3 105169689Skan (and (eq_attr "generic_sched" "yes") 106169689Skan (and (eq_attr "ldsched" "yes") 107169689Skan (and (eq_attr "type" "load_byte,load1") 108169689Skan (eq_attr "is_xscale" "yes")))) 109169689Skan "core") 110169689Skan 111169689Skan(define_insn_reservation "load_ldsched" 2 112169689Skan (and (eq_attr "generic_sched" "yes") 113169689Skan (and (eq_attr "ldsched" "yes") 114169689Skan (and (eq_attr "type" "load_byte,load1") 115169689Skan (eq_attr "is_xscale" "no")))) 116169689Skan "core") 117169689Skan 118169689Skan(define_insn_reservation "load_or_store" 2 119169689Skan (and (eq_attr "generic_sched" "yes") 120169689Skan (and (eq_attr "ldsched" "!yes") 121169689Skan (eq_attr "type" "load_byte,load1,load2,load3,load4,store1"))) 122169689Skan "core*2") 123169689Skan 124169689Skan(define_insn_reservation "mult" 16 125169689Skan (and (eq_attr "generic_sched" "yes") 126169689Skan (and (eq_attr "ldsched" "no") (eq_attr "type" "mult"))) 127169689Skan "core*16") 128169689Skan 129169689Skan(define_insn_reservation "mult_ldsched_strongarm" 3 130169689Skan (and (eq_attr "generic_sched" "yes") 131169689Skan (and (eq_attr "ldsched" "yes") 132169689Skan (and (eq_attr "is_strongarm" "yes") 133169689Skan (eq_attr "type" "mult")))) 134169689Skan "core*2") 135169689Skan 136169689Skan(define_insn_reservation "mult_ldsched" 4 137169689Skan (and (eq_attr "generic_sched" "yes") 138169689Skan (and (eq_attr "ldsched" "yes") 139169689Skan (and (eq_attr "is_strongarm" "no") 140169689Skan (eq_attr "type" "mult")))) 141169689Skan "core*4") 142169689Skan 143169689Skan(define_insn_reservation "multi_cycle" 32 144169689Skan (and (eq_attr "generic_sched" "yes") 145169689Skan (and (eq_attr "core_cycles" "multi") 146169689Skan (eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4"))) 147169689Skan "core*32") 148169689Skan 149169689Skan(define_insn_reservation "single_cycle" 1 150169689Skan (and (eq_attr "generic_sched" "yes") 151169689Skan (eq_attr "core_cycles" "single")) 152169689Skan "core") 153