1;; Generic ARM Pipeline Description
2;; Copyright (C) 2003 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify it
7;; under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 2, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful, but
12;; WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14;; General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING.  If not, write to the Free
18;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
19;; 02110-1301, USA.  */
20
21(define_automaton "arm")
22
23;; Write buffer
24;
25; Strictly, we should model a 4-deep write buffer for ARM7xx based chips
26;
27; The write buffer on some of the arm6 processors is hard to model exactly.
28; There is room in the buffer for up to two addresses and up to eight words
29; of memory, but the two needn't be split evenly.  When writing the two
30; addresses are fully pipelined.  However, a read from memory that is not
31; currently in the cache will block until the writes have completed.
32; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so
33; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous
34; (they aren't allowed to be at present) then there is a startup cost of 1MCLK
35; cycle to add as well.
36(define_cpu_unit "write_buf" "arm")
37
38;; Write blockage unit
39;
40; The write_blockage unit models (partially), the fact that reads will stall
41; until the write buffer empties.
42; The f_mem_r and r_mem_f could also block, but they are to the stack,
43; so we don't model them here
44(define_cpu_unit "write_blockage" "arm")
45
46;; Core
47;
48(define_cpu_unit "core" "arm")
49
50(define_insn_reservation "r_mem_f_wbuf" 5
51  (and (eq_attr "generic_sched" "yes")
52       (and (eq_attr "model_wbuf" "yes")
53	    (eq_attr "type" "r_mem_f")))
54  "core+write_buf*3")
55
56(define_insn_reservation "store_wbuf" 5
57  (and (eq_attr "generic_sched" "yes")
58       (and (eq_attr "model_wbuf" "yes")
59       	    (eq_attr "type" "store1")))
60  "core+write_buf*3+write_blockage*5")
61
62(define_insn_reservation "store2_wbuf" 7
63  (and (eq_attr "generic_sched" "yes")
64       (and (eq_attr "model_wbuf" "yes")
65	    (eq_attr "type" "store2")))
66  "core+write_buf*4+write_blockage*7")
67
68(define_insn_reservation "store3_wbuf" 9
69  (and (eq_attr "generic_sched" "yes")
70       (and (eq_attr "model_wbuf" "yes")
71	    (eq_attr "type" "store3")))
72  "core+write_buf*5+write_blockage*9")
73
74(define_insn_reservation "store4_wbuf" 11
75  (and (eq_attr "generic_sched" "yes")
76       (and (eq_attr "model_wbuf" "yes")
77            (eq_attr "type" "store4")))
78  "core+write_buf*6+write_blockage*11")
79
80(define_insn_reservation "store2" 3
81  (and (eq_attr "generic_sched" "yes")
82       (and (eq_attr "model_wbuf" "no")
83            (eq_attr "type" "store2")))
84  "core*3")
85
86(define_insn_reservation "store3" 4
87  (and (eq_attr "generic_sched" "yes")
88       (and (eq_attr "model_wbuf" "no")
89            (eq_attr "type" "store3")))
90  "core*4")
91
92(define_insn_reservation "store4" 5
93  (and (eq_attr "generic_sched" "yes")
94       (and (eq_attr "model_wbuf" "no")
95	    (eq_attr "type" "store4")))
96  "core*5")
97
98(define_insn_reservation "store_ldsched" 1
99  (and (eq_attr "generic_sched" "yes")
100       (and (eq_attr "ldsched" "yes") 
101	    (eq_attr "type" "store1")))
102  "core")
103
104(define_insn_reservation "load_ldsched_xscale" 3
105  (and (eq_attr "generic_sched" "yes")
106       (and (eq_attr "ldsched" "yes") 
107	    (and (eq_attr "type" "load_byte,load1")
108	         (eq_attr "is_xscale" "yes"))))
109  "core")
110
111(define_insn_reservation "load_ldsched" 2
112  (and (eq_attr "generic_sched" "yes")
113       (and (eq_attr "ldsched" "yes") 
114	    (and (eq_attr "type" "load_byte,load1")
115	         (eq_attr "is_xscale" "no"))))
116  "core")
117
118(define_insn_reservation "load_or_store" 2
119  (and (eq_attr "generic_sched" "yes")
120       (and (eq_attr "ldsched" "!yes") 
121	    (eq_attr "type" "load_byte,load1,load2,load3,load4,store1")))
122  "core*2")
123
124(define_insn_reservation "mult" 16
125  (and (eq_attr "generic_sched" "yes")
126       (and (eq_attr "ldsched" "no") (eq_attr "type" "mult")))
127  "core*16")
128
129(define_insn_reservation "mult_ldsched_strongarm" 3
130  (and (eq_attr "generic_sched" "yes")
131       (and (eq_attr "ldsched" "yes") 
132	    (and (eq_attr "is_strongarm" "yes")
133	         (eq_attr "type" "mult"))))
134  "core*2")
135
136(define_insn_reservation "mult_ldsched" 4
137  (and (eq_attr "generic_sched" "yes")
138       (and (eq_attr "ldsched" "yes") 
139	    (and (eq_attr "is_strongarm" "no")
140	         (eq_attr "type" "mult"))))
141  "core*4")
142
143(define_insn_reservation "multi_cycle" 32
144  (and (eq_attr "generic_sched" "yes")
145       (and (eq_attr "core_cycles" "multi")
146            (eq_attr "type" "!mult,load_byte,load1,load2,load3,load4,store1,store2,store3,store4")))
147  "core*32")
148
149(define_insn_reservation "single_cycle" 1
150  (and (eq_attr "generic_sched" "yes")
151       (eq_attr "core_cycles" "single"))
152  "core")
153