ChangeLog.gcc43 revision 259583
12007-08-08 Andrew Haley <aph@redhat.com> (r128087) 2 3 * config/arm/libunwind.S (UNWIND_WRAPPER _Unwind_Backtrace): New. 4 * config/arm/unwind-arm.h (__gnu_Unwind_Backtrace): New. 5 * config/arm/unwind-arm.c (__gnu_Unwind_Backtrace): New. 6 72007-06-05 Joerg Wunsch <j.gnu@uriah.heep.sax.de> (r125346) 8 9 PR preprocessor/23479 10 * doc/extend.texi: Document the 0b-prefixed binary integer 11 constant extension. 12 132007-05-31 Eric Christopher <echristo@apple.com> (r125246) 14 15 * expr.c (convert_move): Assert that we don't have a BLKmode 16 operand. 17 (store_expr): Handle BLKmode moves by calling emit_block_move. 18 192007-05-27 Eric Christopher <echristo@apple.com> (r125116) 20 21 * config/rs6000/rs6000.c (rs6000_emit_prologue): Update 22 sp_offset depending on stack size. Save r12 depending 23 on registers we're saving later. 24 (rs6000_emit_epilogue): Update sp_offset depending only 25 on stack size. 26 272007-05-24 Richard Sandiford <rsandifo@nildram.co.uk> (r125037) 28 29 * postreload-gcse.c (reg_changed_after_insn_p): New function. 30 (oprs_unchanged_p): Use it to check all registers in a REG. 31 (record_opr_changes): Look for clobbers in CALL_INSN_FUNCTION_USAGE. 32 (reg_set_between_after_reload_p): Delete. 33 (reg_used_between_after_reload_p): Likewise. 34 (reg_set_or_used_since_bb_start): Likewise. 35 (eliminate_partially_redundant_load): Use reg_changed_after_insn_p 36 and reg_used_between_p instead of reg_set_or_used_since_bb_start. 37 Use reg_set_between_p instead of reg_set_between_after_reload_p. 38 * rtlanal.c (reg_set_p): Check whether REG overlaps 39 regs_invalidated_by_call, rather than just checking the 40 membership of REGNO (REG). 41 422007-05-16 Eric Christopher <echristo@apple.com> (r124763) 43 44 * config/rs6000/rs6000.c (rs6000_emit_prologue): Move altivec register 45 saving after stack push. Set sp_offset whenever we push. 46 (rs6000_emit_epilogue): Move altivec register restore before stack push. 47 482007-05-03 Ian Lance Taylor <iant@google.com> (r124381) 49 50 * config/rs6000/rs6000.c (rs6000_override_options): Don't set 51 MASK_PPC_GFXOPT for 8540 or 8548. 52 532007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124341) 54 55 * doc/invoke.texi: Fix typo, 'AMD Family 10h core' instead of 56 'AMD Family 10 core'. 57 582007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124339) 59 60 * config/i386/i386.c (override_options): Accept k8-sse3, opteron-sse3 61 and athlon64-sse3 as improved versions of k8, opteron and athlon64 62 with SSE3 instruction set support. 63 * doc/invoke.texi: Likewise. 64 652007-05-01 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r124330) 66 67 * config/i386/i386.c (override_options): Tuning 32-byte loop 68 alignment for amdfam10 architecture. Increasing the max loop 69 alignment to 24 bytes. 70 712007-04-16 Lawrence Crowl <crowl@google.com> 72 73 * doc/invoke.texi (Debugging Options): Add documentation for the 74 -femit-struct-debug options -femit-struct-debug-baseonly, 75 -femit-struct-debug-reduced, and 76 -femit-struct-debug-detailed[=...]. 77 78 * c-opts.c (c_common_handle_option): Add 79 OPT_femit_struct_debug_baseonly, OPT_femit_struct_debug_reduced, 80 and OPT_femit_struct_debug_detailed_. 81 * c.opt: Add specifications for 82 -femit-struct-debug-baseonly, -femit-struct-debug-reduced, 83 and -femit-struct-debug-detailed[=...]. 84 * opts.c (set_struct_debug_option): Parse the 85 -femit-struct-debug-... options. 86 * opts.c (matches_main_base, main_input_basename, 87 main_input_baselength, base_of_path, matches_main_base): Add 88 variables and functions to compare header base name to compilation 89 unit base name. 90 * opts.c (should_emit_struct_debug): Add to determine to emit a 91 structure based on the option. 92 (dump_struct_debug) Also disabled function to debug this 93 function. 94 * opts.c (handle_options): Save the base name of the 95 compilation unit. 96 97 * langhooks-def.h (LANG_HOOKS_GENERIC_TYPE_P): Define. 98 (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add. 99 This hook indicates if a type is generic. Set it by default 100 to "never generic". 101 * langhooks.h (struct lang_hooks_for_types): Add a new hook 102 to determine if a struct type is generic or not. 103 * cp/cp-tree.h (class_tmpl_impl_spec_p): Declare a C++ hook. 104 * cp/tree.c (class_tmpl_impl_spec_p): Implement the C++ hook. 105 * cp/cp-lang.c (LANG_HOOKS_GENERIC_TYPE_P): Override null C hook 106 with live C++ hook. 107 108 * flags.h (enum debug_info_usage): Add an enumeration to describe 109 a program's use of a structure type. 110 * dwarf2out.c (gen_struct_or_union_type_die): Add a new parameter 111 to indicate the program's usage of the type. Filter structs based 112 on the -femit-struct-debug-... specification. 113 (gen_type_die): Split into two routines, gen_type_die and 114 gen_type_die_with_usage. gen_type_die is now a wrapper 115 that assumes direct usage. 116 (gen_type_die_with_usage): Replace calls to gen_type_die 117 with gen_type_die_with_usage adding the program usage of 118 the referenced type. 119 (dwarf2out_imported_module_or_decl): Suppress struct debug 120 information using should_emit_struct_debug when appropriate. 121 1222007-04-16 Ian Lance Taylor <iant@google.com> (r123906) 123 124 * tree-ssa-propagate.c (cfg_blocks_add): Insert blocks with fewer 125 predecessors at head rather than tail. 126 127 1282007-04-12 Richard Guenther <rguenther@suse.de> (r123736) 129 130 PR tree-optimization/24689 131 PR tree-optimization/31307 132 * fold-const.c (operand_equal_p): Compare INTEGER_CST array 133 indices by value. 134 * gimplify.c (canonicalize_addr_expr): To be consistent with 135 gimplify_compound_lval only set operands two and three of 136 ARRAY_REFs if they are not gimple_min_invariant. This makes 137 it never at this place. 138 * tree-ssa-ccp.c (maybe_fold_offset_to_array_ref): Likewise. 139 1402007-04-07 H.J. Lu <hongjiu.lu@intel.com> (r123639) 141 142 * config/i386/i386.c (ix86_handle_option): Handle SSSE3. 143 1442007-03-28 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r123313) 145 146 * config.gcc: Accept barcelona as a variant of amdfam10. 147 * config/i386/i386.c (override_options): Likewise. 148 * doc/invoke.texi: Likewise. 149 1502007-03-12 Seongbae Park <seongbae.park@gmail.com> 151 152 * c-decl.c (warn_variable_length_array): New function. 153 Refactored from grokdeclarator to handle warn_vla 154 and handle unnamed array case. 155 (grokdeclarator): Refactored VLA warning case. 156 * c.opt (Wvla): New flag. 157 1582007-03-11 Ian Lance Taylor <iant@google.com> (r122831 - partial) 159 160 * tree-vrp.c (vrp_int_const_binop): Handle PLUS_EXPR and 161 the *_DIV_EXPR codes correctly with overflow infinities. 162 1632007-02-09 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> (r121763) 164 165 * config/i386/driver-i386.c: Turn on -mtune=native for AMDFAM10. 166 (bit_SSE4a): New. 167 1682007-02-08 Harsha Jagasia <harsha.jagasia@amd.com> (r121726) 169 170 * config/i386/xmmintrin.h: Make inclusion of emmintrin.h 171 conditional to __SSE2__. 172 (Entries below should have been added to first ChangeLog 173 entry for amdfam10 dated 2007-02-05) 174 * config/i386/emmintrin.h: Generate #error if __SSE2__ is not 175 defined. 176 * config/i386/pmmintrin.h: Generate #error if __SSE3__ is not 177 defined. 178 * config/i386/tmmintrin.h: Generate #error if __SSSE3__ is not 179 defined. 180 1812007-02-07 Jakub Jelinek <jakub@redhat.com> (r121687) 182 183 * config/i386/i386.c (override_options): Set PTA_SSSE3 for core2. 184 1852007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 186 187 * config/i386/athlon.md (athlon_fldxf_k8, athlon_fld_k8, 188 athlon_fstxf_k8, athlon_fst_k8, athlon_fist, athlon_fmov, 189 athlon_fadd_load, athlon_fadd_load_k8, athlon_fadd, athlon_fmul, 190 athlon_fmul_load, athlon_fmul_load_k8, athlon_fsgn, 191 athlon_fdiv_load, athlon_fdiv_load_k8, athlon_fdiv_k8, 192 athlon_fpspc_load, athlon_fpspc, athlon_fcmov_load, 193 athlon_fcmov_load_k8, athlon_fcmov_k8, athlon_fcomi_load_k8, 194 athlon_fcomi, athlon_fcom_load_k8, athlon_fcom): Added amdfam10. 195 1962007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 197 198 * config/i386/i386.md (x86_sahf_1, cmpfp_i_mixed, cmpfp_i_sse, 199 cmpfp_i_i387, cmpfp_iu_mixed, cmpfp_iu_sse, cmpfp_iu_387, 200 swapsi, swaphi_1, swapqi_1, swapdi_rex64, fix_truncsfdi_sse, 201 fix_truncdfdi_sse, fix_truncsfsi_sse, fix_truncdfsi_sse, 202 x86_fldcw_1, floatsisf2_mixed, floatsisf2_sse, floatdisf2_mixed, 203 floatdisf2_sse, floatsidf2_mixed, floatsidf2_sse, 204 floatdidf2_mixed, floatdidf2_sse, muldi3_1_rex64, mulsi3_1, 205 mulsi3_1_zext, mulhi3_1, mulqi3_1, umulqihi3_1, mulqihi3_insn, 206 umulditi3_insn, umulsidi3_insn, mulditi3_insn, mulsidi3_insn, 207 umuldi3_highpart_rex64, umulsi3_highpart_insn, 208 umulsi3_highpart_zext, smuldi3_highpart_rex64, 209 smulsi3_highpart_insn, smulsi3_highpart_zext, x86_64_shld, 210 x86_shld_1, x86_64_shrd, sqrtsf2_mixed, sqrtsf2_sse, 211 sqrtsf2_i387, sqrtdf2_mixed, sqrtdf2_sse, sqrtdf2_i387, 212 sqrtextendsfdf2_i387, sqrtxf2, sqrtextendsfxf2_i387, 213 sqrtextenddfxf2_i387): Added amdfam10_decode. 214 215 * config/i386/athlon.md (athlon_idirect_amdfam10, 216 athlon_ivector_amdfam10, athlon_idirect_load_amdfam10, 217 athlon_ivector_load_amdfam10, athlon_idirect_both_amdfam10, 218 athlon_ivector_both_amdfam10, athlon_idirect_store_amdfam10, 219 athlon_ivector_store_amdfam10): New define_insn_reservation. 220 (athlon_idirect_loadmov, athlon_idirect_movstore): Added 221 amdfam10. 222 2232007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 224 225 * config/i386/athlon.md (athlon_call_amdfam10, 226 athlon_pop_amdfam10, athlon_lea_amdfam10): New 227 define_insn_reservation. 228 (athlon_branch, athlon_push, athlon_leave_k8, athlon_imul_k8, 229 athlon_imul_k8_DI, athlon_imul_mem_k8, athlon_imul_mem_k8_DI, 230 athlon_idiv, athlon_idiv_mem, athlon_str): Added amdfam10. 231 2322007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 233 234 * config/i386/athlon.md (athlon_sseld_amdfam10, 235 athlon_mmxld_amdfam10, athlon_ssest_amdfam10, 236 athlon_mmxssest_short_amdfam10): New define_insn_reservation. 237 2382007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 239 240 * config/i386/athlon.md (athlon_sseins_amdfam10): New 241 define_insn_reservation. 242 * config/i386/i386.md (sseins): Added sseins to define_attr type 243 and define_attr unit. 244 * config/i386/sse.md: Set type attribute to sseins for insertq 245 and insertqi. 246 2472007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 248 249 * config/i386/athlon.md (sselog_load_amdfam10, sselog_amdfam10, 250 ssecmpvector_load_amdfam10, ssecmpvector_amdfam10, 251 ssecomi_load_amdfam10, ssecomi_amdfam10, 252 sseaddvector_load_amdfam10, sseaddvector_amdfam10): New 253 define_insn_reservation. 254 (ssecmp_load_k8, ssecmp, sseadd_load_k8, seadd): Added amdfam10. 255 2562007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 257 258 * config/i386/athlon.md (cvtss2sd_load_amdfam10, 259 cvtss2sd_amdfam10, cvtps2pd_load_amdfam10, cvtps2pd_amdfam10, 260 cvtsi2sd_load_amdfam10, cvtsi2ss_load_amdfam10, 261 cvtsi2sd_amdfam10, cvtsi2ss_amdfam10, cvtsd2ss_load_amdfam10, 262 cvtsd2ss_amdfam10, cvtpd2ps_load_amdfam10, cvtpd2ps_amdfam10, 263 cvtsX2si_load_amdfam10, cvtsX2si_amdfam10): New 264 define_insn_reservation. 265 266 * config/i386/sse.md (cvtsi2ss, cvtsi2ssq, cvtss2si, 267 cvtss2siq, cvttss2si, cvttss2siq, cvtsi2sd, cvtsi2sdq, 268 cvtsd2si, cvtsd2siq, cvttsd2si, cvttsd2siq, 269 cvtpd2dq, cvttpd2dq, cvtsd2ss, cvtss2sd, 270 cvtpd2ps, cvtps2pd): Added amdfam10_decode attribute. 271 2722007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 273 274 * config/i386/athlon.md (athlon_ssedivvector_amdfam10, 275 athlon_ssedivvector_load_amdfam10, athlon_ssemulvector_amdfam10, 276 athlon_ssemulvector_load_amdfam10): New define_insn_reservation. 277 (athlon_ssediv, athlon_ssediv_load_k8, athlon_ssemul, 278 athlon_ssemul_load_k8): Added amdfam10. 279 2802007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 281 282 * config/i386/i386.h (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL): New macro. 283 (x86_sse_unaligned_move_optimal): New variable. 284 285 * config/i386/i386.c (x86_sse_unaligned_move_optimal): Enable for 286 m_AMDFAM10. 287 (ix86_expand_vector_move_misalign): Add code to generate movupd/movups 288 for unaligned vector SSE double/single precision loads for AMDFAM10. 289 2902007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 291 292 * config/i386/i386.h (TARGET_AMDFAM10): New macro. 293 (TARGET_CPU_CPP_BUILTINS): Add code for amdfam10. 294 Define TARGET_CPU_DEFAULT_amdfam10. 295 (TARGET_CPU_DEFAULT_NAMES): Add amdfam10. 296 (processor_type): Add PROCESSOR_AMDFAM10. 297 298 * config/i386/i386.md: Add amdfam10 as a new cpu attribute to match 299 processor_type in config/i386/i386.h. 300 Enable imul peepholes for TARGET_AMDFAM10. 301 302 * config.gcc: Add support for --with-cpu option for amdfam10. 303 304 * config/i386/i386.c (amdfam10_cost): New variable. 305 (m_AMDFAM10): New macro. 306 (m_ATHLON_K8_AMDFAM10): New macro. 307 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 308 x86_cmove, x86_3dnow_a, x86_deep_branch, x86_use_simode_fiop, 309 x86_promote_QImode, x86_integer_DFmode_moves, 310 x86_partial_reg_dependency, x86_memory_mismatch_stall, 311 x86_accumulate_outgoing_args, x86_arch_always_fancy_math_387, 312 x86_sse_partial_reg_dependency, x86_sse_typeless_stores, 313 x86_use_ffreep, x86_use_incdec, x86_four_jump_limit, 314 x86_schedule, x86_use_bt, x86_cmpxchg16b, x86_pad_returns): 315 Enable/disable for amdfam10. 316 (override_options): Add amdfam10_cost to processor_target_table. 317 Set up PROCESSOR_AMDFAM10 for amdfam10 entry in 318 processor_alias_table. 319 (ix86_issue_rate): Add PROCESSOR_AMDFAM10. 320 (ix86_adjust_cost): Add code for amdfam10. 321 3222007-02-05 Harsha Jagasia <harsha.jagasia@amd.com> (r121625) 323 324 * config/i386/i386.opt: Add new Advanced Bit Manipulation (-mabm) 325 instruction set feature flag. Add new (-mpopcnt) flag for popcnt 326 instruction. Add new SSE4A (-msse4a) instruction set feature flag. 327 * config/i386/i386.h: Add builtin definition for SSE4A. 328 * config/i386/i386.md: Add support for ABM instructions 329 (popcnt and lzcnt). 330 * config/i386/sse.md: Add support for SSE4A instructions 331 (movntss, movntsd, extrq, insertq). 332 * config/i386/i386.c: Add support for ABM and SSE4A builtins. 333 Add -march=amdfam10 flag. 334 * config/i386/ammintrin.h: Add support for SSE4A intrinsics. 335 * doc/invoke.texi: Add documentation on flags for sse4a, abm, popcnt 336 and amdfam10. 337 * doc/extend.texi: Add documentation for SSE4A builtins. 338 3392007-01-24 Jakub Jelinek <jakub@redhat.com> (r121140) 340 341 * config/i386/i386.h (x86_cmpxchg16b): Remove const. 342 (TARGET_CMPXCHG16B): Define to x86_cmpxchg16b. 343 * config/i386/i386.c (x86_cmpxchg16b): Remove const. 344 (override_options): Add PTA_CX16 flag. Set x86_cmpxchg16b 345 for CPUs that have PTA_CX16 set. 346 3472007-01-17 Eric Christopher <echristo@apple.com> (r120846) 348 349 * config.gcc: Support core2 processor. 350 3512006-12-13 Ian Lance Taylor <iant@google.com> (r119855) 352 353 PR c++/19564 354 PR c++/19756 355 * c-typeck.c (parser_build_binary_op): Move parentheses warnings 356 to warn_about_parentheses in c-common.c. 357 * c-common.c (warn_about_parentheses): New function. 358 * c-common.h (warn_about_parentheses): Declare. 359 * doc/invoke.texi (Warning Options): Update -Wparentheses 360 description. 361 3622006-12-12 Geoffrey Keating <geoffk@apple.com> (r119820) 363 364 * mips-tdump.c: Replace CROSS_COMPILE with 365 CROSS_DIRECTORY_STRUCTURE. 366 * mips-tfile.c: Likewise. 367 * gcc.c: Likewise. 368 * configure.ac: Likewise. 369 * cppdefault.c: Likewise. 370 * Makefile.in: Likewise. 371 * config/alpha/osf.h: Likewise. 372 * config/i386/cygwin.h: Likewise. 373 * config/i386/beos-elf.h: Likewise. 374 * config/i386/nto.h: Likewise. 375 * config/svr4.h: Likewise. 376 * config/rs6000/aix.h: Likewise. 377 * config/rs6000/sysv4.h: Likewise. 378 * collect2.c: Likewise. 379 * configure: Regenerate. 380 381 * doc/tm.texi (Alignment Output): Document that ASM_OUTPUT_SKIP 382 actually takes an unsigned HOST_WIDE_INT for its second parameter. 383 3842006-12-02 H.J. Lu <hongjiu.lu@intel.com> (r119454 - partial) 385 386 PR target/30040 387 * config/i386/driver-i386.c (bit_SSSE3): New. 388 3892006-11-27 Uros Bizjak <ubizjak@gmail.com> (r119260) 390 391 * config/i386/i386.c (x86_ext_80387_constants): Add m_K8, m_CORE2 392 and m_GENERIC64. 393 3942006-11-18 Vladimir Makarov <vmakarov@redhat.com> (r118973) 395 396 * doc/invoke.texi (core2): Add item. 397 398 * config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New 399 macros. 400 (TARGET_CPU_CPP_BUILTINS): Add code for core2. 401 (TARGET_CPU_DEFAULT_generic): Change value. 402 (TARGET_CPU_DEFAULT_NAMES): Add core2. 403 (processor_type): Add new constant PROCESSOR_CORE2. 404 405 * config/i386/i386.md (cpu): Add core2. 406 407 * config/i386/i386.c (core2_cost): New initialized variable. 408 (m_CORE2): New macro. 409 (x86_use_leave, x86_push_memory, x86_movx, x86_unroll_strlen, 410 x86_deep_branch, x86_partial_reg_stall, x86_use_simode_fiop, 411 x86_use_cltd, x86_promote_QImode, x86_sub_esp_4, x86_sub_esp_8, 412 x86_add_esp_4, x86_add_esp_8, x86_integer_DFmode_moves, 413 x86_partial_reg_dependency, x86_memory_mismatch_stall, 414 x86_accumulate_outgoing_args, x86_prologue_using_move, 415 x86_epilogue_using_move, x86_arch_always_fancy_math_387, 416 x86_sse_partial_reg_dependency, x86_rep_movl_optimal, 417 x86_use_incdec, x86_four_jump_limit, x86_schedule, 418 x86_pad_returns): Add m_CORE2. 419 (override_options): Add entries for Core2. 420 (ix86_issue_rate): Add case for Core2. 421 4222006-11-07 Eric Christopher <echristo@apple.com> (r118576) 423 424 * libgcc2.c (__bswapdi2): Rename from bswapDI2. 425 (__bswapsi2): Ditto. 426 * libgcc2.h: Remove transformation of bswap routines. 427 * config/i386/i386.md (bswapsi2): New. 428 (bswapdi2): Ditto. 429 4302006-10-31 Geoffrey Keating <geoffk@apple.com> (r118360) 431 432 * coverage.c (coverage_checksum_string): Update comment. 433 * dwarf2out.c (switch_to_eh_frame_section): Update for removal 434 of get_file_function_name. 435 * cgraphunit.c (cgraph_build_static_cdtor): Update for rename 436 of get_file_function_name_long. 437 * tree.c (get_file_function_name): Rename from 438 get_file_function_name_long; improve comment; handle 'I' and 'D' 439 specially when the target has ctor/dtor support; remove special 440 handling for 'F'. 441 (get_file_function_name): Remove. 442 * tree.h (get_file_function_name): Rename from 443 get_file_function_name_long. 444 (get_file_function_name): Remove prototype. 445 4462006-10-31 Geoffrey Keating <geoffk@apple.com> (r118356) 447 448 * c-decl.c (grokdeclarator): Don't set DECL_EXTERNAL on 449 inline static functions in c99 mode. 450 451 PR 16622 452 * doc/extend.texi (Inline): Update. 453 * c-tree.h (struct language_function): Remove field 'extern_inline'. 454 * c-decl.c (current_extern_inline): Delete. 455 (pop_scope): Adjust test for an undefined nested function. 456 Add warning about undeclared inline function. 457 (diagnose_mismatched_decls): Update comments. Disallow overriding 458 of inline functions in a translation unit in C99. Allow inline 459 declarations in C99 at any time. 460 (merge_decls): Boolize variables. Handle C99 'extern inline' 461 semantics. 462 (grokdeclarator): Set DECL_EXTERNAL here for functions. Handle 463 C99 inline semantics. 464 (start_function): Don't clear current_extern_inline. Don't set 465 DECL_EXTERNAL. 466 (c_push_function_context): Don't push current_extern_inline. 467 (c_pop_function_context): Don't restore current_extern_inline. 468 469 PR 11377 470 * c-typeck.c (build_external_ref): Warn about static variables 471 used in extern inline functions. 472 * c-decl.c (start_decl): Warn about static variables declared 473 in extern inline functions. 474 4752006-10-27 Vladimir Makarov <vmakarov@redhat.com> (r118090) 476 477 * config/i386/i386.h (TARGET_GEODE): 478 (TARGET_CPU_CPP_BUILTINS): Add code for geode. 479 (TARGET_CPU_DEFAULT_geode): New macro. 480 (TARGET_CPU_DEFAULT_k6, TARGET_CPU_DEFAULT_k6_2, 481 TARGET_CPU_DEFAULT_k6_3, TARGET_CPU_DEFAULT_athlon, 482 TARGET_CPU_DEFAULT_athlon_sse, TARGET_CPU_DEFAULT_k8, 483 TARGET_CPU_DEFAULT_pentium_m, TARGET_CPU_DEFAULT_prescott, 484 TARGET_CPU_DEFAULT_nocona, TARGET_CPU_DEFAULT_generic): Increase 485 the macro values. 486 (TARGET_CPU_DEFAULT_NAMES): Add geode. 487 (processor_type): Add PROCESSOR_GEODE. 488 489 * config/i386/i386.md: Include geode.md. 490 (cpu): Add geode. 491 492 * config/i386/i386.c (geode_cost): New initialized global 493 variable. 494 (m_GEODE, m_K6_GEODE): New macros. 495 (x86_use_leave, x86_push_memory, x86_deep_branch, x86_use_sahf, 496 x86_use_himode_fiop, x86_promote_QImode, x86_add_esp_4, 497 x86_add_esp_8, x86_rep_movl_optimal, x86_ext_80387_constants, 498 x86_schedule): Use m_K6_GEODE instead of m_K6. 499 (x86_movx, x86_cmove): Set up m_GEODE. 500 (x86_integer_DFmode_moves): Clear m_GEODE. 501 (processor_target_table): Add entry for geode. 502 (processor_alias_table): Ditto. 503 504 * config/i386/geode.md: New file. 505 506 * doc/invoke.texi: Add entry about geode processor. 507 5082006-10-24 Richard Guenther <rguenther@suse.de> (r118001) 509 510 PR middle-end/28796 511 * builtins.c (fold_builtin_classify): Use HONOR_INFINITIES 512 and HONOR_NANS instead of MODE_HAS_INFINITIES and MODE_HAS_NANS 513 for deciding optimizations in consistency with fold-const.c 514 (fold_builtin_unordered_cmp): Likewise. 515 5162006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117958) 517 518 * config.gcc (i[34567]86-*-*): Add tmmintrin.h to extra_headers. 519 (x86_64-*-*): Likewise. 520 521 * config/i386/i386.c (pta_flags): Add PTA_SSSE3. 522 (override_options): Check SSSE3. 523 (ix86_builtins): Add IX86_BUILTIN_PHADDW, IX86_BUILTIN_PHADDD, 524 IX86_BUILTIN_PHADDSW, IX86_BUILTIN_PHSUBW, IX86_BUILTIN_PHSUBD, 525 IX86_BUILTIN_PHSUBSW, IX86_BUILTIN_PMADDUBSW, 526 IX86_BUILTIN_PMULHRSW, IX86_BUILTIN_PSHUFB, 527 IX86_BUILTIN_PSIGNB, IX86_BUILTIN_PSIGNW, IX86_BUILTIN_PSIGND, 528 IX86_BUILTIN_PALIGNR, IX86_BUILTIN_PABSB, IX86_BUILTIN_PABSW, 529 IX86_BUILTIN_PABSD, IX86_BUILTIN_PHADDW128, 530 IX86_BUILTIN_PHADDD128, IX86_BUILTIN_PHADDSW128, 531 IX86_BUILTIN_PHSUBW128, IX86_BUILTIN_PHSUBD128, 532 IX86_BUILTIN_PHSUBSW128, IX86_BUILTIN_PMADDUBSW128, 533 IX86_BUILTIN_PMULHRSW128, IX86_BUILTIN_PSHUFB128, 534 IX86_BUILTIN_PSIGNB128, IX86_BUILTIN_PSIGNW128, 535 IX86_BUILTIN_PSIGND128, IX86_BUILTIN_PALIGNR128, 536 IX86_BUILTIN_PABSB128, IX86_BUILTIN_PABSW128 and 537 IX86_BUILTIN_PABSD128. 538 (bdesc_2arg): Add SSSE3. 539 (bdesc_1arg): Likewise. 540 (ix86_init_mmx_sse_builtins): Support SSSE3. 541 (ix86_expand_builtin): Likewise. 542 * config/i386/i386.h (TARGET_CPU_CPP_BUILTINS): Likewise. 543 544 * config/i386/i386.md (UNSPEC_PSHUFB): New. 545 (UNSPEC_PSIGN): Likewise. 546 (UNSPEC_PALIGNR): Likewise. 547 Include mmx.md before sse.md. 548 549 * config/i386/i386.opt: Add -mssse3. 550 551 * config/i386/sse.md (ssse3_phaddwv8hi3): New pattern for SSSE3. 552 (ssse3_phaddwv4hi3): Likewise. 553 (ssse3_phadddv4si3): Likewise. 554 (ssse3_phadddv2si3): Likewise. 555 (ssse3_phaddswv8hi3): Likewise. 556 (ssse3_phaddswv4hi3): Likewise. 557 (ssse3_phsubwv8hi3): Likewise. 558 (ssse3_phsubwv4hi3): Likewise. 559 (ssse3_phsubdv4si3): Likewise. 560 (ssse3_phsubdv2si3): Likewise. 561 (ssse3_phsubswv8hi3): Likewise. 562 (ssse3_phsubswv4hi3): Likewise. 563 (ssse3_pmaddubswv8hi3): Likewise. 564 (ssse3_pmaddubswv4hi3): Likewise. 565 (ssse3_pmulhrswv8hi3): Likewise. 566 (ssse3_pmulhrswv4hi3): Likewise. 567 (ssse3_pshufbv16qi3): Likewise. 568 (ssse3_pshufbv8qi3): Likewise. 569 (ssse3_psign<mode>3): Likewise. 570 (ssse3_psign<mode>3): Likewise. 571 (ssse3_palignrti): Likewise. 572 (ssse3_palignrdi): Likewise. 573 (abs<mode>2): Likewise. 574 (abs<mode>2): Likewise. 575 576 * config/i386/tmmintrin.h: New file. 577 578 * doc/extend.texi: Document SSSE3 built-in functions. 579 580 * doc/invoke.texi: Document -mssse3/-mno-ssse3 switches. 581 5822006-10-22 H.J. Lu <hongjiu.lu@intel.com> (r117959) 583 584 * config/i386/tmmintrin.h: Remove the duplicated content. 585 5862006-10-21 Richard Guenther <rguenther@suse.de> (r117932) 587 588 PR tree-optimization/3511 589 * tree-ssa-pre.c (phi_translate): Fold CALL_EXPRs that 590 got new invariant arguments during PHI translation. 591 5922006-10-21 Richard Guenther <rguenther@suse.de> (r117929) 593 594 * builtins.c (fold_builtin_classify): Fix typo. 595 5962006-09-07 Eric Christopher <echristo@apple.com> (r118361) 597 Falk Hueffner <falk@debian.org> 598 599 * doc/extend.texi (__builtin_bswap32): Document. 600 (__builtin_bswap64): Ditto. 601 * doc/libgcc.texi (bswapsi2): Document. 602 (bswapdi2): Ditto. 603 * doc/rtl.texi (bswap): Document. 604 * optabs.c (expand_unop): Don't widen a bswap. 605 (init_optabs): Init bswap. Set libfuncs explicitly 606 for bswapsi2 and bswapdi2. 607 * optabs.h (OTI_bswap): New. 608 (bswap_optab): Ditto. 609 * genopinit.c (optabs): Handle bswap_optab. 610 * tree.h (tree_index): Add TI_UINT32_TYPE and 611 TI_UINT64_TYPE. 612 (uint32_type_node): New. 613 (uint64_type_node): Ditto. 614 * tree.c (build_common_tree_nodes_2): Initialize 615 uint32_type_node and uint64_type_node. 616 * builtins.c (expand_builtin_bswap): New. 617 (expand_builtin): Call. 618 (fold_builtin_bswap): New. 619 (fold_builtin_1): Call. 620 * fold-const.c (tree_expr_nonnegative_p): Return true 621 for bswap. 622 * builtin-types.def (BT_UINT32): New. 623 (BT_UINT64): Ditto. 624 (BT_FN_UINT32_UINT32): Ditto. 625 (BT_FN_UINT64_UINT64): Ditto. 626 * builtins.def (BUILT_IN_BSWAP32): New. 627 (BUILT_IN_BSWAP64): Ditto. 628 * rtl.def (BSWAP): New. 629 * genattrtab.c (check_attr_value): New. 630 * libgcc2.c (__bswapSI2): New. 631 (__bswapDI2): Ditto. 632 * libgcc2.h (__bswapSI2): Declare. 633 (__bswapDI2): Ditto. 634 * mklibgcc.in (lib2funcs): Add _bswapsi2 and _bswapdi2. 635 * simplify-rtx.c (simplify_const_unary_operation): Return 636 0 for BSWAP. 637 * libgcc-std.ver (__bwapsi2): Add. 638 (__bswapdi2): Ditto. 639 * reload1.c (eliminate_regs_1): Add bswap. 640 (elimination_effects): Ditto. 641 * config/i386/i386.h (x86_bswap): New. 642 (TARGET_BSWAP): Use. 643 * config/i386/i386.c (x86_bswap): Set. 644