i386.h revision 38889
133965Sjdp/* i386-opcode.h -- Intel 80386 opcode table 238889Sjdp Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation. 333965Sjdp 433965SjdpThis file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 533965Sjdp 633965SjdpThis program is free software; you can redistribute it and/or modify 733965Sjdpit under the terms of the GNU General Public License as published by 833965Sjdpthe Free Software Foundation; either version 2 of the License, or 933965Sjdp(at your option) any later version. 1033965Sjdp 1133965SjdpThis program is distributed in the hope that it will be useful, 1233965Sjdpbut WITHOUT ANY WARRANTY; without even the implied warranty of 1333965SjdpMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1433965SjdpGNU General Public License for more details. 1533965Sjdp 1633965SjdpYou should have received a copy of the GNU General Public License 1733965Sjdpalong with this program; if not, write to the Free Software 1833965SjdpFoundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 1933965Sjdp 2033965Sjdp/* The NON_BROKEN_OPCODES cases use the operands in the reverse order 2133965Sjdp from that documented in the Intel manuals. The opcode values are 2233965Sjdp such that they actually generate different instructions. These 2333965Sjdp values must not be changed, as they are the values generated by the 2433965Sjdp UnixWare assembler, and possibly other ix86 assemblers. */ 2533965Sjdp 2633965Sjdpstatic const template i386_optab[] = { 2733965Sjdp 2833965Sjdp#define _ None 2933965Sjdp/* move instructions */ 3033965Sjdp#define MOV_AX_DISP32 0xa0 3133965Sjdp{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } }, 3233965Sjdp{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } }, 3333965Sjdp{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } }, 3433965Sjdp{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } }, 3538889Sjdp/* The next instruction accepts WordReg so that `movl %gs,%esi' can be 3638889Sjdp used to move a segment register to a 32 bit register without using 3738889Sjdp a size prefix. This will set the upper 16 bits of the 32 bit 3838889Sjdp register to an implementation defined value (on the Pentium Pro, 3938889Sjdp the implementation defined value is zero). */ 4038889Sjdp{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, 4133965Sjdp/* move to/from control debug registers */ 4233965Sjdp{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} }, 4333965Sjdp{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} }, 4433965Sjdp{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} }, 4533965Sjdp 4633965Sjdp/* move with sign extend */ 4733965Sjdp/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 4833965Sjdp conflict with the "movs" string move instruction. Thus, 4933965Sjdp {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, 5033965Sjdp is not kosher; we must seperate the two instructions. */ 5133965Sjdp{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} }, 5233965Sjdp{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} }, 5333965Sjdp{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, 5433965Sjdp 5533965Sjdp/* move with zero extend */ 5633965Sjdp{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, 5733965Sjdp{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, 5833965Sjdp 5933965Sjdp/* push instructions */ 6033965Sjdp{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } }, 6133965Sjdp{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } }, 6233965Sjdp{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} }, 6333965Sjdp{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} }, 6433965Sjdp{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } }, 6533965Sjdp{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } }, 6633965Sjdp/* push all */ 6733965Sjdp{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } }, 6833965Sjdp 6933965Sjdp/* pop instructions */ 7033965Sjdp{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } }, 7133965Sjdp{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } }, 7233965Sjdp#define POP_SEG_SHORT 0x7 7333965Sjdp{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } }, 7433965Sjdp{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } }, 7533965Sjdp/* pop all */ 7633965Sjdp{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } }, 7733965Sjdp 7833965Sjdp/* xchg exchange instructions 7933965Sjdp xchg commutes: we allow both operand orders */ 8033965Sjdp{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } }, 8133965Sjdp{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } }, 8233965Sjdp{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 8333965Sjdp{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } }, 8433965Sjdp 8533965Sjdp/* in/out from ports */ 8633965Sjdp{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } }, 8733965Sjdp{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } }, 8833965Sjdp{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } }, 8933965Sjdp{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } }, 9033965Sjdp{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } }, 9133965Sjdp{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } }, 9233965Sjdp{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } }, 9333965Sjdp{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } }, 9433965Sjdp 9533965Sjdp/* load effective address */ 9633965Sjdp{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } }, 9733965Sjdp 9833965Sjdp/* load segment registers from memory */ 9933965Sjdp{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} }, 10033965Sjdp{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} }, 10133965Sjdp{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} }, 10233965Sjdp{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} }, 10333965Sjdp{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} }, 10433965Sjdp 10533965Sjdp/* flags register instructions */ 10633965Sjdp{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} }, 10733965Sjdp{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} }, 10833965Sjdp{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} }, 10933965Sjdp{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} }, 11033965Sjdp{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} }, 11133965Sjdp{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} }, 11233965Sjdp{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} }, 11333965Sjdp{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} }, 11433965Sjdp{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} }, 11533965Sjdp{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} }, 11633965Sjdp{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} }, 11733965Sjdp{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} }, 11833965Sjdp{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} }, 11933965Sjdp{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} }, 12033965Sjdp{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} }, 12133965Sjdp{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} }, 12233965Sjdp 12333965Sjdp{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 12433965Sjdp{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} }, 12533965Sjdp{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} }, 12633965Sjdp{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} }, 12733965Sjdp 12833965Sjdp{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} }, 12933965Sjdp{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} }, 13033965Sjdp 13133965Sjdp{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 13233965Sjdp{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} }, 13333965Sjdp{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} }, 13433965Sjdp{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} }, 13533965Sjdp 13633965Sjdp{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} }, 13733965Sjdp{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} }, 13833965Sjdp 13933965Sjdp{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 14033965Sjdp{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} }, 14133965Sjdp{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} }, 14233965Sjdp{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} }, 14333965Sjdp 14433965Sjdp{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 14533965Sjdp{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} }, 14633965Sjdp{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} }, 14733965Sjdp{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} }, 14833965Sjdp 14933965Sjdp{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} }, 15033965Sjdp{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} }, 15133965Sjdp{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} }, 15233965Sjdp{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} }, 15333965Sjdp 15433965Sjdp{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 15533965Sjdp{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} }, 15633965Sjdp{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} }, 15733965Sjdp{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} }, 15833965Sjdp 15933965Sjdp{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 16033965Sjdp{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} }, 16133965Sjdp{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} }, 16233965Sjdp{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} }, 16333965Sjdp 16433965Sjdp{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 16533965Sjdp{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} }, 16633965Sjdp{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} }, 16733965Sjdp{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} }, 16833965Sjdp 16933965Sjdp/* iclr with 1 operand is really xor with 2 operands. */ 17033965Sjdp{"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } }, 17133965Sjdp 17233965Sjdp{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 17333965Sjdp{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} }, 17433965Sjdp{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} }, 17533965Sjdp{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} }, 17633965Sjdp 17733965Sjdp{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} }, 17833965Sjdp{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} }, 17933965Sjdp 18033965Sjdp{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} }, 18133965Sjdp{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} }, 18233965Sjdp{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} }, 18333965Sjdp{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} }, 18433965Sjdp{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} }, 18533965Sjdp{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} }, 18633965Sjdp 18733965Sjdp/* conversion insns */ 18833965Sjdp/* conversion: intel naming */ 18933965Sjdp{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, 19033965Sjdp{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, 19133965Sjdp{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, 19233965Sjdp{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, 19333965Sjdp/* att naming */ 19433965Sjdp{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, 19533965Sjdp{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, 19633965Sjdp{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, 19733965Sjdp{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, 19833965Sjdp 19933965Sjdp/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 20033965Sjdp expanding 64-bit multiplies, and *cannot* be selected to accomplish 20133965Sjdp 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 20233965Sjdp These multiplies can only be selected with single operand forms. */ 20333965Sjdp{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} }, 20433965Sjdp{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} }, 20533965Sjdp 20633965Sjdp 20733965Sjdp 20833965Sjdp 20933965Sjdp/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. 21033965Sjdp These instructions are exceptions: 'imul $2, %eax, %ecx' would put 21133965Sjdp '%eax' in the reg field and '%ecx' in the regmem field if we did not 21233965Sjdp switch them. */ 21333965Sjdp{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 21433965Sjdp{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} }, 21533965Sjdp{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} }, 21633965Sjdp/* 21733965Sjdp imul with 2 operands mimicks imul with 3 by puting register both 21833965Sjdp in i.rm.reg & i.rm.regmem fields 21933965Sjdp*/ 22033965Sjdp{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} }, 22133965Sjdp{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} }, 22233965Sjdp{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} }, 22333965Sjdp{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} }, 22433965Sjdp{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} }, 22533965Sjdp{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} }, 22633965Sjdp 22733965Sjdp{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} }, 22833965Sjdp{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} }, 22933965Sjdp{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 23033965Sjdp{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} }, 23133965Sjdp 23233965Sjdp{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} }, 23333965Sjdp{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} }, 23433965Sjdp{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 23533965Sjdp{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} }, 23633965Sjdp 23733965Sjdp{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} }, 23833965Sjdp{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} }, 23933965Sjdp{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 24033965Sjdp{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} }, 24133965Sjdp 24233965Sjdp{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} }, 24333965Sjdp{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} }, 24433965Sjdp{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 24533965Sjdp{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} }, 24633965Sjdp 24733965Sjdp{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, 24833965Sjdp{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, 24933965Sjdp{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 25033965Sjdp{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, 25133965Sjdp{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, 25233965Sjdp{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, 25333965Sjdp{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 25433965Sjdp{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, 25533965Sjdp 25633965Sjdp{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, 25733965Sjdp{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, 25833965Sjdp{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} }, 25933965Sjdp 26033965Sjdp{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} }, 26133965Sjdp{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} }, 26233965Sjdp{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 26333965Sjdp{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} }, 26433965Sjdp 26533965Sjdp{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, 26633965Sjdp{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, 26733965Sjdp{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} }, 26833965Sjdp 26933965Sjdp{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} }, 27033965Sjdp{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} }, 27133965Sjdp{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 27233965Sjdp{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} }, 27333965Sjdp 27433965Sjdp/* control transfer instructions */ 27533965Sjdp#define CALL_PC_RELATIVE 0xe8 27633965Sjdp{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} }, 27733965Sjdp{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} }, 27833965Sjdp{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} }, 27933965Sjdp#define CALL_FAR_IMMEDIATE 0x9a 28033965Sjdp{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} }, 28133965Sjdp{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} }, 28233965Sjdp{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} }, 28333965Sjdp 28433965Sjdp#define JUMP_PC_RELATIVE 0xeb 28533965Sjdp{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} }, 28633965Sjdp{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} }, 28733965Sjdp#define JUMP_FAR_IMMEDIATE 0xea 28833965Sjdp{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} }, 28933965Sjdp{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} }, 29033965Sjdp 29133965Sjdp{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} }, 29233965Sjdp{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} }, 29333965Sjdp{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} }, 29433965Sjdp{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} }, 29533965Sjdp{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} }, 29633965Sjdp{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} }, 29733965Sjdp{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} }, 29833965Sjdp{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} }, 29933965Sjdp{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} }, 30033965Sjdp{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} }, 30133965Sjdp{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} }, 30233965Sjdp{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} }, 30333965Sjdp 30433965Sjdp/* conditional jumps */ 30533965Sjdp{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} }, 30633965Sjdp 30733965Sjdp{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} }, 30833965Sjdp 30933965Sjdp{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} }, 31033965Sjdp{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} }, 31133965Sjdp{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} }, 31233965Sjdp 31333965Sjdp{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} }, 31433965Sjdp{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} }, 31533965Sjdp{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} }, 31633965Sjdp 31733965Sjdp{"je", 1, 0x74, _, Jump, { Disp, 0, 0} }, 31833965Sjdp{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} }, 31933965Sjdp 32033965Sjdp{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} }, 32133965Sjdp{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} }, 32233965Sjdp 32333965Sjdp{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} }, 32433965Sjdp{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} }, 32533965Sjdp 32633965Sjdp{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} }, 32733965Sjdp{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} }, 32833965Sjdp 32933965Sjdp{"js", 1, 0x78, _, Jump, { Disp, 0, 0} }, 33033965Sjdp 33133965Sjdp{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} }, 33233965Sjdp 33333965Sjdp{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} }, 33433965Sjdp{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} }, 33533965Sjdp 33633965Sjdp{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} }, 33733965Sjdp{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} }, 33833965Sjdp 33933965Sjdp{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} }, 34033965Sjdp{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} }, 34133965Sjdp 34233965Sjdp{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} }, 34333965Sjdp{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} }, 34433965Sjdp 34533965Sjdp{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} }, 34633965Sjdp{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} }, 34733965Sjdp 34833965Sjdp{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} }, 34933965Sjdp{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} }, 35033965Sjdp 35133965Sjdp#define IS_JUMP_ON_CX_ZERO(o) \ 35233965Sjdp (o == 0xe3) 35333965Sjdp 35438889Sjdp/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ 35533965Sjdp{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} }, 35633965Sjdp{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} }, 35733965Sjdp 35833965Sjdp#define IS_LOOP_ECX_TIMES(o) \ 35933965Sjdp (o == 0xe2 || o == 0xe1 || o == 0xe0) 36033965Sjdp 36133965Sjdp{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} }, 36233965Sjdp 36333965Sjdp{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, 36433965Sjdp{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, 36533965Sjdp 36633965Sjdp{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, 36733965Sjdp{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, 36833965Sjdp 36933965Sjdp/* set byte on flag instructions */ 37033965Sjdp{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} }, 37133965Sjdp 37233965Sjdp{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} }, 37333965Sjdp 37433965Sjdp{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 37533965Sjdp{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 37633965Sjdp{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 37733965Sjdp 37833965Sjdp{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 37933965Sjdp{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 38033965Sjdp{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 38133965Sjdp 38233965Sjdp{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, 38333965Sjdp{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, 38433965Sjdp 38533965Sjdp{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, 38633965Sjdp{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, 38733965Sjdp 38833965Sjdp{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, 38933965Sjdp{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, 39033965Sjdp 39133965Sjdp{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, 39233965Sjdp{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, 39333965Sjdp 39433965Sjdp{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} }, 39533965Sjdp 39633965Sjdp{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} }, 39733965Sjdp 39833965Sjdp{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, 39933965Sjdp{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, 40033965Sjdp 40133965Sjdp{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, 40233965Sjdp{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, 40333965Sjdp 40433965Sjdp{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, 40533965Sjdp{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, 40633965Sjdp 40733965Sjdp{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, 40833965Sjdp{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, 40933965Sjdp 41033965Sjdp{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, 41133965Sjdp{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, 41233965Sjdp 41333965Sjdp{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, 41433965Sjdp{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, 41533965Sjdp 41633965Sjdp#define IS_STRING_INSTRUCTION(o) \ 41733965Sjdp ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ 41833965Sjdp (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ 41933965Sjdp (o) == 0xd7) 42033965Sjdp 42133965Sjdp/* string manipulation */ 42233965Sjdp{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, 42333965Sjdp{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, 42433965Sjdp{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} }, 42533965Sjdp{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} }, 42633965Sjdp{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, 42733965Sjdp{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, 42833965Sjdp{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, 42933965Sjdp{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, 43033965Sjdp{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, 43133965Sjdp{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, 43233965Sjdp{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, 43333965Sjdp{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, 43433965Sjdp{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} }, 43533965Sjdp 43633965Sjdp/* bit manipulation */ 43733965Sjdp{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, 43833965Sjdp{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, 43933965Sjdp{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} }, 44033965Sjdp{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} }, 44133965Sjdp{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} }, 44233965Sjdp{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} }, 44333965Sjdp{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} }, 44433965Sjdp{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} }, 44533965Sjdp{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} }, 44633965Sjdp{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} }, 44733965Sjdp 44833965Sjdp/* interrupts & op. sys insns */ 44933965Sjdp/* See gas/config/tc-i386.c for conversion of 'int $3' into the special 45033965Sjdp int 3 insn. */ 45133965Sjdp#define INT_OPCODE 0xcd 45233965Sjdp#define INT3_OPCODE 0xcc 45333965Sjdp{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} }, 45433965Sjdp{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} }, 45533965Sjdp{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} }, 45633965Sjdp{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} }, 45733965Sjdp{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} }, 45833965Sjdp/* i386sl, i486sl, later 486, and Pentium */ 45933965Sjdp{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} }, 46033965Sjdp 46133965Sjdp{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} }, 46233965Sjdp{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} }, 46333965Sjdp 46433965Sjdp{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} }, 46533965Sjdp{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, 46633965Sjdp/* nop is actually 'xchgl %eax, %eax' */ 46733965Sjdp{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} }, 46833965Sjdp 46933965Sjdp/* protection control */ 47033965Sjdp{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} }, 47133965Sjdp{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 47233965Sjdp{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} }, 47333965Sjdp{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} }, 47433965Sjdp{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} }, 47533965Sjdp{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} }, 47633965Sjdp{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 47733965Sjdp{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} }, 47833965Sjdp 47933965Sjdp{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} }, 48033965Sjdp{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} }, 48133965Sjdp{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} }, 48233965Sjdp{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} }, 48333965Sjdp{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} }, 48433965Sjdp 48533965Sjdp{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} }, 48633965Sjdp{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} }, 48733965Sjdp 48833965Sjdp/* floating point instructions */ 48933965Sjdp 49033965Sjdp/* load */ 49133965Sjdp{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 49233965Sjdp{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */ 49333965Sjdp{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */ 49433965Sjdp{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 49533965Sjdp{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */ 49633965Sjdp{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */ 49733965Sjdp{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ 49833965Sjdp{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ 49933965Sjdp{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */ 50033965Sjdp{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */ 50133965Sjdp 50233965Sjdp/* store (no pop) */ 50333965Sjdp{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 50433965Sjdp{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ 50533965Sjdp{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ 50633965Sjdp{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 50733965Sjdp{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ 50833965Sjdp{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ 50933965Sjdp 51033965Sjdp/* store (with pop) */ 51133965Sjdp{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 51233965Sjdp{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ 51333965Sjdp{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ 51433965Sjdp{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 51533965Sjdp{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ 51633965Sjdp{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ 51733965Sjdp{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ 51833965Sjdp{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ 51933965Sjdp{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */ 52033965Sjdp{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */ 52133965Sjdp 52233965Sjdp/* exchange %st<n> with %st0 */ 52333965Sjdp{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} }, 52433965Sjdp{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */ 52533965Sjdp 52633965Sjdp/* comparison (without pop) */ 52733965Sjdp{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, 52833965Sjdp{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ 52938889Sjdp{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ 53033965Sjdp{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ 53133965Sjdp{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, 53238889Sjdp{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ 53333965Sjdp 53433965Sjdp/* comparison (with pop) */ 53533965Sjdp{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, 53633965Sjdp{"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} }, /* fcomp %st, %st(1) */ 53733965Sjdp{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ 53838889Sjdp{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ 53933965Sjdp{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ 54033965Sjdp{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, 54138889Sjdp{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ 54233965Sjdp{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ 54333965Sjdp 54433965Sjdp/* unordered comparison (with pop) */ 54533965Sjdp{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} }, 54633965Sjdp{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} }, 54733965Sjdp{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ 54833965Sjdp 54933965Sjdp{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */ 55033965Sjdp{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */ 55133965Sjdp 55233965Sjdp/* load constants into %st0 */ 55333965Sjdp{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */ 55433965Sjdp{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */ 55533965Sjdp{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */ 55633965Sjdp{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */ 55733965Sjdp{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */ 55833965Sjdp{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */ 55933965Sjdp{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */ 56033965Sjdp 56133965Sjdp/* arithmetic */ 56233965Sjdp 56333965Sjdp/* add */ 56433965Sjdp{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} }, 56533965Sjdp{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 56633965Sjdp{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */ 56733965Sjdp{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} }, 56833965Sjdp{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 56933965Sjdp{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 57033965Sjdp{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ 57133965Sjdp{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} }, 57233965Sjdp{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} }, 57333965Sjdp{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} }, 57433965Sjdp{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} }, 57533965Sjdp 57633965Sjdp/* sub */ 57733965Sjdp/* Note: intel has decided that certain of these operations are reversed 57833965Sjdp in assembler syntax. */ 57933965Sjdp{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} }, 58033965Sjdp{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 58133965Sjdp#ifdef NON_BROKEN_OPCODES 58233965Sjdp{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 58333965Sjdp#else 58433965Sjdp{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 58533965Sjdp#endif 58633965Sjdp{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} }, 58733965Sjdp{"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} }, 58833965Sjdp{"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 58933965Sjdp#ifdef NON_BROKEN_OPCODES 59033965Sjdp{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 59133965Sjdp{"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, 59233965Sjdp#else 59333965Sjdp{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 59433965Sjdp{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, 59533965Sjdp#endif 59633965Sjdp{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} }, 59733965Sjdp{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} }, 59833965Sjdp{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} }, 59933965Sjdp{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} }, 60033965Sjdp 60133965Sjdp/* sub reverse */ 60233965Sjdp{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} }, 60333965Sjdp{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 60433965Sjdp#ifdef NON_BROKEN_OPCODES 60533965Sjdp{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 60633965Sjdp#else 60733965Sjdp{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 60833965Sjdp#endif 60933965Sjdp{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} }, 61033965Sjdp{"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} }, 61133965Sjdp{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 61233965Sjdp#ifdef NON_BROKEN_OPCODES 61333965Sjdp{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 61433965Sjdp{"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, 61533965Sjdp#else 61633965Sjdp{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 61733965Sjdp{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, 61833965Sjdp#endif 61933965Sjdp{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} }, 62033965Sjdp{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} }, 62133965Sjdp{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} }, 62233965Sjdp{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} }, 62333965Sjdp 62433965Sjdp/* mul */ 62533965Sjdp{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} }, 62633965Sjdp{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 62733965Sjdp{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} }, 62833965Sjdp{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} }, 62933965Sjdp{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 63033965Sjdp{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 63133965Sjdp{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} }, 63233965Sjdp{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} }, 63333965Sjdp{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} }, 63433965Sjdp{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} }, 63533965Sjdp{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} }, 63633965Sjdp 63733965Sjdp/* div */ 63833965Sjdp/* Note: intel has decided that certain of these operations are reversed 63933965Sjdp in assembler syntax. */ 64033965Sjdp{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} }, 64133965Sjdp{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 64233965Sjdp#ifdef NON_BROKEN_OPCODES 64333965Sjdp{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 64433965Sjdp#else 64533965Sjdp{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 64633965Sjdp#endif 64733965Sjdp{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} }, 64833965Sjdp{"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} }, 64933965Sjdp{"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 65033965Sjdp#ifdef NON_BROKEN_OPCODES 65133965Sjdp{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 65233965Sjdp{"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, 65333965Sjdp#else 65433965Sjdp{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 65533965Sjdp{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, 65633965Sjdp#endif 65733965Sjdp{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} }, 65833965Sjdp{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} }, 65933965Sjdp{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} }, 66033965Sjdp{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} }, 66133965Sjdp 66233965Sjdp/* div reverse */ 66333965Sjdp{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} }, 66433965Sjdp{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 66533965Sjdp#ifdef NON_BROKEN_OPCODES 66633965Sjdp{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 66733965Sjdp#else 66833965Sjdp{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 66933965Sjdp#endif 67033965Sjdp{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} }, 67133965Sjdp{"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} }, 67233965Sjdp{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 67333965Sjdp#ifdef NON_BROKEN_OPCODES 67433965Sjdp{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 67533965Sjdp{"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, 67633965Sjdp#else 67733965Sjdp{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 67833965Sjdp{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, 67933965Sjdp#endif 68033965Sjdp{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} }, 68133965Sjdp{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} }, 68233965Sjdp{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} }, 68333965Sjdp{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} }, 68433965Sjdp 68533965Sjdp{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} }, 68633965Sjdp{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} }, 68733965Sjdp{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} }, 68833965Sjdp{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} }, 68933965Sjdp{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} }, 69033965Sjdp{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} }, 69133965Sjdp{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} }, 69233965Sjdp{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} }, 69333965Sjdp{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} }, 69433965Sjdp{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} }, 69533965Sjdp{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} }, 69633965Sjdp{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} }, 69733965Sjdp{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} }, 69833965Sjdp{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} }, 69933965Sjdp{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} }, 70033965Sjdp{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} }, 70133965Sjdp 70233965Sjdp{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} }, 70333965Sjdp{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} }, 70433965Sjdp 70533965Sjdp/* processor control */ 70638889Sjdp{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} }, 70738889Sjdp{"finit", 0, 0xdbe3, _, FWait|NoModrm, { 0, 0, 0} }, 70838889Sjdp{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} }, 70938889Sjdp{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} }, 71038889Sjdp{"fstcw", 1, 0xd9, 7, FWait|Modrm, { Mem, 0, 0} }, 71138889Sjdp{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} }, 71238889Sjdp{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} }, 71338889Sjdp{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} }, 71438889Sjdp{"fstsw", 1, 0xdfe0, _, FWait|NoModrm, { Acc, 0, 0} }, 71538889Sjdp{"fstsw", 1, 0xdd, 7, FWait|Modrm, { Mem, 0, 0} }, 71638889Sjdp{"fstsw", 0, 0xdfe0, _, FWait|NoModrm, { 0, 0, 0} }, 71738889Sjdp{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} }, 71838889Sjdp{"fclex", 0, 0xdbe2, _, FWait|NoModrm, { 0, 0, 0} }, 71938889Sjdp{"fnstenv",1, 0xd9, 6, Modrm, { Mem, 0, 0} }, 72038889Sjdp{"fstenv", 1, 0xd9, 6, FWait|Modrm, { Mem, 0, 0} }, 72138889Sjdp{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} }, 72238889Sjdp{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} }, 72338889Sjdp{"fsave", 1, 0xdd, 6, FWait|Modrm, { Mem, 0, 0} }, 72438889Sjdp{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} }, 72538889Sjdp/* Short forms of fldenv, fstenv use data size prefix. (At least I 72638889Sjdp think so. The PentPro prog ref I have says address size in one 72738889Sjdp place, operand size elsewhere). FIXME: Are these the right names? */ 72838889Sjdp{"fnstenvs",1, 0xd9, 6, Modrm|Data16, { Mem, 0, 0} }, 72938889Sjdp{"fstenvs", 1, 0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} }, 73038889Sjdp{"fldenvs", 1, 0xd9, 4, Modrm|Data16, { Mem, 0, 0} }, 73133965Sjdp 73238889Sjdp{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} }, 73333965Sjdp/* P6:free st(i), pop st */ 73438889Sjdp{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} }, 73538889Sjdp{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} }, 73638889Sjdp#define FWAIT_OPCODE 0x9b 73738889Sjdp{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, 73833965Sjdp 73933965Sjdp/* 74033965Sjdp opcode prefixes; we allow them as seperate insns too 74133965Sjdp (see prefix table below) 74233965Sjdp*/ 74333965Sjdp{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} }, 74433965Sjdp{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} }, 74533965Sjdp{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} }, 74633965Sjdp{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} }, 74733965Sjdp{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} }, 74833965Sjdp{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} }, 74933965Sjdp{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} }, 75033965Sjdp{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} }, 75133965Sjdp{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} }, 75233965Sjdp{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} }, 75333965Sjdp{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} }, 75433965Sjdp{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 75533965Sjdp{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 75633965Sjdp{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 75733965Sjdp{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, 75833965Sjdp{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, 75933965Sjdp 76033965Sjdp/* 486 extensions */ 76133965Sjdp 76233965Sjdp{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } }, 76333965Sjdp{"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 76433965Sjdp{"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 76533965Sjdp{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} }, 76633965Sjdp{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} }, 76733965Sjdp{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} }, 76833965Sjdp 76933965Sjdp/* 586 and late 486 extensions */ 77033965Sjdp{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} }, 77133965Sjdp 77233965Sjdp/* Pentium extensions */ 77333965Sjdp{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} }, 77433965Sjdp{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} }, 77533965Sjdp{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} }, 77633965Sjdp{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} }, 77733965Sjdp 77833965Sjdp/* Pentium Pro extensions */ 77933965Sjdp{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} }, 78033965Sjdp 78138889Sjdp{"ud2", 0, 0x0f0b, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */ 78233965Sjdp 78333965Sjdp{"cmovo", 2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 78433965Sjdp{"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 78533965Sjdp{"cmovb", 2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 78633965Sjdp{"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 78733965Sjdp{"cmove", 2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 78833965Sjdp{"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 78933965Sjdp{"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79033965Sjdp{"cmova", 2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79133965Sjdp{"cmovs", 2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79233965Sjdp{"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79333965Sjdp{"cmovp", 2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79433965Sjdp{"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79533965Sjdp{"cmovl", 2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79633965Sjdp{"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79733965Sjdp{"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79833965Sjdp{"cmovg", 2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 79933965Sjdp 80033965Sjdp{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80133965Sjdp{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80233965Sjdp{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80333965Sjdp{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80433965Sjdp{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80533965Sjdp{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80633965Sjdp{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80733965Sjdp{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 80833965Sjdp 80933965Sjdp{"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 81033965Sjdp{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 81133965Sjdp{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 81233965Sjdp{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 81333965Sjdp 81433965Sjdp/* MMX instructions. */ 81533965Sjdp 81633965Sjdp{"emms", 0, 0x0f77, _, NoModrm, { 0, 0, 0 } }, 81733965Sjdp{"movd", 2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } }, 81833965Sjdp{"movd", 2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } }, 81933965Sjdp{"movq", 2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82033965Sjdp{"movq", 2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } }, 82133965Sjdp{"packssdw", 2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82233965Sjdp{"packsswb", 2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82333965Sjdp{"packuswb", 2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82433965Sjdp{"paddb", 2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82533965Sjdp{"paddw", 2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82633965Sjdp{"paddd", 2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82733965Sjdp{"paddsb", 2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82833965Sjdp{"paddsw", 2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 82933965Sjdp{"paddusb", 2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83033965Sjdp{"paddusw", 2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83138889Sjdp{"pand", 2, 0x0fdb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83233965Sjdp{"pandn", 2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83333965Sjdp{"pcmpeqb", 2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83433965Sjdp{"pcmpeqw", 2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83533965Sjdp{"pcmpeqd", 2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83633965Sjdp{"pcmpgtb", 2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83733965Sjdp{"pcmpgtw", 2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83833965Sjdp{"pcmpgtd", 2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 83933965Sjdp{"pmaddwd", 2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84033965Sjdp{"pmulhw", 2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84133965Sjdp{"pmullw", 2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84233965Sjdp{"por", 2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84333965Sjdp{"psllw", 2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84433965Sjdp{"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } }, 84533965Sjdp{"pslld", 2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84633965Sjdp{"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } }, 84733965Sjdp{"psllq", 2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 84833965Sjdp{"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } }, 84933965Sjdp{"psraw", 2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 85033965Sjdp{"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } }, 85133965Sjdp{"psrad", 2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 85233965Sjdp{"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } }, 85333965Sjdp{"psrlw", 2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 85433965Sjdp{"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } }, 85533965Sjdp{"psrld", 2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 85633965Sjdp{"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } }, 85733965Sjdp{"psrlq", 2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 85833965Sjdp{"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } }, 85933965Sjdp{"psubb", 2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86033965Sjdp{"psubw", 2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86133965Sjdp{"psubd", 2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86233965Sjdp{"psubsb", 2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86333965Sjdp{"psubsw", 2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86433965Sjdp{"psubusb", 2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86533965Sjdp{"psubusw", 2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86633965Sjdp{"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86733965Sjdp{"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86833965Sjdp{"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 86933965Sjdp{"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 87033965Sjdp{"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 87133965Sjdp{"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 87233965Sjdp{"pxor", 2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 87333965Sjdp 87433965Sjdp{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ 87533965Sjdp}; 87633965Sjdp#undef _ 87733965Sjdp 87833965Sjdpstatic const template *const i386_optab_end 87933965Sjdp = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); 88033965Sjdp 88133965Sjdp/* 386 register table */ 88233965Sjdp 88333965Sjdpstatic const reg_entry i386_regtab[] = { 88433965Sjdp /* 8 bit regs */ 88533965Sjdp {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, 88633965Sjdp {"bl", Reg8, 3}, 88733965Sjdp {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, 88833965Sjdp /* 16 bit regs */ 88933965Sjdp {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, 89033965Sjdp {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, 89133965Sjdp /* 32 bit regs */ 89233965Sjdp {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, 89333965Sjdp {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, 89433965Sjdp /* segment registers */ 89533965Sjdp {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, 89633965Sjdp {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, 89733965Sjdp /* control registers */ 89833965Sjdp {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, 89933965Sjdp {"cr4", Control, 4}, 90033965Sjdp /* debug registers */ 90133965Sjdp {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, 90233965Sjdp {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, 90333965Sjdp {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2}, 90433965Sjdp {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7}, 90533965Sjdp /* test registers */ 90633965Sjdp {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, 90733965Sjdp {"tr6", Test, 6}, {"tr7", Test, 7}, 90833965Sjdp /* float registers */ 90933965Sjdp {"st(0)", FloatReg|FloatAcc, 0}, 91033965Sjdp {"st", FloatReg|FloatAcc, 0}, 91133965Sjdp {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 91233965Sjdp {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 91333965Sjdp {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}, 91433965Sjdp {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, 91533965Sjdp {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, 91633965Sjdp {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7} 91733965Sjdp}; 91833965Sjdp 91933965Sjdp#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 92033965Sjdp 92133965Sjdpstatic const reg_entry *const i386_regtab_end 92233965Sjdp = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); 92333965Sjdp 92433965Sjdp/* segment stuff */ 92533965Sjdpstatic const seg_entry cs = { "cs", 0x2e }; 92633965Sjdpstatic const seg_entry ds = { "ds", 0x3e }; 92733965Sjdpstatic const seg_entry ss = { "ss", 0x36 }; 92833965Sjdpstatic const seg_entry es = { "es", 0x26 }; 92933965Sjdpstatic const seg_entry fs = { "fs", 0x64 }; 93033965Sjdpstatic const seg_entry gs = { "gs", 0x65 }; 93133965Sjdpstatic const seg_entry null = { "", 0x0 }; 93233965Sjdp 93333965Sjdp/* 93433965Sjdp This table is used to store the default segment register implied by all 93533965Sjdp possible memory addressing modes. 93633965Sjdp It is indexed by the mode & modrm entries of the modrm byte as follows: 93733965Sjdp index = (mode<<3) | modrm; 93833965Sjdp*/ 93933965Sjdpstatic const seg_entry *const one_byte_segment_defaults[] = { 94033965Sjdp /* mode 0 */ 94133965Sjdp &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, 94233965Sjdp /* mode 1 */ 94333965Sjdp &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 94433965Sjdp /* mode 2 */ 94533965Sjdp &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 94633965Sjdp /* mode 3 --- not a memory reference; never referenced */ 94733965Sjdp}; 94833965Sjdp 94933965Sjdpstatic const seg_entry *const two_byte_segment_defaults[] = { 95033965Sjdp /* mode 0 */ 95133965Sjdp &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 95233965Sjdp /* mode 1 */ 95338889Sjdp &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, 95433965Sjdp /* mode 2 */ 95538889Sjdp &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, 95633965Sjdp /* mode 3 --- not a memory reference; never referenced */ 95733965Sjdp}; 95833965Sjdp 95933965Sjdpstatic const prefix_entry i386_prefixtab[] = { 96033965Sjdp#define ADDR_PREFIX_OPCODE 0x67 96133965Sjdp { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing 96233965Sjdp * (How is this useful?) */ 96333965Sjdp#define WORD_PREFIX_OPCODE 0x66 96433965Sjdp { "data16", 0x66 }, /* operand size prefix */ 96533965Sjdp { "lock", 0xf0 }, /* bus lock prefix */ 96633965Sjdp { "wait", 0x9b }, /* wait for coprocessor */ 96733965Sjdp { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ 96833965Sjdp { "es", 0x26 }, { "fs", 0x64 }, 96933965Sjdp { "gs", 0x65 }, { "ss", 0x36 }, 97033965Sjdp/* REPE & REPNE used to detect rep/repne with a non-string instruction */ 97133965Sjdp#define REPNE 0xf2 97233965Sjdp#define REPE 0xf3 97333965Sjdp { "rep", 0xf3 }, /* repeat string instructions */ 97433965Sjdp { "repe", 0xf3 }, { "repz", 0xf3 }, 97533965Sjdp { "repne", 0xf2 }, { "repnz", 0xf2 } 97633965Sjdp}; 97733965Sjdp 97833965Sjdpstatic const prefix_entry *const i386_prefixtab_end 97933965Sjdp = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); 98033965Sjdp 98133965Sjdp/* end of i386-opcode.h */ 982