i386.h revision 38889
1/* i386-opcode.h -- Intel 80386 opcode table 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation. 3 4This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 5 6This program is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2 of the License, or 9(at your option) any later version. 10 11This program is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with this program; if not, write to the Free Software 18Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 19 20/* The NON_BROKEN_OPCODES cases use the operands in the reverse order 21 from that documented in the Intel manuals. The opcode values are 22 such that they actually generate different instructions. These 23 values must not be changed, as they are the values generated by the 24 UnixWare assembler, and possibly other ix86 assemblers. */ 25 26static const template i386_optab[] = { 27 28#define _ None 29/* move instructions */ 30#define MOV_AX_DISP32 0xa0 31{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } }, 32{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } }, 33{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } }, 34{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } }, 35/* The next instruction accepts WordReg so that `movl %gs,%esi' can be 36 used to move a segment register to a 32 bit register without using 37 a size prefix. This will set the upper 16 bits of the 32 bit 38 register to an implementation defined value (on the Pentium Pro, 39 the implementation defined value is zero). */ 40{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, 41/* move to/from control debug registers */ 42{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} }, 43{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} }, 44{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} }, 45 46/* move with sign extend */ 47/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 48 conflict with the "movs" string move instruction. Thus, 49 {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, 50 is not kosher; we must seperate the two instructions. */ 51{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} }, 52{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} }, 53{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, 54 55/* move with zero extend */ 56{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, 57{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, 58 59/* push instructions */ 60{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } }, 61{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } }, 62{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} }, 63{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} }, 64{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } }, 65{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } }, 66/* push all */ 67{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } }, 68 69/* pop instructions */ 70{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } }, 71{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } }, 72#define POP_SEG_SHORT 0x7 73{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } }, 74{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } }, 75/* pop all */ 76{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } }, 77 78/* xchg exchange instructions 79 xchg commutes: we allow both operand orders */ 80{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } }, 81{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } }, 82{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 83{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } }, 84 85/* in/out from ports */ 86{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } }, 87{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } }, 88{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } }, 89{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } }, 90{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } }, 91{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } }, 92{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } }, 93{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } }, 94 95/* load effective address */ 96{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } }, 97 98/* load segment registers from memory */ 99{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} }, 100{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} }, 101{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} }, 102{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} }, 103{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} }, 104 105/* flags register instructions */ 106{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} }, 107{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} }, 108{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} }, 109{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} }, 110{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} }, 111{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} }, 112{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} }, 113{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} }, 114{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} }, 115{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} }, 116{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} }, 117{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} }, 118{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} }, 119{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} }, 120{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} }, 121{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} }, 122 123{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 124{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} }, 125{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} }, 126{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} }, 127 128{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} }, 129{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} }, 130 131{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 132{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} }, 133{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} }, 134{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} }, 135 136{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} }, 137{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} }, 138 139{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 140{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} }, 141{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} }, 142{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} }, 143 144{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 145{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} }, 146{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} }, 147{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} }, 148 149{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} }, 150{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} }, 151{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} }, 152{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} }, 153 154{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 155{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} }, 156{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} }, 157{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} }, 158 159{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 160{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} }, 161{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} }, 162{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} }, 163 164{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 165{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} }, 166{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} }, 167{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} }, 168 169/* iclr with 1 operand is really xor with 2 operands. */ 170{"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } }, 171 172{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} }, 173{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} }, 174{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} }, 175{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} }, 176 177{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} }, 178{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} }, 179 180{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} }, 181{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} }, 182{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} }, 183{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} }, 184{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} }, 185{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} }, 186 187/* conversion insns */ 188/* conversion: intel naming */ 189{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, 190{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, 191{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, 192{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, 193/* att naming */ 194{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, 195{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, 196{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, 197{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, 198 199/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 200 expanding 64-bit multiplies, and *cannot* be selected to accomplish 201 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 202 These multiplies can only be selected with single operand forms. */ 203{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} }, 204{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} }, 205 206 207 208 209/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. 210 These instructions are exceptions: 'imul $2, %eax, %ecx' would put 211 '%eax' in the reg field and '%ecx' in the regmem field if we did not 212 switch them. */ 213{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 214{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} }, 215{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} }, 216/* 217 imul with 2 operands mimicks imul with 3 by puting register both 218 in i.rm.reg & i.rm.regmem fields 219*/ 220{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} }, 221{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} }, 222{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} }, 223{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} }, 224{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} }, 225{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} }, 226 227{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} }, 228{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} }, 229{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 230{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} }, 231 232{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} }, 233{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} }, 234{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 235{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} }, 236 237{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} }, 238{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} }, 239{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 240{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} }, 241 242{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} }, 243{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} }, 244{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 245{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} }, 246 247{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, 248{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, 249{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 250{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, 251{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, 252{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, 253{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 254{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, 255 256{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, 257{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, 258{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} }, 259 260{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} }, 261{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} }, 262{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 263{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} }, 264 265{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, 266{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, 267{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} }, 268 269{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} }, 270{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} }, 271{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} }, 272{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} }, 273 274/* control transfer instructions */ 275#define CALL_PC_RELATIVE 0xe8 276{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} }, 277{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} }, 278{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} }, 279#define CALL_FAR_IMMEDIATE 0x9a 280{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} }, 281{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} }, 282{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} }, 283 284#define JUMP_PC_RELATIVE 0xeb 285{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} }, 286{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} }, 287#define JUMP_FAR_IMMEDIATE 0xea 288{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} }, 289{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} }, 290 291{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} }, 292{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} }, 293{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} }, 294{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} }, 295{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} }, 296{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} }, 297{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} }, 298{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} }, 299{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} }, 300{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} }, 301{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} }, 302{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} }, 303 304/* conditional jumps */ 305{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} }, 306 307{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} }, 308 309{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} }, 310{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} }, 311{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} }, 312 313{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} }, 314{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} }, 315{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} }, 316 317{"je", 1, 0x74, _, Jump, { Disp, 0, 0} }, 318{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} }, 319 320{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} }, 321{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} }, 322 323{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} }, 324{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} }, 325 326{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} }, 327{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} }, 328 329{"js", 1, 0x78, _, Jump, { Disp, 0, 0} }, 330 331{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} }, 332 333{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} }, 334{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} }, 335 336{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} }, 337{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} }, 338 339{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} }, 340{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} }, 341 342{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} }, 343{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} }, 344 345{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} }, 346{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} }, 347 348{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} }, 349{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} }, 350 351#define IS_JUMP_ON_CX_ZERO(o) \ 352 (o == 0xe3) 353 354/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ 355{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} }, 356{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} }, 357 358#define IS_LOOP_ECX_TIMES(o) \ 359 (o == 0xe2 || o == 0xe1 || o == 0xe0) 360 361{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} }, 362 363{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, 364{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, 365 366{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, 367{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, 368 369/* set byte on flag instructions */ 370{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} }, 371 372{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} }, 373 374{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 375{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 376{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, 377 378{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 379{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 380{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, 381 382{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, 383{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, 384 385{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, 386{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, 387 388{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, 389{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, 390 391{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, 392{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, 393 394{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} }, 395 396{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} }, 397 398{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, 399{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, 400 401{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, 402{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, 403 404{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, 405{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, 406 407{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, 408{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, 409 410{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, 411{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, 412 413{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, 414{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, 415 416#define IS_STRING_INSTRUCTION(o) \ 417 ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ 418 (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ 419 (o) == 0xd7) 420 421/* string manipulation */ 422{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, 423{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, 424{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} }, 425{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} }, 426{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, 427{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, 428{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, 429{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, 430{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, 431{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, 432{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, 433{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, 434{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} }, 435 436/* bit manipulation */ 437{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, 438{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, 439{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} }, 440{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} }, 441{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} }, 442{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} }, 443{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} }, 444{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} }, 445{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} }, 446{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} }, 447 448/* interrupts & op. sys insns */ 449/* See gas/config/tc-i386.c for conversion of 'int $3' into the special 450 int 3 insn. */ 451#define INT_OPCODE 0xcd 452#define INT3_OPCODE 0xcc 453{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} }, 454{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} }, 455{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} }, 456{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} }, 457{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} }, 458/* i386sl, i486sl, later 486, and Pentium */ 459{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} }, 460 461{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} }, 462{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} }, 463 464{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} }, 465{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, 466/* nop is actually 'xchgl %eax, %eax' */ 467{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} }, 468 469/* protection control */ 470{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} }, 471{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 472{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} }, 473{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} }, 474{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} }, 475{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} }, 476{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, 477{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} }, 478 479{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} }, 480{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} }, 481{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} }, 482{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} }, 483{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} }, 484 485{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} }, 486{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} }, 487 488/* floating point instructions */ 489 490/* load */ 491{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 492{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */ 493{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */ 494{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 495{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */ 496{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */ 497{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ 498{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ 499{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */ 500{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */ 501 502/* store (no pop) */ 503{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 504{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ 505{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ 506{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 507{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ 508{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ 509 510/* store (with pop) */ 511{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 512{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ 513{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ 514{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ 515{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ 516{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ 517{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ 518{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ 519{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */ 520{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */ 521 522/* exchange %st<n> with %st0 */ 523{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} }, 524{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */ 525 526/* comparison (without pop) */ 527{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, 528{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ 529{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ 530{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ 531{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, 532{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ 533 534/* comparison (with pop) */ 535{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, 536{"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} }, /* fcomp %st, %st(1) */ 537{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ 538{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ 539{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ 540{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, 541{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ 542{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ 543 544/* unordered comparison (with pop) */ 545{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} }, 546{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} }, 547{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ 548 549{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */ 550{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */ 551 552/* load constants into %st0 */ 553{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */ 554{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */ 555{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */ 556{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */ 557{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */ 558{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */ 559{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */ 560 561/* arithmetic */ 562 563/* add */ 564{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} }, 565{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 566{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */ 567{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} }, 568{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 569{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 570{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ 571{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} }, 572{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} }, 573{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} }, 574{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} }, 575 576/* sub */ 577/* Note: intel has decided that certain of these operations are reversed 578 in assembler syntax. */ 579{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} }, 580{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 581#ifdef NON_BROKEN_OPCODES 582{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 583#else 584{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 585#endif 586{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} }, 587{"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} }, 588{"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 589#ifdef NON_BROKEN_OPCODES 590{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 591{"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, 592#else 593{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 594{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, 595#endif 596{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} }, 597{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} }, 598{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} }, 599{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} }, 600 601/* sub reverse */ 602{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} }, 603{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 604#ifdef NON_BROKEN_OPCODES 605{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 606#else 607{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 608#endif 609{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} }, 610{"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} }, 611{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 612#ifdef NON_BROKEN_OPCODES 613{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 614{"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, 615#else 616{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 617{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, 618#endif 619{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} }, 620{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} }, 621{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} }, 622{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} }, 623 624/* mul */ 625{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} }, 626{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 627{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} }, 628{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} }, 629{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 630{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 631{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} }, 632{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} }, 633{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} }, 634{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} }, 635{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} }, 636 637/* div */ 638/* Note: intel has decided that certain of these operations are reversed 639 in assembler syntax. */ 640{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} }, 641{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 642#ifdef NON_BROKEN_OPCODES 643{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 644#else 645{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 646#endif 647{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} }, 648{"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} }, 649{"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 650#ifdef NON_BROKEN_OPCODES 651{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 652{"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, 653#else 654{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 655{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, 656#endif 657{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} }, 658{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} }, 659{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} }, 660{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} }, 661 662/* div reverse */ 663{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} }, 664{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 665#ifdef NON_BROKEN_OPCODES 666{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 667#else 668{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 669#endif 670{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} }, 671{"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} }, 672{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 673#ifdef NON_BROKEN_OPCODES 674{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, 675{"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, 676#else 677{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, 678{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, 679#endif 680{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} }, 681{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} }, 682{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} }, 683{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} }, 684 685{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} }, 686{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} }, 687{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} }, 688{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} }, 689{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} }, 690{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} }, 691{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} }, 692{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} }, 693{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} }, 694{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} }, 695{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} }, 696{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} }, 697{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} }, 698{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} }, 699{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} }, 700{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} }, 701 702{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} }, 703{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} }, 704 705/* processor control */ 706{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} }, 707{"finit", 0, 0xdbe3, _, FWait|NoModrm, { 0, 0, 0} }, 708{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} }, 709{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} }, 710{"fstcw", 1, 0xd9, 7, FWait|Modrm, { Mem, 0, 0} }, 711{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} }, 712{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} }, 713{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} }, 714{"fstsw", 1, 0xdfe0, _, FWait|NoModrm, { Acc, 0, 0} }, 715{"fstsw", 1, 0xdd, 7, FWait|Modrm, { Mem, 0, 0} }, 716{"fstsw", 0, 0xdfe0, _, FWait|NoModrm, { 0, 0, 0} }, 717{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} }, 718{"fclex", 0, 0xdbe2, _, FWait|NoModrm, { 0, 0, 0} }, 719{"fnstenv",1, 0xd9, 6, Modrm, { Mem, 0, 0} }, 720{"fstenv", 1, 0xd9, 6, FWait|Modrm, { Mem, 0, 0} }, 721{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} }, 722{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} }, 723{"fsave", 1, 0xdd, 6, FWait|Modrm, { Mem, 0, 0} }, 724{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} }, 725/* Short forms of fldenv, fstenv use data size prefix. (At least I 726 think so. The PentPro prog ref I have says address size in one 727 place, operand size elsewhere). FIXME: Are these the right names? */ 728{"fnstenvs",1, 0xd9, 6, Modrm|Data16, { Mem, 0, 0} }, 729{"fstenvs", 1, 0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} }, 730{"fldenvs", 1, 0xd9, 4, Modrm|Data16, { Mem, 0, 0} }, 731 732{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} }, 733/* P6:free st(i), pop st */ 734{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} }, 735{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} }, 736#define FWAIT_OPCODE 0x9b 737{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, 738 739/* 740 opcode prefixes; we allow them as seperate insns too 741 (see prefix table below) 742*/ 743{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} }, 744{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} }, 745{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} }, 746{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} }, 747{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} }, 748{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} }, 749{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} }, 750{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} }, 751{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} }, 752{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} }, 753{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} }, 754{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 755{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 756{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, 757{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, 758{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, 759 760/* 486 extensions */ 761 762{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } }, 763{"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 764{"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, 765{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} }, 766{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} }, 767{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} }, 768 769/* 586 and late 486 extensions */ 770{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} }, 771 772/* Pentium extensions */ 773{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} }, 774{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} }, 775{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} }, 776{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} }, 777 778/* Pentium Pro extensions */ 779{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} }, 780 781{"ud2", 0, 0x0f0b, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */ 782 783{"cmovo", 2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 784{"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 785{"cmovb", 2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 786{"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 787{"cmove", 2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 788{"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 789{"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 790{"cmova", 2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 791{"cmovs", 2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 792{"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 793{"cmovp", 2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 794{"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 795{"cmovl", 2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 796{"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 797{"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 798{"cmovg", 2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, 799 800{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 801{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 802{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 803{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 804{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 805{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 806{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 807{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 808 809{"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 810{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 811{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} }, 812{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, 813 814/* MMX instructions. */ 815 816{"emms", 0, 0x0f77, _, NoModrm, { 0, 0, 0 } }, 817{"movd", 2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } }, 818{"movd", 2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } }, 819{"movq", 2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 820{"movq", 2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } }, 821{"packssdw", 2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 822{"packsswb", 2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 823{"packuswb", 2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 824{"paddb", 2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 825{"paddw", 2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 826{"paddd", 2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 827{"paddsb", 2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 828{"paddsw", 2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 829{"paddusb", 2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 830{"paddusw", 2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 831{"pand", 2, 0x0fdb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 832{"pandn", 2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 833{"pcmpeqb", 2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 834{"pcmpeqw", 2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 835{"pcmpeqd", 2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 836{"pcmpgtb", 2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 837{"pcmpgtw", 2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 838{"pcmpgtd", 2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 839{"pmaddwd", 2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 840{"pmulhw", 2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 841{"pmullw", 2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 842{"por", 2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 843{"psllw", 2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 844{"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } }, 845{"pslld", 2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 846{"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } }, 847{"psllq", 2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 848{"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } }, 849{"psraw", 2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 850{"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } }, 851{"psrad", 2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 852{"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } }, 853{"psrlw", 2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 854{"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } }, 855{"psrld", 2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 856{"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } }, 857{"psrlq", 2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 858{"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } }, 859{"psubb", 2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 860{"psubw", 2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 861{"psubd", 2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 862{"psubsb", 2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 863{"psubsw", 2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 864{"psubusb", 2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 865{"psubusw", 2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 866{"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 867{"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 868{"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 869{"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 870{"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 871{"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 872{"pxor", 2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, 873 874{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ 875}; 876#undef _ 877 878static const template *const i386_optab_end 879 = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); 880 881/* 386 register table */ 882 883static const reg_entry i386_regtab[] = { 884 /* 8 bit regs */ 885 {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, 886 {"bl", Reg8, 3}, 887 {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, 888 /* 16 bit regs */ 889 {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, 890 {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, 891 /* 32 bit regs */ 892 {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, 893 {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, 894 /* segment registers */ 895 {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, 896 {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, 897 /* control registers */ 898 {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, 899 {"cr4", Control, 4}, 900 /* debug registers */ 901 {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, 902 {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, 903 {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2}, 904 {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7}, 905 /* test registers */ 906 {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, 907 {"tr6", Test, 6}, {"tr7", Test, 7}, 908 /* float registers */ 909 {"st(0)", FloatReg|FloatAcc, 0}, 910 {"st", FloatReg|FloatAcc, 0}, 911 {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, 912 {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, 913 {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}, 914 {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, 915 {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, 916 {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7} 917}; 918 919#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 920 921static const reg_entry *const i386_regtab_end 922 = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); 923 924/* segment stuff */ 925static const seg_entry cs = { "cs", 0x2e }; 926static const seg_entry ds = { "ds", 0x3e }; 927static const seg_entry ss = { "ss", 0x36 }; 928static const seg_entry es = { "es", 0x26 }; 929static const seg_entry fs = { "fs", 0x64 }; 930static const seg_entry gs = { "gs", 0x65 }; 931static const seg_entry null = { "", 0x0 }; 932 933/* 934 This table is used to store the default segment register implied by all 935 possible memory addressing modes. 936 It is indexed by the mode & modrm entries of the modrm byte as follows: 937 index = (mode<<3) | modrm; 938*/ 939static const seg_entry *const one_byte_segment_defaults[] = { 940 /* mode 0 */ 941 &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, 942 /* mode 1 */ 943 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 944 /* mode 2 */ 945 &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, 946 /* mode 3 --- not a memory reference; never referenced */ 947}; 948 949static const seg_entry *const two_byte_segment_defaults[] = { 950 /* mode 0 */ 951 &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, 952 /* mode 1 */ 953 &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, 954 /* mode 2 */ 955 &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, 956 /* mode 3 --- not a memory reference; never referenced */ 957}; 958 959static const prefix_entry i386_prefixtab[] = { 960#define ADDR_PREFIX_OPCODE 0x67 961 { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing 962 * (How is this useful?) */ 963#define WORD_PREFIX_OPCODE 0x66 964 { "data16", 0x66 }, /* operand size prefix */ 965 { "lock", 0xf0 }, /* bus lock prefix */ 966 { "wait", 0x9b }, /* wait for coprocessor */ 967 { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ 968 { "es", 0x26 }, { "fs", 0x64 }, 969 { "gs", 0x65 }, { "ss", 0x36 }, 970/* REPE & REPNE used to detect rep/repne with a non-string instruction */ 971#define REPNE 0xf2 972#define REPE 0xf3 973 { "rep", 0xf3 }, /* repeat string instructions */ 974 { "repe", 0xf3 }, { "repz", 0xf3 }, 975 { "repne", 0xf2 }, { "repnz", 0xf2 } 976}; 977 978static const prefix_entry *const i386_prefixtab_end 979 = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); 980 981/* end of i386-opcode.h */ 982