1/* $NetBSD: fpu_emu.c,v 1.14 2005/12/11 12:18:42 christos Exp $ */ 2 3/* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Copyright (c) 1992, 1993 40 * The Regents of the University of California. All rights reserved. 41 * 42 * This software was developed by the Computer Systems Engineering group 43 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 44 * contributed to Berkeley. 45 * 46 * All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the University of 49 * California, Lawrence Berkeley Laboratory. 50 * 51 * Redistribution and use in source and binary forms, with or without 52 * modification, are permitted provided that the following conditions 53 * are met: 54 * 1. Redistributions of source code must retain the above copyright 55 * notice, this list of conditions and the following disclaimer. 56 * 2. Redistributions in binary form must reproduce the above copyright 57 * notice, this list of conditions and the following disclaimer in the 58 * documentation and/or other materials provided with the distribution. 59 * 3. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 76 */ 77 78#include <sys/cdefs.h> 79__FBSDID("$FreeBSD$"); 80 81#include "opt_ddb.h" 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/kdb.h> 86#include <sys/kernel.h> 87#include <sys/proc.h> 88#include <sys/sysctl.h> 89#include <sys/signal.h> 90#include <sys/syslog.h> 91#include <sys/signalvar.h> 92 93#include <machine/fpu.h> 94#include <machine/reg.h> 95 96#include <powerpc/fpu/fpu_emu.h> 97#include <powerpc/fpu/fpu_extern.h> 98#include <powerpc/fpu/fpu_instr.h> 99 100static SYSCTL_NODE(_hw, OID_AUTO, fpu_emu, CTLFLAG_RW, 0, "FPU emulator"); 101 102#define FPU_EMU_EVCNT_DECL(name) \ 103static u_int fpu_emu_evcnt_##name; \ 104SYSCTL_INT(_hw_fpu_emu, OID_AUTO, evcnt_##name, CTLFLAG_RD, \ 105 &fpu_emu_evcnt_##name, 0, "") 106 107#define FPU_EMU_EVCNT_INCR(name) fpu_emu_evcnt_##name++ 108 109FPU_EMU_EVCNT_DECL(stfiwx); 110FPU_EMU_EVCNT_DECL(fpstore); 111FPU_EMU_EVCNT_DECL(fpload); 112FPU_EMU_EVCNT_DECL(fcmpu); 113FPU_EMU_EVCNT_DECL(frsp); 114FPU_EMU_EVCNT_DECL(fctiw); 115FPU_EMU_EVCNT_DECL(fcmpo); 116FPU_EMU_EVCNT_DECL(mtfsb1); 117FPU_EMU_EVCNT_DECL(fnegabs); 118FPU_EMU_EVCNT_DECL(mcrfs); 119FPU_EMU_EVCNT_DECL(mtfsb0); 120FPU_EMU_EVCNT_DECL(fmr); 121FPU_EMU_EVCNT_DECL(mtfsfi); 122FPU_EMU_EVCNT_DECL(fnabs); 123FPU_EMU_EVCNT_DECL(fabs); 124FPU_EMU_EVCNT_DECL(mffs); 125FPU_EMU_EVCNT_DECL(mtfsf); 126FPU_EMU_EVCNT_DECL(fctid); 127FPU_EMU_EVCNT_DECL(fcfid); 128FPU_EMU_EVCNT_DECL(fdiv); 129FPU_EMU_EVCNT_DECL(fsub); 130FPU_EMU_EVCNT_DECL(fadd); 131FPU_EMU_EVCNT_DECL(fsqrt); 132FPU_EMU_EVCNT_DECL(fsel); 133FPU_EMU_EVCNT_DECL(fpres); 134FPU_EMU_EVCNT_DECL(fmul); 135FPU_EMU_EVCNT_DECL(frsqrte); 136FPU_EMU_EVCNT_DECL(fmulsub); 137FPU_EMU_EVCNT_DECL(fmuladd); 138FPU_EMU_EVCNT_DECL(fnmsub); 139FPU_EMU_EVCNT_DECL(fnmadd); 140 141/* FPSR exception masks */ 142#define FPSR_EX_MSK (FPSCR_VX|FPSCR_OX|FPSCR_UX|FPSCR_ZX| \ 143 FPSCR_XX|FPSCR_VXSNAN|FPSCR_VXISI|FPSCR_VXIDI| \ 144 FPSCR_VXZDZ|FPSCR_VXIMZ|FPSCR_VXVC|FPSCR_VXSOFT|\ 145 FPSCR_VXSQRT|FPSCR_VXCVI) 146#define FPSR_EX (FPSCR_VE|FPSCR_OE|FPSCR_UE|FPSCR_ZE|FPSCR_XE) 147#define FPSR_EXOP (FPSR_EX_MSK&(~FPSR_EX)) 148 149int fpe_debug = 0; 150 151#ifdef DEBUG 152vm_offset_t opc_disasm(vm_offset_t, int); 153 154/* 155 * Dump a `fpn' structure. 156 */ 157void 158fpu_dumpfpn(struct fpn *fp) 159{ 160 static const char *class[] = { 161 "SNAN", "QNAN", "ZERO", "NUM", "INF" 162 }; 163 164 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 165 fp->fp_sign ? '-' : ' ', 166 fp->fp_mant[0], fp->fp_mant[1], 167 fp->fp_mant[2], fp->fp_mant[3], 168 fp->fp_exp); 169} 170#endif 171 172/* 173 * fpu_execute returns the following error numbers (0 = no error): 174 */ 175#define FPE 1 /* take a floating point exception */ 176#define NOTFPU 2 /* not an FPU instruction */ 177#define FAULT 3 178 179 180/* 181 * Emulate a floating-point instruction. 182 * Return zero for success, else signal number. 183 * (Typically: zero, SIGFPE, SIGILL, SIGSEGV) 184 */ 185int 186fpu_emulate(struct trapframe *frame, struct fpreg *fpf) 187{ 188 static union instr insn; 189 static struct fpemu fe; 190 static int lastill = 0; 191 int sig; 192 193 /* initialize insn.is_datasize to tell it is *not* initialized */ 194 fe.fe_fpstate = fpf; 195 fe.fe_cx = 0; 196 197 /* always set this (to avoid a warning) */ 198 199 if (copyin((void *) (frame->srr0), &insn.i_int, sizeof (insn.i_int))) { 200#ifdef DEBUG 201 printf("fpu_emulate: fault reading opcode\n"); 202#endif 203 return SIGSEGV; 204 } 205 206 DPRINTF(FPE_EX, ("fpu_emulate: emulating insn %x at %p\n", 207 insn.i_int, (void *)frame->srr0)); 208 209 210 if ((insn.i_any.i_opcd == OPC_TWI) || 211 ((insn.i_any.i_opcd == OPC_integer_31) && 212 (insn.i_x.i_xo == OPC31_TW))) { 213 /* Check for the two trap insns. */ 214 DPRINTF(FPE_EX, ("fpu_emulate: SIGTRAP\n")); 215 return (SIGTRAP); 216 } 217 sig = 0; 218 switch (fpu_execute(frame, &fe, &insn)) { 219 case 0: 220 DPRINTF(FPE_EX, ("fpu_emulate: success\n")); 221 frame->srr0 += 4; 222 break; 223 224 case FPE: 225 DPRINTF(FPE_EX, ("fpu_emulate: SIGFPE\n")); 226 sig = SIGFPE; 227 break; 228 229 case FAULT: 230 DPRINTF(FPE_EX, ("fpu_emulate: SIGSEGV\n")); 231 sig = SIGSEGV; 232 break; 233 234 case NOTFPU: 235 default: 236 DPRINTF(FPE_EX, ("fpu_emulate: SIGILL\n")); 237#ifdef DEBUG 238 if (fpe_debug & FPE_EX) { 239 printf("fpu_emulate: illegal insn %x at %p:", 240 insn.i_int, (void *) (frame->srr0)); 241 opc_disasm(frame->srr0, insn.i_int); 242 } 243#endif 244 /* 245 * XXXX retry an illegal insn once due to cache issues. 246 */ 247 if (lastill == frame->srr0) { 248 sig = SIGILL; 249#ifdef DEBUG 250 if (fpe_debug & FPE_EX) 251 kdb_enter(KDB_WHY_UNSET, "illegal instruction"); 252#endif 253 } 254 lastill = frame->srr0; 255 break; 256 } 257 258 return (sig); 259} 260 261/* 262 * Execute an FPU instruction (one that runs entirely in the FPU; not 263 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 264 * modified to reflect the setting the hardware would have left. 265 * 266 * Note that we do not catch all illegal opcodes, so you can, for instance, 267 * multiply two integers this way. 268 */ 269int 270fpu_execute(struct trapframe *tf, struct fpemu *fe, union instr *insn) 271{ 272 struct fpn *fp; 273 union instr instr = *insn; 274 int *a; 275 vm_offset_t addr; 276 int ra, rb, rc, rt, type, mask, fsr, cx, bf, setcr; 277 unsigned int cond; 278 struct fpreg *fs; 279 280 /* Setup work. */ 281 fp = NULL; 282 fs = fe->fe_fpstate; 283 fe->fe_fpscr = ((int *)&fs->fpscr)[1]; 284 285 /* 286 * On PowerPC all floating point values are stored in registers 287 * as doubles, even when used for single precision operations. 288 */ 289 type = FTYPE_DBL; 290 cond = instr.i_any.i_rc; 291 setcr = 0; 292 bf = 0; /* XXX gcc */ 293 294#if defined(DDB) && defined(DEBUG) 295 if (fpe_debug & FPE_EX) { 296 vm_offset_t loc = tf->srr0; 297 298 printf("Trying to emulate: %p ", (void *)loc); 299 opc_disasm(loc, instr.i_int); 300 } 301#endif 302 303 /* 304 * `Decode' and execute instruction. 305 */ 306 307 if ((instr.i_any.i_opcd >= OPC_LFS && instr.i_any.i_opcd <= OPC_STFDU) || 308 instr.i_any.i_opcd == OPC_integer_31) { 309 /* 310 * Handle load/store insns: 311 * 312 * Convert to/from single if needed, calculate addr, 313 * and update index reg if needed. 314 */ 315 double buf; 316 size_t size = sizeof(float); 317 int store, update; 318 319 cond = 0; /* ld/st never set condition codes */ 320 321 322 if (instr.i_any.i_opcd == OPC_integer_31) { 323 if (instr.i_x.i_xo == OPC31_STFIWX) { 324 FPU_EMU_EVCNT_INCR(stfiwx); 325 326 /* Store as integer */ 327 ra = instr.i_x.i_ra; 328 rb = instr.i_x.i_rb; 329 DPRINTF(FPE_INSN, 330 ("reg %d has %jx reg %d has %jx\n", 331 ra, (uintmax_t)tf->fixreg[ra], rb, 332 (uintmax_t)tf->fixreg[rb])); 333 334 addr = tf->fixreg[rb]; 335 if (ra != 0) 336 addr += tf->fixreg[ra]; 337 rt = instr.i_x.i_rt; 338 a = (int *)&fs->fpreg[rt]; 339 DPRINTF(FPE_INSN, 340 ("fpu_execute: Store INT %x at %p\n", 341 a[1], (void *)addr)); 342 if (copyout(&a[1], (void *)addr, sizeof(int))) 343 return (FAULT); 344 return (0); 345 } 346 347 if ((instr.i_x.i_xo & OPC31_FPMASK) != OPC31_FPOP) 348 /* Not an indexed FP load/store op */ 349 return (NOTFPU); 350 351 store = (instr.i_x.i_xo & 0x80); 352 if (instr.i_x.i_xo & 0x40) 353 size = sizeof(double); 354 else 355 type = FTYPE_SNG; 356 update = (instr.i_x.i_xo & 0x20); 357 358 /* calculate EA of load/store */ 359 ra = instr.i_x.i_ra; 360 rb = instr.i_x.i_rb; 361 DPRINTF(FPE_INSN, ("reg %d has %jx reg %d has %jx\n", 362 ra, (uintmax_t)tf->fixreg[ra], rb, 363 (uintmax_t)tf->fixreg[rb])); 364 addr = tf->fixreg[rb]; 365 if (ra != 0) 366 addr += tf->fixreg[ra]; 367 rt = instr.i_x.i_rt; 368 } else { 369 store = instr.i_d.i_opcd & 0x4; 370 if (instr.i_d.i_opcd & 0x2) 371 size = sizeof(double); 372 else 373 type = FTYPE_SNG; 374 update = instr.i_d.i_opcd & 0x1; 375 376 /* calculate EA of load/store */ 377 ra = instr.i_d.i_ra; 378 addr = instr.i_d.i_d; 379 DPRINTF(FPE_INSN, ("reg %d has %jx displ %jx\n", 380 ra, (uintmax_t)tf->fixreg[ra], 381 (uintmax_t)addr)); 382 if (ra != 0) 383 addr += tf->fixreg[ra]; 384 rt = instr.i_d.i_rt; 385 } 386 387 if (update && ra == 0) 388 return (NOTFPU); 389 390 if (store) { 391 /* Store */ 392 FPU_EMU_EVCNT_INCR(fpstore); 393 if (type != FTYPE_DBL) { 394 DPRINTF(FPE_INSN, 395 ("fpu_execute: Store SNG at %p\n", 396 (void *)addr)); 397 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt); 398 fpu_implode(fe, fp, type, (void *)&buf); 399 if (copyout(&buf, (void *)addr, size)) 400 return (FAULT); 401 } else { 402 DPRINTF(FPE_INSN, 403 ("fpu_execute: Store DBL at %p\n", 404 (void *)addr)); 405 if (copyout(&fs->fpreg[rt], (void *)addr, size)) 406 return (FAULT); 407 } 408 } else { 409 /* Load */ 410 FPU_EMU_EVCNT_INCR(fpload); 411 DPRINTF(FPE_INSN, ("fpu_execute: Load from %p\n", 412 (void *)addr)); 413 if (copyin((const void *)addr, &fs->fpreg[rt], size)) 414 return (FAULT); 415 if (type != FTYPE_DBL) { 416 fpu_explode(fe, fp = &fe->fe_f1, type, rt); 417 fpu_implode(fe, fp, FTYPE_DBL, 418 (u_int *)&fs->fpreg[rt]); 419 } 420 } 421 if (update) 422 tf->fixreg[ra] = addr; 423 /* Complete. */ 424 return (0); 425#ifdef notyet 426 } else if (instr.i_any.i_opcd == OPC_load_st_62) { 427 /* These are 64-bit extensions */ 428 return (NOTFPU); 429#endif 430 } else if (instr.i_any.i_opcd == OPC_sp_fp_59 || 431 instr.i_any.i_opcd == OPC_dp_fp_63) { 432 433 434 if (instr.i_any.i_opcd == OPC_dp_fp_63 && 435 !(instr.i_a.i_xo & OPC63M_MASK)) { 436 /* Format X */ 437 rt = instr.i_x.i_rt; 438 ra = instr.i_x.i_ra; 439 rb = instr.i_x.i_rb; 440 441 442 /* One of the special opcodes.... */ 443 switch (instr.i_x.i_xo) { 444 case OPC63_FCMPU: 445 FPU_EMU_EVCNT_INCR(fcmpu); 446 DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n")); 447 rt >>= 2; 448 fpu_explode(fe, &fe->fe_f1, type, ra); 449 fpu_explode(fe, &fe->fe_f2, type, rb); 450 fpu_compare(fe, 0); 451 /* Make sure we do the condition regs. */ 452 cond = 0; 453 /* N.B.: i_rs is already left shifted by two. */ 454 bf = instr.i_x.i_rs & 0xfc; 455 setcr = 1; 456 break; 457 458 case OPC63_FRSP: 459 /* 460 * Convert to single: 461 * 462 * PowerPC uses this to round a double 463 * precision value to single precision, 464 * but values in registers are always 465 * stored in double precision format. 466 */ 467 FPU_EMU_EVCNT_INCR(frsp); 468 DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n")); 469 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb); 470 fpu_implode(fe, fp, FTYPE_SNG, 471 (u_int *)&fs->fpreg[rt]); 472 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 473 type = FTYPE_DBL; 474 break; 475 case OPC63_FCTIW: 476 case OPC63_FCTIWZ: 477 FPU_EMU_EVCNT_INCR(fctiw); 478 DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n")); 479 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 480 type = FTYPE_INT; 481 break; 482 case OPC63_FCMPO: 483 FPU_EMU_EVCNT_INCR(fcmpo); 484 DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n")); 485 rt >>= 2; 486 fpu_explode(fe, &fe->fe_f1, type, ra); 487 fpu_explode(fe, &fe->fe_f2, type, rb); 488 fpu_compare(fe, 1); 489 /* Make sure we do the condition regs. */ 490 cond = 0; 491 /* N.B.: i_rs is already left shifted by two. */ 492 bf = instr.i_x.i_rs & 0xfc; 493 setcr = 1; 494 break; 495 case OPC63_MTFSB1: 496 FPU_EMU_EVCNT_INCR(mtfsb1); 497 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB1\n")); 498 fe->fe_fpscr |= 499 (~(FPSCR_VX|FPSR_EX) & (1<<(31-rt))); 500 break; 501 case OPC63_FNEG: 502 FPU_EMU_EVCNT_INCR(fnegabs); 503 DPRINTF(FPE_INSN, ("fpu_execute: FNEGABS\n")); 504 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 505 sizeof(double)); 506 a = (int *)&fs->fpreg[rt]; 507 *a ^= (1U << 31); 508 break; 509 case OPC63_MCRFS: 510 FPU_EMU_EVCNT_INCR(mcrfs); 511 DPRINTF(FPE_INSN, ("fpu_execute: MCRFS\n")); 512 cond = 0; 513 rt &= 0x1c; 514 ra &= 0x1c; 515 /* Extract the bits we want */ 516 mask = (fe->fe_fpscr >> (28 - ra)) & 0xf; 517 /* Clear the bits we copied. */ 518 fe->fe_cx = 519 (FPSR_EX_MSK | (0xf << (28 - ra))); 520 fe->fe_fpscr &= fe->fe_cx; 521 /* Now shove them in the right part of cr */ 522 tf->cr &= ~(0xf << (28 - rt)); 523 tf->cr |= (mask << (28 - rt)); 524 break; 525 case OPC63_MTFSB0: 526 FPU_EMU_EVCNT_INCR(mtfsb0); 527 DPRINTF(FPE_INSN, ("fpu_execute: MTFSB0\n")); 528 fe->fe_fpscr &= 529 ((FPSCR_VX|FPSR_EX) & ~(1<<(31-rt))); 530 break; 531 case OPC63_FMR: 532 FPU_EMU_EVCNT_INCR(fmr); 533 DPRINTF(FPE_INSN, ("fpu_execute: FMR\n")); 534 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 535 sizeof(double)); 536 break; 537 case OPC63_MTFSFI: 538 FPU_EMU_EVCNT_INCR(mtfsfi); 539 DPRINTF(FPE_INSN, ("fpu_execute: MTFSFI\n")); 540 rb >>= 1; 541 rt &= 0x1c; /* Already left-shifted 4 */ 542 fe->fe_cx = rb << (28 - rt); 543 mask = 0xf<<(28 - rt); 544 fe->fe_fpscr = (fe->fe_fpscr & ~mask) | 545 fe->fe_cx; 546/* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 547 break; 548 case OPC63_FNABS: 549 FPU_EMU_EVCNT_INCR(fnabs); 550 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 551 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 552 sizeof(double)); 553 a = (int *)&fs->fpreg[rt]; 554 *a |= (1U << 31); 555 break; 556 case OPC63_FABS: 557 FPU_EMU_EVCNT_INCR(fabs); 558 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 559 memcpy(&fs->fpreg[rt], &fs->fpreg[rb], 560 sizeof(double)); 561 a = (int *)&fs->fpreg[rt]; 562 *a &= ~(1U << 31); 563 break; 564 case OPC63_MFFS: 565 FPU_EMU_EVCNT_INCR(mffs); 566 DPRINTF(FPE_INSN, ("fpu_execute: MFFS\n")); 567 memcpy(&fs->fpreg[rt], &fs->fpscr, 568 sizeof(fs->fpscr)); 569 break; 570 case OPC63_MTFSF: 571 FPU_EMU_EVCNT_INCR(mtfsf); 572 DPRINTF(FPE_INSN, ("fpu_execute: MTFSF\n")); 573 if ((rt = instr.i_xfl.i_flm) == -1) 574 mask = -1; 575 else { 576 mask = 0; 577 /* Convert 1 bit -> 4 bits */ 578 for (ra = 0; ra < 8; ra ++) 579 if (rt & (1<<ra)) 580 mask |= (0xf<<(4*ra)); 581 } 582 a = (int *)&fs->fpreg[rt]; 583 fe->fe_cx = mask & a[1]; 584 fe->fe_fpscr = (fe->fe_fpscr&~mask) | 585 (fe->fe_cx); 586/* XXX weird stuff about OX, FX, FEX, and VX should be handled */ 587 break; 588 case OPC63_FCTID: 589 case OPC63_FCTIDZ: 590 FPU_EMU_EVCNT_INCR(fctid); 591 DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n")); 592 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 593 type = FTYPE_LNG; 594 break; 595 case OPC63_FCFID: 596 FPU_EMU_EVCNT_INCR(fcfid); 597 DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n")); 598 type = FTYPE_LNG; 599 fpu_explode(fe, fp = &fe->fe_f1, type, rb); 600 type = FTYPE_DBL; 601 break; 602 default: 603 return (NOTFPU); 604 break; 605 } 606 } else { 607 /* Format A */ 608 rt = instr.i_a.i_frt; 609 ra = instr.i_a.i_fra; 610 rb = instr.i_a.i_frb; 611 rc = instr.i_a.i_frc; 612 613 /* 614 * All arithmetic operations work on registers, which 615 * are stored as doubles. 616 */ 617 type = FTYPE_DBL; 618 switch ((unsigned int)instr.i_a.i_xo) { 619 case OPC59_FDIVS: 620 FPU_EMU_EVCNT_INCR(fdiv); 621 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 622 fpu_explode(fe, &fe->fe_f1, type, ra); 623 fpu_explode(fe, &fe->fe_f2, type, rb); 624 fp = fpu_div(fe); 625 break; 626 case OPC59_FSUBS: 627 FPU_EMU_EVCNT_INCR(fsub); 628 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 629 fpu_explode(fe, &fe->fe_f1, type, ra); 630 fpu_explode(fe, &fe->fe_f2, type, rb); 631 fp = fpu_sub(fe); 632 break; 633 case OPC59_FADDS: 634 FPU_EMU_EVCNT_INCR(fadd); 635 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 636 fpu_explode(fe, &fe->fe_f1, type, ra); 637 fpu_explode(fe, &fe->fe_f2, type, rb); 638 fp = fpu_add(fe); 639 break; 640 case OPC59_FSQRTS: 641 FPU_EMU_EVCNT_INCR(fsqrt); 642 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 643 fpu_explode(fe, &fe->fe_f1, type, rb); 644 fp = fpu_sqrt(fe); 645 break; 646 case OPC63M_FSEL: 647 FPU_EMU_EVCNT_INCR(fsel); 648 DPRINTF(FPE_INSN, ("fpu_execute: FSEL\n")); 649 a = (int *)&fe->fe_fpstate->fpreg[ra]; 650 if ((*a & 0x80000000) && (*a & 0x7fffffff)) 651 /* fra < 0 */ 652 rc = rb; 653 DPRINTF(FPE_INSN, ("f%d => f%d\n", rc, rt)); 654 memcpy(&fs->fpreg[rt], &fs->fpreg[rc], 655 sizeof(double)); 656 break; 657 case OPC59_FRES: 658 FPU_EMU_EVCNT_INCR(fpres); 659 DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n")); 660 fpu_explode(fe, &fe->fe_f1, type, rb); 661 fp = fpu_sqrt(fe); 662 /* now we've gotta overwrite the dest reg */ 663 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 664 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 665 fpu_div(fe); 666 break; 667 case OPC59_FMULS: 668 FPU_EMU_EVCNT_INCR(fmul); 669 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 670 fpu_explode(fe, &fe->fe_f1, type, ra); 671 fpu_explode(fe, &fe->fe_f2, type, rc); 672 fp = fpu_mul(fe); 673 break; 674 case OPC63M_FRSQRTE: 675 /* Reciprocal sqrt() estimate */ 676 FPU_EMU_EVCNT_INCR(frsqrte); 677 DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n")); 678 fpu_explode(fe, &fe->fe_f1, type, rb); 679 fp = fpu_sqrt(fe); 680 fe->fe_f2 = *fp; 681 /* now we've gotta overwrite the dest reg */ 682 *((int *)&fe->fe_fpstate->fpreg[rt]) = 1; 683 fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt); 684 fpu_div(fe); 685 break; 686 case OPC59_FMSUBS: 687 FPU_EMU_EVCNT_INCR(fmulsub); 688 DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n")); 689 fpu_explode(fe, &fe->fe_f1, type, ra); 690 fpu_explode(fe, &fe->fe_f2, type, rc); 691 fp = fpu_mul(fe); 692 fe->fe_f1 = *fp; 693 fpu_explode(fe, &fe->fe_f2, type, rb); 694 fp = fpu_sub(fe); 695 break; 696 case OPC59_FMADDS: 697 FPU_EMU_EVCNT_INCR(fmuladd); 698 DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n")); 699 fpu_explode(fe, &fe->fe_f1, type, ra); 700 fpu_explode(fe, &fe->fe_f2, type, rc); 701 fp = fpu_mul(fe); 702 fe->fe_f1 = *fp; 703 fpu_explode(fe, &fe->fe_f2, type, rb); 704 fp = fpu_add(fe); 705 break; 706 case OPC59_FNMSUBS: 707 FPU_EMU_EVCNT_INCR(fnmsub); 708 DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n")); 709 fpu_explode(fe, &fe->fe_f1, type, ra); 710 fpu_explode(fe, &fe->fe_f2, type, rc); 711 fp = fpu_mul(fe); 712 fe->fe_f1 = *fp; 713 fpu_explode(fe, &fe->fe_f2, type, rb); 714 fp = fpu_sub(fe); 715 /* Negate */ 716 fp->fp_sign ^= 1; 717 break; 718 case OPC59_FNMADDS: 719 FPU_EMU_EVCNT_INCR(fnmadd); 720 DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n")); 721 fpu_explode(fe, &fe->fe_f1, type, ra); 722 fpu_explode(fe, &fe->fe_f2, type, rc); 723 fp = fpu_mul(fe); 724 fe->fe_f1 = *fp; 725 fpu_explode(fe, &fe->fe_f2, type, rb); 726 fp = fpu_add(fe); 727 /* Negate */ 728 fp->fp_sign ^= 1; 729 break; 730 default: 731 return (NOTFPU); 732 break; 733 } 734 735 /* If the instruction was single precision, round */ 736 if (!(instr.i_any.i_opcd & 0x4)) { 737 fpu_implode(fe, fp, FTYPE_SNG, 738 (u_int *)&fs->fpreg[rt]); 739 fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt); 740 } 741 } 742 } else { 743 return (NOTFPU); 744 } 745 746 /* 747 * ALU operation is complete. Collapse the result and then check 748 * for exceptions. If we got any, and they are enabled, do not 749 * alter the destination register, just stop with an exception. 750 * Otherwise set new current exceptions and accrue. 751 */ 752 if (fp) 753 fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]); 754 cx = fe->fe_cx; 755 fsr = fe->fe_fpscr; 756 if (cx != 0) { 757 fsr &= ~FPSCR_FX; 758 if ((cx^fsr)&FPSR_EX_MSK) 759 fsr |= FPSCR_FX; 760 mask = fsr & FPSR_EX; 761 mask <<= (25-3); 762 if (cx & mask) 763 fsr |= FPSCR_FEX; 764 if (cx & FPSCR_FPRF) { 765 /* Need to replace CC */ 766 fsr &= ~FPSCR_FPRF; 767 } 768 if (cx & (FPSR_EXOP)) 769 fsr |= FPSCR_VX; 770 fsr |= cx; 771 DPRINTF(FPE_INSN, ("fpu_execute: cx %x, fsr %x\n", cx, fsr)); 772 } 773 774 if (cond) { 775 cond = fsr & 0xf0000000; 776 /* Isolate condition codes */ 777 cond >>= 28; 778 /* Move fpu condition codes to cr[1] */ 779 tf->cr &= (0x0f000000); 780 tf->cr |= (cond<<24); 781 DPRINTF(FPE_INSN, ("fpu_execute: cr[1] <= %x\n", cond)); 782 } 783 784 if (setcr) { 785 cond = fsr & FPSCR_FPCC; 786 /* Isolate condition codes */ 787 cond <<= 16; 788 /* Move fpu condition codes to cr[1] */ 789 tf->cr &= ~(0xf0000000>>bf); 790 tf->cr |= (cond>>bf); 791 DPRINTF(FPE_INSN, ("fpu_execute: cr[%d] (cr=%jx) <= %x\n", 792 bf/4, (uintmax_t)tf->cr, cond)); 793 } 794 795 ((int *)&fs->fpscr)[1] = fsr; 796 if (fsr & FPSCR_FEX) 797 return(FPE); 798 return (0); /* success */ 799} 800