rp_pci.c revision 130841
1/*- 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * PCI-specific part separated from: 6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted prodived that the follwoing conditions 10 * are met. 11 * 1. Redistributions of source code must retain the above copyright 12 * notive, this list of conditions and the following disclainer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials prodided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Comtrol Corporation. 19 * 4. The name of Comtrol Corporation may not be used to endorse or 20 * promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD: head/sys/dev/rp/rp_pci.c 130841 2004-06-21 13:02:25Z gallatin $"); 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/fcntl.h> 42#include <sys/malloc.h> 43#include <sys/tty.h> 44#include <sys/conf.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <machine/resource.h> 48#include <machine/bus.h> 49#include <sys/bus.h> 50#include <sys/rman.h> 51 52#define ROCKET_C 53#include <dev/rp/rpreg.h> 54#include <dev/rp/rpvar.h> 55 56#include <dev/pci/pcireg.h> 57#include <dev/pci/pcivar.h> 58 59/* PCI IDs */ 60#define RP_VENDOR_ID 0x11FE 61#define RP_DEVICE_ID_32I 0x0001 62#define RP_DEVICE_ID_8I 0x0002 63#define RP_DEVICE_ID_16I 0x0003 64#define RP_DEVICE_ID_4Q 0x0004 65#define RP_DEVICE_ID_8O 0x0005 66#define RP_DEVICE_ID_8J 0x0006 67#define RP_DEVICE_ID_4J 0x0007 68#define RP_DEVICE_ID_6M 0x000C 69#define RP_DEVICE_ID_4M 0x000D 70 71/************************************************************************** 72 MUDBAC remapped for PCI 73**************************************************************************/ 74 75#define _CFG_INT_PCI 0x40 76#define _PCI_INT_FUNC 0x3A 77 78#define PCI_STROB 0x2000 79#define INTR_EN_PCI 0x0010 80 81/*************************************************************************** 82Function: sPCIControllerEOI 83Purpose: Strobe the MUDBAC's End Of Interrupt bit. 84Call: sPCIControllerEOI(CtlP) 85 CONTROLLER_T *CtlP; Ptr to controller structure 86*/ 87#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB) 88 89/*************************************************************************** 90Function: sPCIGetControllerIntStatus 91Purpose: Get the controller interrupt status 92Call: sPCIGetControllerIntStatus(CtlP) 93 CONTROLLER_T *CtlP; Ptr to controller structure 94Return: Byte_t: The controller interrupt status in the lower 4 95 bits. Bits 0 through 3 represent AIOP's 0 96 through 3 respectively. If a bit is set that 97 AIOP is interrupting. Bits 4 through 7 will 98 always be cleared. 99*/ 100#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f) 101 102static devclass_t rp_devclass; 103 104static int rp_pciprobe(device_t dev); 105static int rp_pciattach(device_t dev); 106#if notdef 107static int rp_pcidetach(device_t dev); 108static int rp_pcishutdown(device_t dev); 109#endif /* notdef */ 110static void rp_pcireleaseresource(CONTROLLER_t *ctlp); 111static int sPCIInitController( CONTROLLER_t *CtlP, 112 int AiopNum, 113 int IRQNum, 114 Byte_t Frequency, 115 int PeriodicOnly, 116 int VendorDevice); 117static rp_aiop2rid_t rp_pci_aiop2rid; 118static rp_aiop2off_t rp_pci_aiop2off; 119static rp_ctlmask_t rp_pci_ctlmask; 120 121/* 122 * The following functions are the pci-specific part 123 * of rp driver. 124 */ 125 126static int 127rp_pciprobe(device_t dev) 128{ 129 char *s; 130 131 s = NULL; 132 if ((pci_get_devid(dev) & 0xffff) == RP_VENDOR_ID) 133 s = "RocketPort PCI"; 134 135 if (s != NULL) { 136 device_set_desc(dev, s); 137 return (0); 138 } 139 140 return (ENXIO); 141} 142 143static int 144rp_pciattach(device_t dev) 145{ 146 int num_ports, num_aiops; 147 int aiop; 148 CONTROLLER_t *ctlp; 149 int unit; 150 int retval; 151 u_int32_t stcmd; 152 153 ctlp = device_get_softc(dev); 154 bzero(ctlp, sizeof(*ctlp)); 155 ctlp->dev = dev; 156 unit = device_get_unit(dev); 157 ctlp->aiop2rid = rp_pci_aiop2rid; 158 ctlp->aiop2off = rp_pci_aiop2off; 159 ctlp->ctlmask = rp_pci_ctlmask; 160 161 /* Wake up the device. */ 162 stcmd = pci_read_config(dev, PCIR_COMMAND, 4); 163 if ((stcmd & PCIM_CMD_PORTEN) == 0) { 164 stcmd |= (PCIM_CMD_PORTEN); 165 pci_write_config(dev, PCIR_COMMAND, 4, stcmd); 166 } 167 168 /* The IO ports of AIOPs for a PCI controller are continuous. */ 169 ctlp->io_num = 1; 170 ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO); 171 ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO); 172 if (ctlp->io_rid == NULL || ctlp->io == NULL) { 173 device_printf(dev, "rp_pciattach: Out of memory.\n"); 174 retval = ENOMEM; 175 goto nogo; 176 } 177 178 ctlp->bus_ctlp = NULL; 179 180 ctlp->io_rid[0] = 0x10; 181 ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 182 &ctlp->io_rid[0], RF_ACTIVE); 183 if(ctlp->io[0] == NULL) { 184 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n"); 185 retval = ENXIO; 186 goto nogo; 187 } 188 189 num_aiops = sPCIInitController(ctlp, 190 MAX_AIOPS_PER_BOARD, 0, 191 FREQ_DIS, 0, (pci_get_devid(dev) >> 16) & 0xffff); 192 193 num_ports = 0; 194 for(aiop=0; aiop < num_aiops; aiop++) { 195 sResetAiopByNum(ctlp, aiop); 196 num_ports += sGetAiopNumChan(ctlp, aiop); 197 } 198 199 retval = rp_attachcommon(ctlp, num_aiops, num_ports); 200 if (retval != 0) 201 goto nogo; 202 203 return (0); 204 205nogo: 206 rp_pcireleaseresource(ctlp); 207 208 return (retval); 209} 210 211static int 212rp_pcidetach(device_t dev) 213{ 214 CONTROLLER_t *ctlp; 215 216 if (device_get_state(dev) == DS_BUSY) 217 return (EBUSY); 218 219 ctlp = device_get_softc(dev); 220 221 rp_pcireleaseresource(ctlp); 222 223 return (0); 224} 225 226static int 227rp_pcishutdown(device_t dev) 228{ 229 CONTROLLER_t *ctlp; 230 231 if (device_get_state(dev) == DS_BUSY) 232 return (EBUSY); 233 234 ctlp = device_get_softc(dev); 235 236 rp_pcireleaseresource(ctlp); 237 238 return (0); 239} 240 241static void 242rp_pcireleaseresource(CONTROLLER_t *ctlp) 243{ 244 rp_untimeout(); 245 if (ctlp->io != NULL) { 246 if (ctlp->io[0] != NULL) 247 bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]); 248 free(ctlp->io, M_DEVBUF); 249 ctlp->io = NULL; 250 } 251 if (ctlp->io_rid != NULL) { 252 free(ctlp->io_rid, M_DEVBUF); 253 ctlp->io = NULL; 254 } 255 rp_releaseresource(ctlp); 256} 257 258static int 259sPCIInitController( CONTROLLER_t *CtlP, 260 int AiopNum, 261 int IRQNum, 262 Byte_t Frequency, 263 int PeriodicOnly, 264 int VendorDevice) 265{ 266 int i; 267 268 CtlP->CtlID = CTLID_0001; /* controller release 1 */ 269 270 sPCIControllerEOI(CtlP); 271 272 /* Init AIOPs */ 273 CtlP->NumAiop = 0; 274 for(i=0; i < AiopNum; i++) 275 { 276 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/ 277 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */ 278 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/ 279 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */ 280 { 281 break; /* done looking for AIOPs */ 282 } 283 284 switch( VendorDevice ) { 285 case RP_DEVICE_ID_4Q: 286 case RP_DEVICE_ID_4J: 287 case RP_DEVICE_ID_4M: 288 CtlP->AiopNumChan[i] = 4; 289 break; 290 case RP_DEVICE_ID_6M: 291 CtlP->AiopNumChan[i] = 6; 292 break; 293 case RP_DEVICE_ID_8O: 294 case RP_DEVICE_ID_8J: 295 case RP_DEVICE_ID_8I: 296 case RP_DEVICE_ID_16I: 297 case RP_DEVICE_ID_32I: 298 CtlP->AiopNumChan[i] = 8; 299 break; 300 default: 301#if notdef 302 CtlP->AiopNumChan[i] = 8; 303#else 304 CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i); 305#endif /* notdef */ 306 break; 307 } 308 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/ 309 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE); /* clock prescaler */ 310 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/ 311 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC); 312 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/ 313 CtlP->NumAiop++; /* bump count of AIOPs */ 314 } 315 316 if(CtlP->NumAiop == 0) 317 return(-1); 318 else 319 return(CtlP->NumAiop); 320} 321 322/* 323 * ARGSUSED 324 * Maps (aiop, offset) to rid. 325 */ 326static int 327rp_pci_aiop2rid(int aiop, int offset) 328{ 329 /* Always return zero for a PCI controller. */ 330 return 0; 331} 332 333/* 334 * ARGSUSED 335 * Maps (aiop, offset) to the offset of resource. 336 */ 337static int 338rp_pci_aiop2off(int aiop, int offset) 339{ 340 /* Each AIOP reserves 0x40 bytes. */ 341 return aiop * 0x40 + offset; 342} 343 344/* Read the int status for a PCI controller. */ 345static unsigned char 346rp_pci_ctlmask(CONTROLLER_t *ctlp) 347{ 348 return sPCIGetControllerIntStatus(ctlp); 349} 350 351static device_method_t rp_pcimethods[] = { 352 /* Device interface */ 353 DEVMETHOD(device_probe, rp_pciprobe), 354 DEVMETHOD(device_attach, rp_pciattach), 355 DEVMETHOD(device_detach, rp_pcidetach), 356 DEVMETHOD(device_shutdown, rp_pcishutdown), 357 358 { 0, 0 } 359}; 360 361static driver_t rp_pcidriver = { 362 "rp", 363 rp_pcimethods, 364 sizeof(CONTROLLER_t), 365}; 366 367/* 368 * rp can be attached to a pci bus. 369 */ 370DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0); 371