1/*-
2 * Copyright (c) Comtrol Corporation <support@comtrol.com>
3 * All rights reserved.
4 *
5 * PCI-specific part separated from:
6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted prodived that the follwoing conditions
10 * are met.
11 * 1. Redistributions of source code must retain the above copyright
12 *    notive, this list of conditions and the following disclainer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials prodided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 *    must display the following acknowledgement:
18 *       This product includes software developed by Comtrol Corporation.
19 * 4. The name of Comtrol Corporation may not be used to endorse or
20 *    promote products derived from this software without specific
21 *    prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED.  IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#include <sys/cdefs.h>
37__FBSDID("$FreeBSD$");
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/fcntl.h>
42#include <sys/malloc.h>
43#include <sys/tty.h>
44#include <sys/conf.h>
45#include <sys/kernel.h>
46#include <sys/module.h>
47#include <machine/resource.h>
48#include <machine/bus.h>
49#include <sys/bus.h>
50#include <sys/rman.h>
51
52#define ROCKET_C
53#include <dev/rp/rpreg.h>
54#include <dev/rp/rpvar.h>
55
56#include <dev/pci/pcireg.h>
57#include <dev/pci/pcivar.h>
58
59/* PCI IDs  */
60#define RP_VENDOR_ID		0x11FE
61#define RP_DEVICE_ID_32I	0x0001
62#define RP_DEVICE_ID_8I		0x0002
63#define RP_DEVICE_ID_16I	0x0003
64#define RP_DEVICE_ID_4Q		0x0004
65#define RP_DEVICE_ID_8O		0x0005
66#define RP_DEVICE_ID_8J		0x0006
67#define RP_DEVICE_ID_4J		0x0007
68#define RP_DEVICE_ID_6M		0x000C
69#define RP_DEVICE_ID_4M		0x000D
70#define RP_DEVICE_ID_UPCI_32	0x0801
71#define RP_DEVICE_ID_UPCI_16	0x0803
72#define RP_DEVICE_ID_UPCI_8O	0x0805
73
74/**************************************************************************
75  MUDBAC remapped for PCI
76**************************************************************************/
77
78#define _CFG_INT_PCI	0x40
79#define _PCI_INT_FUNC	0x3A
80
81#define PCI_STROB	0x2000
82#define INTR_EN_PCI	0x0010
83
84/***************************************************************************
85Function: sPCIControllerEOI
86Purpose:  Strobe the MUDBAC's End Of Interrupt bit.
87Call:	  sPCIControllerEOI(CtlP)
88	  CONTROLLER_T *CtlP; Ptr to controller structure
89*/
90#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB)
91
92/***************************************************************************
93Function: sPCIGetControllerIntStatus
94Purpose:  Get the controller interrupt status
95Call:	  sPCIGetControllerIntStatus(CtlP)
96	  CONTROLLER_T *CtlP; Ptr to controller structure
97Return:   Byte_t: The controller interrupt status in the lower 4
98			 bits.	Bits 0 through 3 represent AIOP's 0
99			 through 3 respectively.  If a bit is set that
100			 AIOP is interrupting.	Bits 4 through 7 will
101			 always be cleared.
102*/
103#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f)
104
105static devclass_t rp_devclass;
106
107static int rp_pciprobe(device_t dev);
108static int rp_pciattach(device_t dev);
109#ifdef notdef
110static int rp_pcidetach(device_t dev);
111static int rp_pcishutdown(device_t dev);
112#endif /* notdef */
113static void rp_pcireleaseresource(CONTROLLER_t *ctlp);
114static int sPCIInitController( CONTROLLER_t *CtlP,
115			       int AiopNum,
116			       int IRQNum,
117			       Byte_t Frequency,
118			       int PeriodicOnly,
119			       int VendorDevice);
120static rp_aiop2rid_t rp_pci_aiop2rid;
121static rp_aiop2off_t rp_pci_aiop2off;
122static rp_ctlmask_t rp_pci_ctlmask;
123
124/*
125 * The following functions are the pci-specific part
126 * of rp driver.
127 */
128
129static int
130rp_pciprobe(device_t dev)
131{
132	char *s;
133
134	s = NULL;
135	if (pci_get_vendor(dev) == RP_VENDOR_ID)
136		s = "RocketPort PCI";
137
138	if (s != NULL) {
139		device_set_desc(dev, s);
140		return (BUS_PROBE_DEFAULT);
141	}
142
143	return (ENXIO);
144}
145
146static int
147rp_pciattach(device_t dev)
148{
149	int	num_ports, num_aiops;
150	int	aiop;
151	CONTROLLER_t	*ctlp;
152	int	unit;
153	int	retval;
154
155	ctlp = device_get_softc(dev);
156	bzero(ctlp, sizeof(*ctlp));
157	ctlp->dev = dev;
158	unit = device_get_unit(dev);
159	ctlp->aiop2rid = rp_pci_aiop2rid;
160	ctlp->aiop2off = rp_pci_aiop2off;
161	ctlp->ctlmask = rp_pci_ctlmask;
162
163	/* The IO ports of AIOPs for a PCI controller are continuous. */
164	ctlp->io_num = 1;
165	ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
166	ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO);
167	if (ctlp->io_rid == NULL || ctlp->io == NULL) {
168		device_printf(dev, "rp_pciattach: Out of memory.\n");
169		retval = ENOMEM;
170		goto nogo;
171	}
172
173	ctlp->bus_ctlp = NULL;
174
175	switch (pci_get_device(dev)) {
176	case RP_DEVICE_ID_UPCI_16:
177	case RP_DEVICE_ID_UPCI_32:
178	case RP_DEVICE_ID_UPCI_8O:
179		ctlp->io_rid[0] = PCIR_BAR(2);
180		break;
181	default:
182		ctlp->io_rid[0] = PCIR_BAR(0);
183		break;
184	}
185	ctlp->io[0] = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
186		&ctlp->io_rid[0], RF_ACTIVE);
187	if(ctlp->io[0] == NULL) {
188		device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n");
189		retval = ENXIO;
190		goto nogo;
191	}
192
193	num_aiops = sPCIInitController(ctlp,
194				       MAX_AIOPS_PER_BOARD, 0,
195				       FREQ_DIS, 0, pci_get_device(dev));
196
197	num_ports = 0;
198	for(aiop=0; aiop < num_aiops; aiop++) {
199		sResetAiopByNum(ctlp, aiop);
200		num_ports += sGetAiopNumChan(ctlp, aiop);
201	}
202
203	retval = rp_attachcommon(ctlp, num_aiops, num_ports);
204	if (retval != 0)
205		goto nogo;
206
207	return (0);
208
209nogo:
210	rp_pcireleaseresource(ctlp);
211
212	return (retval);
213}
214
215static int
216rp_pcidetach(device_t dev)
217{
218	CONTROLLER_t	*ctlp;
219
220	ctlp = device_get_softc(dev);
221	rp_pcireleaseresource(ctlp);
222
223	return (0);
224}
225
226static int
227rp_pcishutdown(device_t dev)
228{
229	CONTROLLER_t	*ctlp;
230
231	ctlp = device_get_softc(dev);
232	rp_pcireleaseresource(ctlp);
233
234	return (0);
235}
236
237static void
238rp_pcireleaseresource(CONTROLLER_t *ctlp)
239{
240	rp_untimeout();
241	if (ctlp->io != NULL) {
242		if (ctlp->io[0] != NULL)
243			bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]);
244		free(ctlp->io, M_DEVBUF);
245		ctlp->io = NULL;
246	}
247	if (ctlp->io_rid != NULL) {
248		free(ctlp->io_rid, M_DEVBUF);
249		ctlp->io = NULL;
250	}
251	rp_releaseresource(ctlp);
252}
253
254static int
255sPCIInitController( CONTROLLER_t *CtlP,
256		    int AiopNum,
257		    int IRQNum,
258		    Byte_t Frequency,
259		    int PeriodicOnly,
260		    int VendorDevice)
261{
262	int		i;
263
264	CtlP->CtlID = CTLID_0001;	/* controller release 1 */
265
266	sPCIControllerEOI(CtlP);
267
268	/* Init AIOPs */
269	CtlP->NumAiop = 0;
270	for(i=0; i < AiopNum; i++)
271	{
272		/*device_printf(CtlP->dev, "aiop %d.\n", i);*/
273		CtlP->AiopID[i] = sReadAiopID(CtlP, i);	/* read AIOP ID */
274		/*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/
275		if(CtlP->AiopID[i] == AIOPID_NULL)	/* if AIOP does not exist */
276		{
277			break;				/* done looking for AIOPs */
278		}
279
280		switch( VendorDevice ) {
281		case RP_DEVICE_ID_4Q:
282		case RP_DEVICE_ID_4J:
283		case RP_DEVICE_ID_4M:
284      			CtlP->AiopNumChan[i] = 4;
285			break;
286		case RP_DEVICE_ID_6M:
287      			CtlP->AiopNumChan[i] = 6;
288			break;
289		case RP_DEVICE_ID_8O:
290		case RP_DEVICE_ID_8J:
291		case RP_DEVICE_ID_8I:
292		case RP_DEVICE_ID_16I:
293		case RP_DEVICE_ID_32I:
294      			CtlP->AiopNumChan[i] = 8;
295			break;
296		default:
297#ifdef notdef
298      			CtlP->AiopNumChan[i] = 8;
299#else
300      			CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i);
301#endif /* notdef */
302			break;
303		}
304		/*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/
305		rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE);	/* clock prescaler */
306		/*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/
307		rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC);
308		/*device_printf(CtlP->dev, "configured clock prescaler.\n");*/
309		CtlP->NumAiop++;				/* bump count of AIOPs */
310	}
311
312	if(CtlP->NumAiop == 0)
313		return(-1);
314	else
315		return(CtlP->NumAiop);
316}
317
318/*
319 * ARGSUSED
320 * Maps (aiop, offset) to rid.
321 */
322static int
323rp_pci_aiop2rid(int aiop, int offset)
324{
325	/* Always return zero for a PCI controller. */
326	return 0;
327}
328
329/*
330 * ARGSUSED
331 * Maps (aiop, offset) to the offset of resource.
332 */
333static int
334rp_pci_aiop2off(int aiop, int offset)
335{
336	/* Each AIOP reserves 0x40 bytes. */
337	return aiop * 0x40 + offset;
338}
339
340/* Read the int status for a PCI controller. */
341static unsigned char
342rp_pci_ctlmask(CONTROLLER_t *ctlp)
343{
344	return sPCIGetControllerIntStatus(ctlp);
345}
346
347static device_method_t rp_pcimethods[] = {
348	/* Device interface */
349	DEVMETHOD(device_probe,		rp_pciprobe),
350	DEVMETHOD(device_attach,	rp_pciattach),
351	DEVMETHOD(device_detach,	rp_pcidetach),
352	DEVMETHOD(device_shutdown,	rp_pcishutdown),
353
354	{ 0, 0 }
355};
356
357static driver_t rp_pcidriver = {
358	"rp",
359	rp_pcimethods,
360	sizeof(CONTROLLER_t),
361};
362
363/*
364 * rp can be attached to a pci bus.
365 */
366DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0);
367