rp_pci.c revision 105215
1/* 2 * Copyright (c) Comtrol Corporation <support@comtrol.com> 3 * All rights reserved. 4 * 5 * PCI-specific part separated from: 6 * sys/i386/isa/rp.c,v 1.33 1999/09/28 11:45:27 phk Exp 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted prodived that the follwoing conditions 10 * are met. 11 * 1. Redistributions of source code must retain the above copyright 12 * notive, this list of conditions and the following disclainer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials prodided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Comtrol Corporation. 19 * 4. The name of Comtrol Corporation may not be used to endorse or 20 * promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY COMTROL CORPORATION ``AS IS'' AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL COMTROL CORPORATION BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, LIFE OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD: head/sys/dev/rp/rp_pci.c 105215 2002-10-16 08:48:39Z phk $ 36 */ 37 38#include <sys/param.h> 39#include <sys/systm.h> 40#include <sys/fcntl.h> 41#include <sys/malloc.h> 42#include <sys/tty.h> 43#include <sys/conf.h> 44#include <sys/kernel.h> 45#include <machine/resource.h> 46#include <machine/bus.h> 47#include <sys/bus.h> 48#include <sys/rman.h> 49 50#define ROCKET_C 51#include <dev/rp/rpreg.h> 52#include <dev/rp/rpvar.h> 53 54#include <pci/pcireg.h> 55#include <pci/pcivar.h> 56 57/* PCI IDs */ 58#define RP_VENDOR_ID 0x11FE 59#define RP_DEVICE_ID_32I 0x0001 60#define RP_DEVICE_ID_8I 0x0002 61#define RP_DEVICE_ID_16I 0x0003 62#define RP_DEVICE_ID_4Q 0x0004 63#define RP_DEVICE_ID_8O 0x0005 64#define RP_DEVICE_ID_8J 0x0006 65#define RP_DEVICE_ID_4J 0x0007 66#define RP_DEVICE_ID_6M 0x000C 67#define RP_DEVICE_ID_4M 0x000D 68 69/************************************************************************** 70 MUDBAC remapped for PCI 71**************************************************************************/ 72 73#define _CFG_INT_PCI 0x40 74#define _PCI_INT_FUNC 0x3A 75 76#define PCI_STROB 0x2000 77#define INTR_EN_PCI 0x0010 78 79/*************************************************************************** 80Function: sPCIControllerEOI 81Purpose: Strobe the MUDBAC's End Of Interrupt bit. 82Call: sPCIControllerEOI(CtlP) 83 CONTROLLER_T *CtlP; Ptr to controller structure 84*/ 85#define sPCIControllerEOI(CtlP) rp_writeio2(CtlP, 0, _PCI_INT_FUNC, PCI_STROB) 86 87/*************************************************************************** 88Function: sPCIGetControllerIntStatus 89Purpose: Get the controller interrupt status 90Call: sPCIGetControllerIntStatus(CtlP) 91 CONTROLLER_T *CtlP; Ptr to controller structure 92Return: Byte_t: The controller interrupt status in the lower 4 93 bits. Bits 0 through 3 represent AIOP's 0 94 through 3 respectively. If a bit is set that 95 AIOP is interrupting. Bits 4 through 7 will 96 always be cleared. 97*/ 98#define sPCIGetControllerIntStatus(CTLP) ((rp_readio2(CTLP, 0, _PCI_INT_FUNC) >> 8) & 0x1f) 99 100static devclass_t rp_devclass; 101 102static int rp_pciprobe(device_t dev); 103static int rp_pciattach(device_t dev); 104#if notdef 105static int rp_pcidetach(device_t dev); 106static int rp_pcishutdown(device_t dev); 107#endif /* notdef */ 108static void rp_pcireleaseresource(CONTROLLER_t *ctlp); 109static int sPCIInitController( CONTROLLER_t *CtlP, 110 int AiopNum, 111 int IRQNum, 112 Byte_t Frequency, 113 int PeriodicOnly, 114 int VendorDevice); 115static rp_aiop2rid_t rp_pci_aiop2rid; 116static rp_aiop2off_t rp_pci_aiop2off; 117static rp_ctlmask_t rp_pci_ctlmask; 118 119/* 120 * The following functions are the pci-specific part 121 * of rp driver. 122 */ 123 124static int 125rp_pciprobe(device_t dev) 126{ 127 char *s; 128 129 s = NULL; 130 if ((pci_get_devid(dev) & 0xffff) == RP_VENDOR_ID) 131 s = "RocketPort PCI"; 132 133 if (s != NULL) { 134 device_set_desc(dev, s); 135 return (0); 136 } 137 138 return (ENXIO); 139} 140 141static int 142rp_pciattach(device_t dev) 143{ 144 int num_ports, num_aiops; 145 int aiop; 146 CONTROLLER_t *ctlp; 147 int unit; 148 int retval; 149 u_int32_t stcmd; 150 151 ctlp = device_get_softc(dev); 152 bzero(ctlp, sizeof(*ctlp)); 153 ctlp->dev = dev; 154 unit = device_get_unit(dev); 155 ctlp->aiop2rid = rp_pci_aiop2rid; 156 ctlp->aiop2off = rp_pci_aiop2off; 157 ctlp->ctlmask = rp_pci_ctlmask; 158 159 /* Wake up the device. */ 160 stcmd = pci_read_config(dev, PCIR_COMMAND, 4); 161 if ((stcmd & PCIM_CMD_PORTEN) == 0) { 162 stcmd |= (PCIM_CMD_PORTEN); 163 pci_write_config(dev, PCIR_COMMAND, 4, stcmd); 164 } 165 166 /* The IO ports of AIOPs for a PCI controller are continuous. */ 167 ctlp->io_num = 1; 168 ctlp->io_rid = malloc(sizeof(*(ctlp->io_rid)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO); 169 ctlp->io = malloc(sizeof(*(ctlp->io)) * ctlp->io_num, M_DEVBUF, M_NOWAIT | M_ZERO); 170 if (ctlp->io_rid == NULL || ctlp->io == NULL) { 171 device_printf(dev, "rp_pciattach: Out of memory.\n"); 172 retval = ENOMEM; 173 goto nogo; 174 } 175 176 ctlp->bus_ctlp = NULL; 177 178 ctlp->io_rid[0] = 0x10; 179 ctlp->io[0] = bus_alloc_resource(dev, SYS_RES_IOPORT, &ctlp->io_rid[0], 0, ~0, 1, RF_ACTIVE); 180 if(ctlp->io[0] == NULL) { 181 device_printf(dev, "ioaddr mapping failed for RocketPort(PCI).\n"); 182 retval = ENXIO; 183 goto nogo; 184 } 185 186 num_aiops = sPCIInitController(ctlp, 187 MAX_AIOPS_PER_BOARD, 0, 188 FREQ_DIS, 0, (pci_get_devid(dev) >> 16) & 0xffff); 189 190 num_ports = 0; 191 for(aiop=0; aiop < num_aiops; aiop++) { 192 sResetAiopByNum(ctlp, aiop); 193 num_ports += sGetAiopNumChan(ctlp, aiop); 194 } 195 196 retval = rp_attachcommon(ctlp, num_aiops, num_ports); 197 if (retval != 0) 198 goto nogo; 199 200 return (0); 201 202nogo: 203 rp_pcireleaseresource(ctlp); 204 205 return (retval); 206} 207 208#if notdef 209static int 210rp_pcidetach(device_t dev) 211{ 212 CONTROLLER_t *ctlp; 213 214 if (device_get_state(dev) == DS_BUSY) 215 return (EBUSY); 216 217 ctlp = device_get_softc(dev); 218 219 rp_pcireleaseresource(ctlp); 220 221 return (0); 222} 223 224static int 225rp_pcishutdown(device_t dev) 226{ 227 CONTROLLER_t *ctlp; 228 229 if (device_get_state(dev) == DS_BUSY) 230 return (EBUSY); 231 232 ctlp = device_get_softc(dev); 233 234 rp_pcireleaseresource(ctlp); 235 236 return (0); 237} 238#endif /* notdef */ 239 240static void 241rp_pcireleaseresource(CONTROLLER_t *ctlp) 242{ 243 rp_releaseresource(ctlp); 244 245 if (ctlp->io != NULL) { 246 if (ctlp->io[0] != NULL) 247 bus_release_resource(ctlp->dev, SYS_RES_IOPORT, ctlp->io_rid[0], ctlp->io[0]); 248 free(ctlp->io, M_DEVBUF); 249 } 250 if (ctlp->io_rid != NULL) 251 free(ctlp->io_rid, M_DEVBUF); 252} 253 254static int 255sPCIInitController( CONTROLLER_t *CtlP, 256 int AiopNum, 257 int IRQNum, 258 Byte_t Frequency, 259 int PeriodicOnly, 260 int VendorDevice) 261{ 262 int i; 263 264 CtlP->CtlID = CTLID_0001; /* controller release 1 */ 265 266 sPCIControllerEOI(CtlP); 267 268 /* Init AIOPs */ 269 CtlP->NumAiop = 0; 270 for(i=0; i < AiopNum; i++) 271 { 272 /*device_printf(CtlP->dev, "aiop %d.\n", i);*/ 273 CtlP->AiopID[i] = sReadAiopID(CtlP, i); /* read AIOP ID */ 274 /*device_printf(CtlP->dev, "ID = %d.\n", CtlP->AiopID[i]);*/ 275 if(CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */ 276 { 277 break; /* done looking for AIOPs */ 278 } 279 280 switch( VendorDevice ) { 281 case RP_DEVICE_ID_4Q: 282 case RP_DEVICE_ID_4J: 283 case RP_DEVICE_ID_4M: 284 CtlP->AiopNumChan[i] = 4; 285 break; 286 case RP_DEVICE_ID_6M: 287 CtlP->AiopNumChan[i] = 6; 288 break; 289 case RP_DEVICE_ID_8O: 290 case RP_DEVICE_ID_8J: 291 case RP_DEVICE_ID_8I: 292 case RP_DEVICE_ID_16I: 293 case RP_DEVICE_ID_32I: 294 CtlP->AiopNumChan[i] = 8; 295 break; 296 default: 297#if notdef 298 CtlP->AiopNumChan[i] = 8; 299#else 300 CtlP->AiopNumChan[i] = sReadAiopNumChan(CtlP, i); 301#endif /* notdef */ 302 break; 303 } 304 /*device_printf(CtlP->dev, "%d channels.\n", CtlP->AiopNumChan[i]);*/ 305 rp_writeaiop2(CtlP, i, _INDX_ADDR,_CLK_PRE); /* clock prescaler */ 306 /*device_printf(CtlP->dev, "configuring clock prescaler.\n");*/ 307 rp_writeaiop1(CtlP, i, _INDX_DATA,CLOCK_PRESC); 308 /*device_printf(CtlP->dev, "configured clock prescaler.\n");*/ 309 CtlP->NumAiop++; /* bump count of AIOPs */ 310 } 311 312 if(CtlP->NumAiop == 0) 313 return(-1); 314 else 315 return(CtlP->NumAiop); 316} 317 318/* 319 * ARGSUSED 320 * Maps (aiop, offset) to rid. 321 */ 322static int 323rp_pci_aiop2rid(int aiop, int offset) 324{ 325 /* Always return zero for a PCI controller. */ 326 return 0; 327} 328 329/* 330 * ARGSUSED 331 * Maps (aiop, offset) to the offset of resource. 332 */ 333static int 334rp_pci_aiop2off(int aiop, int offset) 335{ 336 /* Each AIOP reserves 0x40 bytes. */ 337 return aiop * 0x40 + offset; 338} 339 340/* Read the int status for a PCI controller. */ 341static unsigned char 342rp_pci_ctlmask(CONTROLLER_t *ctlp) 343{ 344 return sPCIGetControllerIntStatus(ctlp); 345} 346 347static device_method_t rp_pcimethods[] = { 348 /* Device interface */ 349 DEVMETHOD(device_probe, rp_pciprobe), 350 DEVMETHOD(device_attach, rp_pciattach), 351#if notdef 352 DEVMETHOD(device_detach, rp_pcidetach), 353 DEVMETHOD(device_shutdown, rp_pcishutdown), 354#endif /* notdef */ 355 356 { 0, 0 } 357}; 358 359static driver_t rp_pcidriver = { 360 "rp", 361 rp_pcimethods, 362 sizeof(CONTROLLER_t), 363}; 364 365/* 366 * rp can be attached to a pci bus. 367 */ 368DRIVER_MODULE(rp, pci, rp_pcidriver, rp_devclass, 0, 0); 369