1/*- 2 * Copyright (c) 2002-2007 Neterion, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef XGE_HAL_TYPES_H 30#define XGE_HAL_TYPES_H 31 32#include <dev/nxge/include/xge-os-pal.h> 33 34__EXTERN_BEGIN_DECLS 35 36/* 37 * BIT(loc) - set bit at offset 38 */ 39#define BIT(loc) (0x8000000000000000ULL >> (loc)) 40 41/* 42 * vBIT(val, loc, sz) - set bits at offset 43 */ 44#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz))) 45#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz))) 46 47/* 48 * bVALx(bits, loc) - Get the value of x bits at location 49 */ 50#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1) 51#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3) 52#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7) 53#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF) 54#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F) 55#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F) 56#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F) 57#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF) 58#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF) 59#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF) 60#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF) 61#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF) 62#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF) 63#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF) 64#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF) 65#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF) 66#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFF) 67#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFF) 68#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFF) 69#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFF) 70#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFF) 71#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFF) 72#define bVAL60(bits, loc) ((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFF) 73 74#define XGE_HAL_BASE_INF 100 75#define XGE_HAL_BASE_ERR 200 76#define XGE_HAL_BASE_BADCFG 300 77 78#define XGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL 79 80/** 81 * enum xge_hal_status_e - HAL return codes. 82 * @XGE_HAL_OK: Success. 83 * @XGE_HAL_FAIL: Failure. 84 * @XGE_HAL_COMPLETIONS_REMAIN: There are more completions on a channel. 85 * (specific to polling mode completion processing). 86 * @XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS: No more completed 87 * descriptors. See xge_hal_fifo_dtr_next_completed(). 88 * @XGE_HAL_INF_OUT_OF_DESCRIPTORS: Out of descriptors. Channel 89 * descriptors 90 * are reserved (via xge_hal_fifo_dtr_reserve(), 91 * xge_hal_fifo_dtr_reserve()) 92 * and not yet freed (via xge_hal_fifo_dtr_free(), 93 * xge_hal_ring_dtr_free()). 94 * @XGE_HAL_INF_CHANNEL_IS_NOT_READY: Channel is not ready for 95 * operation. 96 * @XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING: Indicates that host needs to 97 * poll until PIO is executed. 98 * @XGE_HAL_INF_STATS_IS_NOT_READY: Cannot retrieve statistics because 99 * HAL and/or device is not yet initialized. 100 * @XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS: No descriptors left to 101 * reserve. Internal use only. 102 * @XGE_HAL_INF_IRQ_POLLING_CONTINUE: Returned by the ULD channel 103 * callback when instructed to exit descriptor processing loop 104 * prematurely. Typical usage: polling mode of processing completed 105 * descriptors. 106 * Upon getting LRO_ISED, ll driver shall 107 * 1) initialise lro struct with mbuf if sg_num == 1. 108 * 2) else it will update m_data_ptr_of_mbuf to tcp pointer and 109 * append the new mbuf to the tail of mbuf chain in lro struct. 110 * 111 * @XGE_HAL_INF_LRO_BEGIN: Returned by ULD LRO module, when new LRO is 112 * being initiated. 113 * @XGE_HAL_INF_LRO_CONT: Returned by ULD LRO module, when new frame 114 * is appended at the end of existing LRO. 115 * @XGE_HAL_INF_LRO_UNCAPABLE: Returned by ULD LRO module, when new 116 * frame is not LRO capable. 117 * @XGE_HAL_INF_LRO_END_1: Returned by ULD LRO module, when new frame 118 * triggers LRO flush. 119 * @XGE_HAL_INF_LRO_END_2: Returned by ULD LRO module, when new 120 * frame triggers LRO flush. Lro frame should be flushed first then 121 * new frame should be flushed next. 122 * @XGE_HAL_INF_LRO_END_3: Returned by ULD LRO module, when new 123 * frame triggers close of current LRO session and opening of new LRO session 124 * with the frame. 125 * @XGE_HAL_INF_LRO_SESSIONS_XCDED: Returned by ULD LRO module, when no 126 * more LRO sessions can be added. 127 * @XGE_HAL_INF_NOT_ENOUGH_HW_CQES: TBD 128 * @XGE_HAL_ERR_DRIVER_NOT_INITIALIZED: HAL is not initialized. 129 * @XGE_HAL_ERR_OUT_OF_MEMORY: Out of memory (example, when and 130 * allocating descriptors). 131 * @XGE_HAL_ERR_CHANNEL_NOT_FOUND: xge_hal_channel_open will return this 132 * error if corresponding channel is not configured. 133 * @XGE_HAL_ERR_WRONG_IRQ: Returned by HAL's ISR when the latter is 134 * invoked not because of the Xframe-generated interrupt. 135 * @XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES: Returned when user tries to 136 * configure more than XGE_HAL_MAX_MAC_ADDRESSES mac addresses. 137 * @XGE_HAL_ERR_BAD_DEVICE_ID: Unknown device PCI ID. 138 * @XGE_HAL_ERR_OUT_ALIGNED_FRAGS: Too many unaligned fragments 139 * in a scatter-gather list. 140 * @XGE_HAL_ERR_DEVICE_NOT_INITIALIZED: Device is not initialized. 141 * Typically means wrong sequence of API calls. 142 * @XGE_HAL_ERR_SWAPPER_CTRL: Error during device initialization: failed 143 * to set Xframe byte swapper in accordnace with the host 144 * endian-ness. 145 * @XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT: Failed to restore the device to 146 * a "quiescent" state. 147 * @XGE_HAL_ERR_INVALID_MTU_SIZE: Returned when MTU size specified by 148 * caller is not in the (64, 9600) range. 149 * @XGE_HAL_ERR_OUT_OF_MAPPING: Failed to map DMA-able memory. 150 * @XGE_HAL_ERR_BAD_SUBSYSTEM_ID: Bad PCI subsystem ID. (Currently we 151 * check for zero/non-zero only.) 152 * @XGE_HAL_ERR_INVALID_BAR_ID: Invalid BAR ID. Xframe supports two Base 153 * Address Register Spaces: BAR0 (id=0) and BAR1 (id=1). 154 * @XGE_HAL_ERR_INVALID_OFFSET: Invalid offset. Example, attempt to read 155 * register value (with offset) outside of the BAR0 space. 156 * @XGE_HAL_ERR_INVALID_DEVICE: Invalid device. The HAL device handle 157 * (passed by ULD) is invalid. 158 * @XGE_HAL_ERR_OUT_OF_SPACE: Out-of-provided-buffer-space. Returned by 159 * management "get" routines when the retrieved information does 160 * not fit into the provided buffer. 161 * @XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE: Invalid bit size. 162 * @XGE_HAL_ERR_VERSION_CONFLICT: Upper-layer driver and HAL (versions) 163 * are not compatible. 164 * @XGE_HAL_ERR_INVALID_MAC_ADDRESS: Invalid MAC address. 165 * @XGE_HAL_ERR_SPDM_NOT_ENABLED: SPDM support is not enabled. 166 * @XGE_HAL_ERR_SPDM_TABLE_FULL: SPDM table is full. 167 * @XGE_HAL_ERR_SPDM_INVALID_ENTRY: Invalid SPDM entry. 168 * @XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND: Unable to locate the entry in the 169 * SPDM table. 170 * @XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT: Local SPDM table is not in 171 * synch ith the actual one. 172 * @XGE_HAL_ERR_INVALID_PCI_INFO: Invalid or unrecognized PCI frequency, 173 * and or width, and or mode (Xframe-II only, see UG on PCI_INFO register). 174 * @XGE_HAL_ERR_CRITICAL: Critical error. Returned by HAL APIs 175 * (including xge_hal_device_handle_tcode()) on: ECC, parity, SERR. 176 * Also returned when PIO read does not go through ("all-foxes") 177 * because of "slot-freeze". 178 * @XGE_HAL_ERR_RESET_FAILED: Failed to soft-reset the device. 179 * Returned by xge_hal_device_reset(). One circumstance when it could 180 * happen: slot freeze by the system (see @XGE_HAL_ERR_CRITICAL). 181 * @XGE_HAL_ERR_TOO_MANY: This error is returned if there were laready 182 * maximum number of sessions or queues allocated 183 * @XGE_HAL_ERR_PKT_DROP: TBD 184 * @XGE_HAL_BADCFG_TX_URANGE_A: Invalid Tx link utilization range A. See 185 * the structure xge_hal_tti_config_t{} for valid values. 186 * @XGE_HAL_BADCFG_TX_UFC_A: Invalid frame count for Tx link utilization 187 * range A. See the structure xge_hal_tti_config_t{} for valid values. 188 * @XGE_HAL_BADCFG_TX_URANGE_B: Invalid Tx link utilization range B. See 189 * the structure xge_hal_tti_config_t{} for valid values. 190 * @XGE_HAL_BADCFG_TX_UFC_B: Invalid frame count for Tx link utilization 191 * range B. See the strucuture xge_hal_tti_config_t{} for valid values. 192 * @XGE_HAL_BADCFG_TX_URANGE_C: Invalid Tx link utilization range C. See 193 * the structure xge_hal_tti_config_t{} for valid values. 194 * @XGE_HAL_BADCFG_TX_UFC_C: Invalid frame count for Tx link utilization 195 * range C. See the structure xge_hal_tti_config_t{} for valid values. 196 * @XGE_HAL_BADCFG_TX_UFC_D: Invalid frame count for Tx link utilization 197 * range D. See the structure xge_hal_tti_config_t{} for valid values. 198 * @XGE_HAL_BADCFG_TX_TIMER_VAL: Invalid Tx timer value. See the 199 * structure xge_hal_tti_config_t{} for valid values. 200 * @XGE_HAL_BADCFG_TX_TIMER_CI_EN: Invalid Tx timer continuous interrupt 201 * enable. See the structure xge_hal_tti_config_t{} for valid values. 202 * @XGE_HAL_BADCFG_RX_URANGE_A: Invalid Rx link utilization range A. See 203 * the structure xge_hal_rti_config_t{} for valid values. 204 * @XGE_HAL_BADCFG_RX_UFC_A: Invalid frame count for Rx link utilization 205 * range A. See the structure xge_hal_rti_config_t{} for valid values. 206 * @XGE_HAL_BADCFG_RX_URANGE_B: Invalid Rx link utilization range B. See 207 * the structure xge_hal_rti_config_t{} for valid values. 208 * @XGE_HAL_BADCFG_RX_UFC_B: Invalid frame count for Rx link utilization 209 * range B. See the structure xge_hal_rti_config_t{} for valid values. 210 * @XGE_HAL_BADCFG_RX_URANGE_C: Invalid Rx link utilization range C. See 211 * the structure xge_hal_rti_config_t{} for valid values. 212 * @XGE_HAL_BADCFG_RX_UFC_C: Invalid frame count for Rx link utilization 213 * range C. See the structure xge_hal_rti_config_t{} for valid values. 214 * @XGE_HAL_BADCFG_RX_UFC_D: Invalid frame count for Rx link utilization 215 * range D. See the structure xge_hal_rti_config_t{} for valid values. 216 * @XGE_HAL_BADCFG_RX_TIMER_VAL: Invalid Rx timer value. See the 217 * structure xge_hal_rti_config_t{} for valid values. 218 * @XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH: Invalid initial fifo queue 219 * length. See the structure xge_hal_fifo_queue_t for valid values. 220 * @XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH: Invalid fifo queue max length. 221 * See the structure xge_hal_fifo_queue_t for valid values. 222 * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR: Invalid fifo queue interrupt mode. 223 * See the structure xge_hal_fifo_queue_t for valid values. 224 * @XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS: Invalid Initial number of 225 * RxD blocks for the ring. See the structure xge_hal_ring_queue_t for 226 * valid values. 227 * @XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS: Invalid maximum number of RxD 228 * blocks for the ring. See the structure xge_hal_ring_queue_t for 229 * valid values. 230 * @XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE: Invalid ring buffer mode. See 231 * the structure xge_hal_ring_queue_t for valid values. 232 * @XGE_HAL_BADCFG_RING_QUEUE_SIZE: Invalid ring queue size. See the 233 * structure xge_hal_ring_queue_t for valid values. 234 * @XGE_HAL_BADCFG_BACKOFF_INTERVAL_US: Invalid backoff timer interval 235 * for the ring. See the structure xge_hal_ring_queue_t for valid values. 236 * @XGE_HAL_BADCFG_MAX_FRM_LEN: Invalid ring max frame length. See the 237 * structure xge_hal_ring_queue_t for valid values. 238 * @XGE_HAL_BADCFG_RING_PRIORITY: Invalid ring priority. See the 239 * structure xge_hal_ring_queue_t for valid values. 240 * @XGE_HAL_BADCFG_TMAC_UTIL_PERIOD: Invalid tmac util period. See the 241 * structure xge_hal_mac_config_t{} for valid values. 242 * @XGE_HAL_BADCFG_RMAC_UTIL_PERIOD: Invalid rmac util period. See the 243 * structure xge_hal_mac_config_t{} for valid values. 244 * @XGE_HAL_BADCFG_RMAC_BCAST_EN: Invalid rmac brodcast enable. See the 245 * structure xge_hal_mac_config_t{} for valid values. 246 * @XGE_HAL_BADCFG_RMAC_HIGH_PTIME: Invalid rmac pause time. See the 247 * structure xge_hal_mac_config_t{} for valid values. 248 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3: Invalid threshold for pause 249 * frame generation for queues 0 through 3. See the structure 250 * xge_hal_mac_config_t{} for valid values. 251 * @XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7:Invalid threshold for pause 252 * frame generation for queues 4 through 7. See the structure 253 * xge_hal_mac_config_t{} for valid values. 254 * @XGE_HAL_BADCFG_FIFO_FRAGS: Invalid fifo max fragments length. See 255 * the structure xge_hal_fifo_config_t{} for valid values. 256 * @XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD: Invalid fifo reserve 257 * threshold. See the structure xge_hal_fifo_config_t{} for valid values. 258 * @XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE: Invalid fifo descriptors memblock 259 * size. See the structure xge_hal_fifo_config_t{} for valid values. 260 * @XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE: Invalid ring descriptors memblock 261 * size. See the structure xge_hal_ring_config_t{} for valid values. 262 * @XGE_HAL_BADCFG_MAX_MTU: Invalid max mtu for the device. See the 263 * structure xge_hal_device_config_t{} for valid values. 264 * @XGE_HAL_BADCFG_ISR_POLLING_CNT: Invalid isr polling count. See the 265 * structure xge_hal_device_config_t{} for valid values. 266 * @XGE_HAL_BADCFG_LATENCY_TIMER: Invalid Latency timer. See the 267 * structure xge_hal_device_config_t{} for valid values. 268 * @XGE_HAL_BADCFG_MAX_SPLITS_TRANS: Invalid maximum number of pci-x 269 * split transactions. See the structure xge_hal_device_config_t{} for valid 270 * values. 271 * @XGE_HAL_BADCFG_MMRB_COUNT: Invalid mmrb count. See the structure 272 * xge_hal_device_config_t{} for valid values. 273 * @XGE_HAL_BADCFG_SHARED_SPLITS: Invalid number of outstanding split 274 * transactions that is shared by Tx and Rx requests. See the structure 275 * xge_hal_device_config_t{} for valid values. 276 * @XGE_HAL_BADCFG_STATS_REFRESH_TIME: Invalid time interval for 277 * automatic statistics transfer to the host. See the structure 278 * xge_hal_device_config_t{} for valid values. 279 * @XGE_HAL_BADCFG_PCI_FREQ_MHERZ: Invalid pci clock frequency. See the 280 * structure xge_hal_device_config_t{} for valid values. 281 * @XGE_HAL_BADCFG_PCI_MODE: Invalid pci mode. See the structure 282 * xge_hal_device_config_t{} for valid values. 283 * @XGE_HAL_BADCFG_INTR_MODE: Invalid interrupt mode. See the structure 284 * xge_hal_device_config_t{} for valid values. 285 * @XGE_HAL_BADCFG_SCHED_TIMER_US: Invalid scheduled timer interval to 286 * generate interrupt. See the structure xge_hal_device_config_t{} 287 * for valid values. 288 * @XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT: Invalid scheduled timer one 289 * shot. See the structure xge_hal_device_config_t{} for valid values. 290 * @XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL: Invalid driver queue initial 291 * size. See the structure xge_hal_driver_config_t{} for valid values. 292 * @XGE_HAL_BADCFG_QUEUE_SIZE_MAX: Invalid driver queue max size. See 293 * the structure xge_hal_driver_config_t{} for valid values. 294 * @XGE_HAL_BADCFG_RING_RTH_EN: Invalid value of RTH-enable. See 295 * the structure xge_hal_ring_queue_t for valid values. 296 * @XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS: Invalid value configured for 297 * indicate_max_pkts variable. 298 * @XGE_HAL_BADCFG_TX_TIMER_AC_EN: Invalid value for Tx timer 299 * auto-cancel. See xge_hal_tti_config_t{}. 300 * @XGE_HAL_BADCFG_RX_TIMER_AC_EN: Invalid value for Rx timer 301 * auto-cancel. See xge_hal_rti_config_t{}. 302 * @XGE_HAL_BADCFG_RXUFCA_INTR_THRES: TODO 303 * @XGE_HAL_BADCFG_RXUFCA_LO_LIM: TODO 304 * @XGE_HAL_BADCFG_RXUFCA_HI_LIM: TODO 305 * @XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD: TODO 306 * @XGE_HAL_BADCFG_TRACEBUF_SIZE: Bad configuration: the size of the circular 307 * (in memory) trace buffer either too large or too small. See the 308 * the corresponding header file or README for the acceptable range. 309 * @XGE_HAL_BADCFG_LINK_VALID_CNT: Bad configuration: the link-valid 310 * counter cannot have the specified value. Note that the link-valid 311 * counting is done only at device-open time, to determine with the 312 * specified certainty that the link is up. See the 313 * the corresponding header file or README for the acceptable range. 314 * See also @XGE_HAL_BADCFG_LINK_RETRY_CNT. 315 * @XGE_HAL_BADCFG_LINK_RETRY_CNT: Bad configuration: the specified 316 * link-up retry count is out of the valid range. Note that the link-up 317 * retry counting is done only at device-open time. 318 * See also xge_hal_device_config_t{}. 319 * @XGE_HAL_BADCFG_LINK_STABILITY_PERIOD: Invalid link stability period. 320 * @XGE_HAL_BADCFG_DEVICE_POLL_MILLIS: Invalid device poll interval. 321 * @XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN: TBD 322 * @XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN: TBD 323 * @XGE_HAL_BADCFG_MEDIA: TBD 324 * @XGE_HAL_BADCFG_NO_ISR_EVENTS: TBD 325 * See the structure xge_hal_device_config_t{} for valid values. 326 * @XGE_HAL_EOF_TRACE_BUF: End of the circular (in memory) trace buffer. 327 * Returned by xge_hal_mgmt_trace_read(), when user tries to read the trace 328 * past the buffer limits. Used to enable user to load the trace in two 329 * or more reads. 330 * @XGE_HAL_BADCFG_RING_RTS_MAC_EN: Invalid value of RTS_MAC_EN enable. See 331 * the structure xge_hal_ring_queue_t for valid values. 332 * @XGE_HAL_BADCFG_LRO_SG_SIZE : Invalid value of LRO scatter gatter size. 333 * See the structure xge_hal_device_config_t for valid values. 334 * @XGE_HAL_BADCFG_LRO_FRM_LEN : Invalid value of LRO frame length. 335 * See the structure xge_hal_device_config_t for valid values. 336 * @XGE_HAL_BADCFG_WQE_NUM_ODS: TBD 337 * @XGE_HAL_BADCFG_BIMODAL_INTR: Invalid value to configure bimodal interrupts 338 * Enumerates status and error codes returned by HAL public 339 * API functions. 340 * @XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US: TBD 341 * @XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US: TBD 342 * @XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED: TBD 343 * @XGE_HAL_BADCFG_RTS_QOS_EN: TBD 344 * @XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR: TBD 345 * @XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR: TBD 346 * @XGE_HAL_BADCFG_RTS_PORT_EN: TBD 347 * @XGE_HAL_BADCFG_RING_RTS_PORT_EN: TBD 348 * 349 */ 350typedef enum xge_hal_status_e { 351 XGE_HAL_OK = 0, 352 XGE_HAL_FAIL = 1, 353 XGE_HAL_COMPLETIONS_REMAIN = 2, 354 355 XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS = XGE_HAL_BASE_INF + 1, 356 XGE_HAL_INF_OUT_OF_DESCRIPTORS = XGE_HAL_BASE_INF + 2, 357 XGE_HAL_INF_CHANNEL_IS_NOT_READY = XGE_HAL_BASE_INF + 3, 358 XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING = XGE_HAL_BASE_INF + 4, 359 XGE_HAL_INF_STATS_IS_NOT_READY = XGE_HAL_BASE_INF + 5, 360 XGE_HAL_INF_NO_MORE_FREED_DESCRIPTORS = XGE_HAL_BASE_INF + 6, 361 XGE_HAL_INF_IRQ_POLLING_CONTINUE = XGE_HAL_BASE_INF + 7, 362 XGE_HAL_INF_LRO_BEGIN = XGE_HAL_BASE_INF + 8, 363 XGE_HAL_INF_LRO_CONT = XGE_HAL_BASE_INF + 9, 364 XGE_HAL_INF_LRO_UNCAPABLE = XGE_HAL_BASE_INF + 10, 365 XGE_HAL_INF_LRO_END_1 = XGE_HAL_BASE_INF + 11, 366 XGE_HAL_INF_LRO_END_2 = XGE_HAL_BASE_INF + 12, 367 XGE_HAL_INF_LRO_END_3 = XGE_HAL_BASE_INF + 13, 368 XGE_HAL_INF_LRO_SESSIONS_XCDED = XGE_HAL_BASE_INF + 14, 369 XGE_HAL_INF_NOT_ENOUGH_HW_CQES = XGE_HAL_BASE_INF + 15, 370 XGE_HAL_ERR_DRIVER_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 1, 371 XGE_HAL_ERR_OUT_OF_MEMORY = XGE_HAL_BASE_ERR + 4, 372 XGE_HAL_ERR_CHANNEL_NOT_FOUND = XGE_HAL_BASE_ERR + 5, 373 XGE_HAL_ERR_WRONG_IRQ = XGE_HAL_BASE_ERR + 6, 374 XGE_HAL_ERR_OUT_OF_MAC_ADDRESSES = XGE_HAL_BASE_ERR + 7, 375 XGE_HAL_ERR_SWAPPER_CTRL = XGE_HAL_BASE_ERR + 8, 376 XGE_HAL_ERR_DEVICE_IS_NOT_QUIESCENT = XGE_HAL_BASE_ERR + 9, 377 XGE_HAL_ERR_INVALID_MTU_SIZE = XGE_HAL_BASE_ERR + 10, 378 XGE_HAL_ERR_OUT_OF_MAPPING = XGE_HAL_BASE_ERR + 11, 379 XGE_HAL_ERR_BAD_SUBSYSTEM_ID = XGE_HAL_BASE_ERR + 12, 380 XGE_HAL_ERR_INVALID_BAR_ID = XGE_HAL_BASE_ERR + 13, 381 XGE_HAL_ERR_INVALID_OFFSET = XGE_HAL_BASE_ERR + 14, 382 XGE_HAL_ERR_INVALID_DEVICE = XGE_HAL_BASE_ERR + 15, 383 XGE_HAL_ERR_OUT_OF_SPACE = XGE_HAL_BASE_ERR + 16, 384 XGE_HAL_ERR_INVALID_VALUE_BIT_SIZE = XGE_HAL_BASE_ERR + 17, 385 XGE_HAL_ERR_VERSION_CONFLICT = XGE_HAL_BASE_ERR + 18, 386 XGE_HAL_ERR_INVALID_MAC_ADDRESS = XGE_HAL_BASE_ERR + 19, 387 XGE_HAL_ERR_BAD_DEVICE_ID = XGE_HAL_BASE_ERR + 20, 388 XGE_HAL_ERR_OUT_ALIGNED_FRAGS = XGE_HAL_BASE_ERR + 21, 389 XGE_HAL_ERR_DEVICE_NOT_INITIALIZED = XGE_HAL_BASE_ERR + 22, 390 XGE_HAL_ERR_SPDM_NOT_ENABLED = XGE_HAL_BASE_ERR + 23, 391 XGE_HAL_ERR_SPDM_TABLE_FULL = XGE_HAL_BASE_ERR + 24, 392 XGE_HAL_ERR_SPDM_INVALID_ENTRY = XGE_HAL_BASE_ERR + 25, 393 XGE_HAL_ERR_SPDM_ENTRY_NOT_FOUND = XGE_HAL_BASE_ERR + 26, 394 XGE_HAL_ERR_SPDM_TABLE_DATA_INCONSISTENT= XGE_HAL_BASE_ERR + 27, 395 XGE_HAL_ERR_INVALID_PCI_INFO = XGE_HAL_BASE_ERR + 28, 396 XGE_HAL_ERR_CRITICAL = XGE_HAL_BASE_ERR + 29, 397 XGE_HAL_ERR_RESET_FAILED = XGE_HAL_BASE_ERR + 30, 398 XGE_HAL_ERR_TOO_MANY = XGE_HAL_BASE_ERR + 32, 399 XGE_HAL_ERR_PKT_DROP = XGE_HAL_BASE_ERR + 33, 400 401 XGE_HAL_BADCFG_TX_URANGE_A = XGE_HAL_BASE_BADCFG + 1, 402 XGE_HAL_BADCFG_TX_UFC_A = XGE_HAL_BASE_BADCFG + 2, 403 XGE_HAL_BADCFG_TX_URANGE_B = XGE_HAL_BASE_BADCFG + 3, 404 XGE_HAL_BADCFG_TX_UFC_B = XGE_HAL_BASE_BADCFG + 4, 405 XGE_HAL_BADCFG_TX_URANGE_C = XGE_HAL_BASE_BADCFG + 5, 406 XGE_HAL_BADCFG_TX_UFC_C = XGE_HAL_BASE_BADCFG + 6, 407 XGE_HAL_BADCFG_TX_UFC_D = XGE_HAL_BASE_BADCFG + 8, 408 XGE_HAL_BADCFG_TX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 9, 409 XGE_HAL_BADCFG_TX_TIMER_CI_EN = XGE_HAL_BASE_BADCFG + 10, 410 XGE_HAL_BADCFG_RX_URANGE_A = XGE_HAL_BASE_BADCFG + 11, 411 XGE_HAL_BADCFG_RX_UFC_A = XGE_HAL_BASE_BADCFG + 12, 412 XGE_HAL_BADCFG_RX_URANGE_B = XGE_HAL_BASE_BADCFG + 13, 413 XGE_HAL_BADCFG_RX_UFC_B = XGE_HAL_BASE_BADCFG + 14, 414 XGE_HAL_BADCFG_RX_URANGE_C = XGE_HAL_BASE_BADCFG + 15, 415 XGE_HAL_BADCFG_RX_UFC_C = XGE_HAL_BASE_BADCFG + 16, 416 XGE_HAL_BADCFG_RX_UFC_D = XGE_HAL_BASE_BADCFG + 17, 417 XGE_HAL_BADCFG_RX_TIMER_VAL = XGE_HAL_BASE_BADCFG + 18, 418 XGE_HAL_BADCFG_FIFO_QUEUE_INITIAL_LENGTH= XGE_HAL_BASE_BADCFG + 19, 419 XGE_HAL_BADCFG_FIFO_QUEUE_MAX_LENGTH = XGE_HAL_BASE_BADCFG + 20, 420 XGE_HAL_BADCFG_FIFO_QUEUE_INTR = XGE_HAL_BASE_BADCFG + 21, 421 XGE_HAL_BADCFG_RING_QUEUE_INITIAL_BLOCKS=XGE_HAL_BASE_BADCFG + 22, 422 XGE_HAL_BADCFG_RING_QUEUE_MAX_BLOCKS = XGE_HAL_BASE_BADCFG + 23, 423 XGE_HAL_BADCFG_RING_QUEUE_BUFFER_MODE = XGE_HAL_BASE_BADCFG + 24, 424 XGE_HAL_BADCFG_RING_QUEUE_SIZE = XGE_HAL_BASE_BADCFG + 25, 425 XGE_HAL_BADCFG_BACKOFF_INTERVAL_US = XGE_HAL_BASE_BADCFG + 26, 426 XGE_HAL_BADCFG_MAX_FRM_LEN = XGE_HAL_BASE_BADCFG + 27, 427 XGE_HAL_BADCFG_RING_PRIORITY = XGE_HAL_BASE_BADCFG + 28, 428 XGE_HAL_BADCFG_TMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 29, 429 XGE_HAL_BADCFG_RMAC_UTIL_PERIOD = XGE_HAL_BASE_BADCFG + 30, 430 XGE_HAL_BADCFG_RMAC_BCAST_EN = XGE_HAL_BASE_BADCFG + 31, 431 XGE_HAL_BADCFG_RMAC_HIGH_PTIME = XGE_HAL_BASE_BADCFG + 32, 432 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q0Q3 = XGE_HAL_BASE_BADCFG +33, 433 XGE_HAL_BADCFG_MC_PAUSE_THRESHOLD_Q4Q7 = XGE_HAL_BASE_BADCFG + 34, 434 XGE_HAL_BADCFG_FIFO_FRAGS = XGE_HAL_BASE_BADCFG + 35, 435 XGE_HAL_BADCFG_FIFO_RESERVE_THRESHOLD = XGE_HAL_BASE_BADCFG + 37, 436 XGE_HAL_BADCFG_FIFO_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 38, 437 XGE_HAL_BADCFG_RING_MEMBLOCK_SIZE = XGE_HAL_BASE_BADCFG + 39, 438 XGE_HAL_BADCFG_MAX_MTU = XGE_HAL_BASE_BADCFG + 40, 439 XGE_HAL_BADCFG_ISR_POLLING_CNT = XGE_HAL_BASE_BADCFG + 41, 440 XGE_HAL_BADCFG_LATENCY_TIMER = XGE_HAL_BASE_BADCFG + 42, 441 XGE_HAL_BADCFG_MAX_SPLITS_TRANS = XGE_HAL_BASE_BADCFG + 43, 442 XGE_HAL_BADCFG_MMRB_COUNT = XGE_HAL_BASE_BADCFG + 44, 443 XGE_HAL_BADCFG_SHARED_SPLITS = XGE_HAL_BASE_BADCFG + 45, 444 XGE_HAL_BADCFG_STATS_REFRESH_TIME = XGE_HAL_BASE_BADCFG + 46, 445 XGE_HAL_BADCFG_PCI_FREQ_MHERZ = XGE_HAL_BASE_BADCFG + 47, 446 XGE_HAL_BADCFG_PCI_MODE = XGE_HAL_BASE_BADCFG + 48, 447 XGE_HAL_BADCFG_INTR_MODE = XGE_HAL_BASE_BADCFG + 49, 448 XGE_HAL_BADCFG_SCHED_TIMER_US = XGE_HAL_BASE_BADCFG + 50, 449 XGE_HAL_BADCFG_SCHED_TIMER_ON_SHOT = XGE_HAL_BASE_BADCFG + 51, 450 XGE_HAL_BADCFG_QUEUE_SIZE_INITIAL = XGE_HAL_BASE_BADCFG + 52, 451 XGE_HAL_BADCFG_QUEUE_SIZE_MAX = XGE_HAL_BASE_BADCFG + 53, 452 XGE_HAL_BADCFG_RING_RTH_EN = XGE_HAL_BASE_BADCFG + 54, 453 XGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS = XGE_HAL_BASE_BADCFG + 55, 454 XGE_HAL_BADCFG_TX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 56, 455 XGE_HAL_BADCFG_RX_TIMER_AC_EN = XGE_HAL_BASE_BADCFG + 57, 456 XGE_HAL_BADCFG_RXUFCA_INTR_THRES = XGE_HAL_BASE_BADCFG + 58, 457 XGE_HAL_BADCFG_RXUFCA_LO_LIM = XGE_HAL_BASE_BADCFG + 59, 458 XGE_HAL_BADCFG_RXUFCA_HI_LIM = XGE_HAL_BASE_BADCFG + 60, 459 XGE_HAL_BADCFG_RXUFCA_LBOLT_PERIOD = XGE_HAL_BASE_BADCFG + 61, 460 XGE_HAL_BADCFG_TRACEBUF_SIZE = XGE_HAL_BASE_BADCFG + 62, 461 XGE_HAL_BADCFG_LINK_VALID_CNT = XGE_HAL_BASE_BADCFG + 63, 462 XGE_HAL_BADCFG_LINK_RETRY_CNT = XGE_HAL_BASE_BADCFG + 64, 463 XGE_HAL_BADCFG_LINK_STABILITY_PERIOD = XGE_HAL_BASE_BADCFG + 65, 464 XGE_HAL_BADCFG_DEVICE_POLL_MILLIS = XGE_HAL_BASE_BADCFG + 66, 465 XGE_HAL_BADCFG_RMAC_PAUSE_GEN_EN = XGE_HAL_BASE_BADCFG + 67, 466 XGE_HAL_BADCFG_RMAC_PAUSE_RCV_EN = XGE_HAL_BASE_BADCFG + 68, 467 XGE_HAL_BADCFG_MEDIA = XGE_HAL_BASE_BADCFG + 69, 468 XGE_HAL_BADCFG_NO_ISR_EVENTS = XGE_HAL_BASE_BADCFG + 70, 469 XGE_HAL_BADCFG_RING_RTS_MAC_EN = XGE_HAL_BASE_BADCFG + 71, 470 XGE_HAL_BADCFG_LRO_SG_SIZE = XGE_HAL_BASE_BADCFG + 72, 471 XGE_HAL_BADCFG_LRO_FRM_LEN = XGE_HAL_BASE_BADCFG + 73, 472 XGE_HAL_BADCFG_WQE_NUM_ODS = XGE_HAL_BASE_BADCFG + 74, 473 XGE_HAL_BADCFG_BIMODAL_INTR = XGE_HAL_BASE_BADCFG + 75, 474 XGE_HAL_BADCFG_BIMODAL_TIMER_LO_US = XGE_HAL_BASE_BADCFG + 76, 475 XGE_HAL_BADCFG_BIMODAL_TIMER_HI_US = XGE_HAL_BASE_BADCFG + 77, 476 XGE_HAL_BADCFG_BIMODAL_XENA_NOT_ALLOWED = XGE_HAL_BASE_BADCFG + 78, 477 XGE_HAL_BADCFG_RTS_QOS_EN = XGE_HAL_BASE_BADCFG + 79, 478 XGE_HAL_BADCFG_FIFO_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 80, 479 XGE_HAL_BADCFG_RING_QUEUE_INTR_VECTOR = XGE_HAL_BASE_BADCFG + 81, 480 XGE_HAL_BADCFG_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 82, 481 XGE_HAL_BADCFG_RING_RTS_PORT_EN = XGE_HAL_BASE_BADCFG + 83, 482 XGE_HAL_BADCFG_TRACEBUF_TIMESTAMP = XGE_HAL_BASE_BADCFG + 84, 483 XGE_HAL_EOF_TRACE_BUF = -1 484} xge_hal_status_e; 485 486#define XGE_HAL_ETH_ALEN 6 487typedef u8 macaddr_t[XGE_HAL_ETH_ALEN]; 488 489#define XGE_HAL_PCI_XFRAME_CONFIG_SPACE_SIZE 0x100 490 491/* frames sizes */ 492#define XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14 493#define XGE_HAL_HEADER_802_2_SIZE 3 494#define XGE_HAL_HEADER_SNAP_SIZE 5 495#define XGE_HAL_HEADER_VLAN_SIZE 4 496#define XGE_HAL_MAC_HEADER_MAX_SIZE \ 497 (XGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \ 498 XGE_HAL_HEADER_802_2_SIZE + \ 499 XGE_HAL_HEADER_SNAP_SIZE) 500 501#define XGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64) 502 503/* 32bit alignments */ 504#define XGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 2 505#define XGE_HAL_HEADER_802_2_SNAP_ALIGN 2 506#define XGE_HAL_HEADER_802_2_ALIGN 3 507#define XGE_HAL_HEADER_SNAP_ALIGN 1 508 509#define XGE_HAL_L3_CKSUM_OK 0xFFFF 510#define XGE_HAL_L4_CKSUM_OK 0xFFFF 511#define XGE_HAL_MIN_MTU 46 512#define XGE_HAL_MAX_MTU 9600 513#define XGE_HAL_DEFAULT_MTU 1500 514 515#define XGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920 516 517#define XGE_HAL_PCISIZE_XENA 26 /* multiples of dword */ 518#define XGE_HAL_PCISIZE_HERC 64 /* multiples of dword */ 519 520#define XGE_HAL_MAX_MSIX_MESSAGES 64 521#define XGE_HAL_MAX_MSIX_MESSAGES_WITH_ADDR XGE_HAL_MAX_MSIX_MESSAGES * 2 522/* Highest level interrupt blocks */ 523#define XGE_HAL_TX_PIC_INTR (0x0001<<0) 524#define XGE_HAL_TX_DMA_INTR (0x0001<<1) 525#define XGE_HAL_TX_MAC_INTR (0x0001<<2) 526#define XGE_HAL_TX_XGXS_INTR (0x0001<<3) 527#define XGE_HAL_TX_TRAFFIC_INTR (0x0001<<4) 528#define XGE_HAL_RX_PIC_INTR (0x0001<<5) 529#define XGE_HAL_RX_DMA_INTR (0x0001<<6) 530#define XGE_HAL_RX_MAC_INTR (0x0001<<7) 531#define XGE_HAL_RX_XGXS_INTR (0x0001<<8) 532#define XGE_HAL_RX_TRAFFIC_INTR (0x0001<<9) 533#define XGE_HAL_MC_INTR (0x0001<<10) 534#define XGE_HAL_SCHED_INTR (0x0001<<11) 535#define XGE_HAL_ALL_INTRS (XGE_HAL_TX_PIC_INTR | \ 536 XGE_HAL_TX_DMA_INTR | \ 537 XGE_HAL_TX_MAC_INTR | \ 538 XGE_HAL_TX_XGXS_INTR | \ 539 XGE_HAL_TX_TRAFFIC_INTR | \ 540 XGE_HAL_RX_PIC_INTR | \ 541 XGE_HAL_RX_DMA_INTR | \ 542 XGE_HAL_RX_MAC_INTR | \ 543 XGE_HAL_RX_XGXS_INTR | \ 544 XGE_HAL_RX_TRAFFIC_INTR | \ 545 XGE_HAL_MC_INTR | \ 546 XGE_HAL_SCHED_INTR) 547#define XGE_HAL_GEN_MASK_INTR (0x0001<<12) 548 549/* Interrupt masks for the general interrupt mask register */ 550#define XGE_HAL_ALL_INTRS_DIS 0xFFFFFFFFFFFFFFFFULL 551 552#define XGE_HAL_TXPIC_INT_M BIT(0) 553#define XGE_HAL_TXDMA_INT_M BIT(1) 554#define XGE_HAL_TXMAC_INT_M BIT(2) 555#define XGE_HAL_TXXGXS_INT_M BIT(3) 556#define XGE_HAL_TXTRAFFIC_INT_M BIT(8) 557#define XGE_HAL_PIC_RX_INT_M BIT(32) 558#define XGE_HAL_RXDMA_INT_M BIT(33) 559#define XGE_HAL_RXMAC_INT_M BIT(34) 560#define XGE_HAL_MC_INT_M BIT(35) 561#define XGE_HAL_RXXGXS_INT_M BIT(36) 562#define XGE_HAL_RXTRAFFIC_INT_M BIT(40) 563 564/* MSI level Interrupts */ 565#define XGE_HAL_MAX_MSIX_VECTORS (16) 566 567typedef struct xge_hal_ipv4 { 568 u32 addr; 569}xge_hal_ipv4; 570 571typedef struct xge_hal_ipv6 { 572 u64 addr[2]; 573}xge_hal_ipv6; 574 575typedef union xge_hal_ipaddr_t { 576 xge_hal_ipv4 ipv4; 577 xge_hal_ipv6 ipv6; 578}xge_hal_ipaddr_t; 579 580/* DMA level Interrupts */ 581#define XGE_HAL_TXDMA_PFC_INT_M BIT(0) 582 583/* PFC block interrupts */ 584#define XGE_HAL_PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO 585full */ 586 587/* basic handles */ 588typedef void* xge_hal_device_h; 589typedef void* xge_hal_dtr_h; 590typedef void* xge_hal_channel_h; 591 592/* 593 * I2C device id. Used in I2C control register for accessing EEPROM device 594 * memory. 595 */ 596#define XGE_DEV_ID 5 597 598typedef enum xge_hal_xpak_alarm_type_e { 599 XGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 600 XGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 601 XGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 602} xge_hal_xpak_alarm_type_e; 603 604 605__EXTERN_END_DECLS 606 607#endif /* XGE_HAL_TYPES_H */ 608