1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36#define NGE_CSR 0x00 37#define NGE_CFG 0x04 38#define NGE_MEAR 0x08 39#define NGE_PCITST 0x0C 40#define NGE_ISR 0x10 41#define NGE_IMR 0x14 42#define NGE_IER 0x18 43#define NGE_IHR 0x1C 44#define NGE_TX_LISTPTR_LO 0x20 45#define NGE_TX_LISTPTR_HI 0x24 46#define NGE_TX_LISTPTR NGE_TX_LISTPTR_LO 47#define NGE_TX_CFG 0x28 48#define NGE_GPIO 0x2C 49#define NGE_RX_LISTPTR_LO 0x30 50#define NGE_RX_LISTPTR_HI 0x34 51#define NGE_RX_LISTPTR NGE_RX_LISTPTR_LO 52#define NGE_RX_CFG 0x38 53#define NGE_PRIOQCTL 0x3C 54#define NGE_WOLCSR 0x40 55#define NGE_PAUSECSR 0x44 56#define NGE_RXFILT_CTL 0x48 57#define NGE_RXFILT_DATA 0x4C 58#define NGE_BOOTROM_ADDR 0x50 59#define NGE_BOOTROM_DATA 0x54 60#define NGE_SILICONREV 0x58 61#define NGE_MIBCTL 0x5C 62#define NGE_MIB_RXERRPKT 0x60 63#define NGE_MIB_RXERRFCS 0x64 64#define NGE_MIB_RXERRMISSEDPKT 0x68 65#define NGE_MIB_RXERRALIGN 0x6C 66#define NGE_MIB_RXERRSYM 0x70 67#define NGE_MIB_RXERRGIANT 0x74 68#define NGE_MIB_RXERRRANGLEN 0x78 69#define NGE_MIB_RXBADOPCODE 0x7C 70#define NGE_MIB_RXPAUSEPKTS 0x80 71#define NGE_MIB_TXPAUSEPKTS 0x84 72#define NGE_MIB_TXERRSQE 0x88 73#define NGE_TXPRIOQ_PTR1 0xA0 74#define NGE_TXPRIOQ_PTR2 0xA4 75#define NGE_TXPRIOQ_PTR3 0xA8 76#define NGE_RXPRIOQ_PTR1 0xB0 77#define NGE_RXPRIOQ_PTR2 0xB4 78#define NGE_RXPRIOQ_PTR3 0xB8 79#define NGE_VLAN_IP_RXCTL 0xBC 80#define NGE_VLAN_IP_TXCTL 0xC0 81#define NGE_VLAN_DATA 0xC4 82#define NGE_CLKRUN 0xCC 83#define NGE_TBI_BMCR 0xE0 84#define NGE_TBI_BMSR 0xE4 85#define NGE_TBI_ANAR 0xE8 86#define NGE_TBI_ANLPAR 0xEC 87#define NGE_TBI_ANER 0xF0 88#define NGE_TBI_ESR 0xF4 89 90/* Control/status register */ 91#define NGE_CSR_TX_ENABLE 0x00000001 92#define NGE_CSR_TX_DISABLE 0x00000002 93#define NGE_CSR_RX_ENABLE 0x00000004 94#define NGE_CSR_RX_DISABLE 0x00000008 95#define NGE_CSR_TX_RESET 0x00000010 96#define NGE_CSR_RX_RESET 0x00000020 97#define NGE_CSR_SOFTINTR 0x00000080 98#define NGE_CSR_RESET 0x00000100 99#define NGE_CSR_TX_PRIOQ_ENB0 0x00000200 100#define NGE_CSR_TX_PRIOQ_ENB1 0x00000400 101#define NGE_CSR_TX_PRIOQ_ENB2 0x00000800 102#define NGE_CSR_TX_PRIOQ_ENB3 0x00001000 103#define NGE_CSR_RX_PRIOQ_ENB0 0x00002000 104#define NGE_CSR_RX_PRIOQ_ENB1 0x00004000 105#define NGE_CSR_RX_PRIOQ_ENB2 0x00008000 106#define NGE_CSR_RX_PRIOQ_ENB3 0x00010000 107 108/* Configuration register */ 109#define NGE_CFG_BIGENDIAN 0x00000001 110#define NGE_CFG_EXT_125MHZ 0x00000002 111#define NGE_CFG_BOOTROM_DIS 0x00000004 112#define NGE_CFG_PERR_DETECT 0x00000008 113#define NGE_CFG_DEFER_DISABLE 0x00000010 114#define NGE_CFG_OUTOFWIN_TIMER 0x00000020 115#define NGE_CFG_SINGLE_BACKOFF 0x00000040 116#define NGE_CFG_PCIREQ_ALG 0x00000080 117#define NGE_CFG_EXTSTS_ENB 0x00000100 118#define NGE_CFG_PHY_DIS 0x00000200 119#define NGE_CFG_PHY_RST 0x00000400 120#define NGE_CFG_64BIT_ADDR_ENB 0x00000800 121#define NGE_CFG_64BIT_DATA_ENB 0x00001000 122#define NGE_CFG_64BIT_PCI_DET 0x00002000 123#define NGE_CFG_64BIT_TARG 0x00004000 124#define NGE_CFG_MWI_DIS 0x00008000 125#define NGE_CFG_MRM_DIS 0x00010000 126#define NGE_CFG_TMRTST 0x00020000 127#define NGE_CFG_PHYINTR_SPD 0x00040000 128#define NGE_CFG_PHYINTR_LNK 0x00080000 129#define NGE_CFG_PHYINTR_DUP 0x00100000 130#define NGE_CFG_MODE_1000 0x00400000 131#define NGE_CFG_TBI_EN 0x01000000 132#define NGE_CFG_DUPLEX_STS 0x10000000 133#define NGE_CFG_SPEED_STS 0x60000000 134#define NGE_CFG_LINK_STS 0x80000000 135 136/* MII/EEPROM control register */ 137#define NGE_MEAR_EE_DIN 0x00000001 138#define NGE_MEAR_EE_DOUT 0x00000002 139#define NGE_MEAR_EE_CLK 0x00000004 140#define NGE_MEAR_EE_CSEL 0x00000008 141#define NGE_MEAR_MII_DATA 0x00000010 142#define NGE_MEAR_MII_DIR 0x00000020 143#define NGE_MEAR_MII_CLK 0x00000040 144 145#define NGE_EECMD_WRITE 0x140 146#define NGE_EECMD_READ 0x180 147#define NGE_EECMD_ERASE 0x1c0 148 149#define NGE_EE_NODEADDR 0xA 150 151/* PCI control register */ 152#define NGE_PCICTL_SRAMADDR 0x0000001F 153#define NGE_PCICTL_RAMTSTENB 0x00000020 154#define NGE_PCICTL_TXTSTENB 0x00000040 155#define NGE_PCICTL_RXTSTENB 0x00000080 156#define NGE_PCICTL_BMTSTENB 0x00000200 157#define NGE_PCICTL_RAMADDR 0x001F0000 158#define NGE_PCICTL_ROMTIME 0x0F000000 159#define NGE_PCICTL_DISCTEST 0x40000000 160 161/* Interrupt/status register */ 162#define NGE_ISR_RX_OK 0x00000001 163#define NGE_ISR_RX_DESC_OK 0x00000002 164#define NGE_ISR_RX_ERR 0x00000004 165#define NGE_ISR_RX_EARLY 0x00000008 166#define NGE_ISR_RX_IDLE 0x00000010 167#define NGE_ISR_RX_OFLOW 0x00000020 168#define NGE_ISR_TX_OK 0x00000040 169#define NGE_ISR_TX_DESC_OK 0x00000080 170#define NGE_ISR_TX_ERR 0x00000100 171#define NGE_ISR_TX_IDLE 0x00000200 172#define NGE_ISR_TX_UFLOW 0x00000400 173#define NGE_ISR_MIB_SERVICE 0x00000800 174#define NGE_ISR_SOFTINTR 0x00001000 175#define NGE_ISR_PME_EVENT 0x00002000 176#define NGE_ISR_PHY_INTR 0x00004000 177#define NGE_ISR_HIBITS 0x00008000 178#define NGE_ISR_RX_FIFO_OFLOW 0x00010000 179#define NGE_ISR_TGT_ABRT 0x00020000 180#define NGE_ISR_BM_ABRT 0x00040000 181#define NGE_ISR_SYSERR 0x00080000 182#define NGE_ISR_PARITY_ERR 0x00100000 183#define NGE_ISR_RX_RESET_DONE 0x00200000 184#define NGE_ISR_TX_RESET_DONE 0x00400000 185#define NGE_ISR_RX_PRIOQ_DESC0 0x00800000 186#define NGE_ISR_RX_PRIOQ_DESC1 0x01000000 187#define NGE_ISR_RX_PRIOQ_DESC2 0x02000000 188#define NGE_ISR_RX_PRIOQ_DESC3 0x04000000 189#define NGE_ISR_TX_PRIOQ_DESC0 0x08000000 190#define NGE_ISR_TX_PRIOQ_DESC1 0x10000000 191#define NGE_ISR_TX_PRIOQ_DESC2 0x20000000 192#define NGE_ISR_TX_PRIOQ_DESC3 0x40000000 193 194/* Interrupt mask register */ 195#define NGE_IMR_RX_OK 0x00000001 196#define NGE_IMR_RX_DESC_OK 0x00000002 197#define NGE_IMR_RX_ERR 0x00000004 198#define NGE_IMR_RX_EARLY 0x00000008 199#define NGE_IMR_RX_IDLE 0x00000010 200#define NGE_IMR_RX_OFLOW 0x00000020 201#define NGE_IMR_TX_OK 0x00000040 202#define NGE_IMR_TX_DESC_OK 0x00000080 203#define NGE_IMR_TX_ERR 0x00000100 204#define NGE_IMR_TX_IDLE 0x00000200 205#define NGE_IMR_TX_UFLOW 0x00000400 206#define NGE_IMR_MIB_SERVICE 0x00000800 207#define NGE_IMR_SOFTINTR 0x00001000 208#define NGE_IMR_PME_EVENT 0x00002000 209#define NGE_IMR_PHY_INTR 0x00004000 210#define NGE_IMR_HIBITS 0x00008000 211#define NGE_IMR_RX_FIFO_OFLOW 0x00010000 212#define NGE_IMR_TGT_ABRT 0x00020000 213#define NGE_IMR_BM_ABRT 0x00040000 214#define NGE_IMR_SYSERR 0x00080000 215#define NGE_IMR_PARITY_ERR 0x00100000 216#define NGE_IMR_RX_RESET_DONE 0x00200000 217#define NGE_IMR_TX_RESET_DONE 0x00400000 218#define NGE_IMR_RX_PRIOQ_DESC0 0x00800000 219#define NGE_IMR_RX_PRIOQ_DESC1 0x01000000 220#define NGE_IMR_RX_PRIOQ_DESC2 0x02000000 221#define NGE_IMR_RX_PRIOQ_DESC3 0x04000000 222#define NGE_IMR_TX_PRIOQ_DESC0 0x08000000 223#define NGE_IMR_TX_PRIOQ_DESC1 0x10000000 224#define NGE_IMR_TX_PRIOQ_DESC2 0x20000000 225#define NGE_IMR_TX_PRIOQ_DESC3 0x40000000 226 227#define NGE_INTRS \ 228 (NGE_IMR_RX_OFLOW|NGE_IMR_TX_UFLOW|NGE_IMR_TX_OK|\ 229 NGE_IMR_TX_IDLE|NGE_IMR_RX_OK|NGE_IMR_RX_ERR|\ 230 NGE_IMR_SYSERR|NGE_IMR_PHY_INTR|\ 231 NGE_IMR_RX_IDLE|NGE_IMR_RX_FIFO_OFLOW) 232 233/* Interrupt enable register */ 234#define NGE_IER_INTRENB 0x00000001 235 236/* Interrupt moderation timer register */ 237#define NGE_IHR_HOLDOFF 0x000000FF 238#define NGE_IHR_HOLDCTL 0x00000100 239 240/* Transmit configuration register */ 241#define NGE_TXCFG_DRAIN_THRESH 0x000000FF /* 32-byte units */ 242#define NGE_TXCFG_FILL_THRESH 0x0000FF00 /* 32-byte units */ 243#define NGE_1000MB_BURST_DIS 0x00080000 244#define NGE_TXCFG_DMABURST 0x00700000 245#define NGE_TXCFG_ECRETRY 0x00800000 246#define NGE_TXCFG_AUTOPAD 0x10000000 247#define NGE_TXCFG_LOOPBK 0x20000000 248#define NGE_TXCFG_IGN_HBEAT 0x40000000 249#define NGE_TXCFG_IGN_CARR 0x80000000 250 251#define NGE_TXCFG_DRAIN(x) (((x) >> 5) & NGE_TXCFG_DRAIN_THRESH) 252#define NGE_TXCFG_FILL(x) ((((x) >> 5) << 8) & NGE_TXCFG_FILL_THRESH) 253 254#define NGE_TXDMA_1024BYTES 0x00000000 255#define NGE_TXDMA_8BYTES 0x00100000 256#define NGE_TXDMA_16BYTES 0x00200000 257#define NGE_TXDMA_32BYTES 0x00300000 258#define NGE_TXDMA_64BYTES 0x00400000 259#define NGE_TXDMA_128BYTES 0x00500000 260#define NGE_TXDMA_256BYTES 0x00600000 261#define NGE_TXDMA_512BYTES 0x00700000 262 263#define NGE_TXCFG \ 264 (NGE_TXDMA_512BYTES|NGE_TXCFG_AUTOPAD|\ 265 NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(6400)) 266 267/* GPIO register */ 268#define NGE_GPIO_GP1_OUT 0x00000001 269#define NGE_GPIO_GP2_OUT 0x00000002 270#define NGE_GPIO_GP3_OUT 0x00000004 271#define NGE_GPIO_GP4_OUT 0x00000008 272#define NGE_GPIO_GP5_OUT 0x00000010 273#define NGE_GPIO_GP1_OUTENB 0x00000020 274#define NGE_GPIO_GP2_OUTENB 0x00000040 275#define NGE_GPIO_GP3_OUTENB 0x00000080 276#define NGE_GPIO_GP4_OUTENB 0x00000100 277#define NGE_GPIO_GP5_OUTENB 0x00000200 278#define NGE_GPIO_GP1_IN 0x00000400 279#define NGE_GPIO_GP2_IN 0x00000800 280#define NGE_GPIO_GP3_IN 0x00001000 281#define NGE_GPIO_GP4_IN 0x00002000 282#define NGE_GPIO_GP5_IN 0x00004000 283 284/* Receive configuration register */ 285#define NGE_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */ 286#define NGE_RXCFG_DMABURST 0x00700000 287#define NGE_RXCFG_RX_RANGEERR 0x04000000 /* accept in-range err frames */ 288#define NGE_RXCFG_RX_GIANTS 0x08000000 /* accept packets > 1518 bytes */ 289#define NGE_RXCFG_RX_FDX 0x10000000 /* full duplex receive */ 290#define NGE_RXCFG_RX_NOCRC 0x20000000 /* strip CRC */ 291#define NGE_RXCFG_RX_RUNT 0x40000000 /* accept short frames */ 292#define NGE_RXCFG_RX_BADPKTS 0x80000000 /* accept error frames */ 293 294#define NGE_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & NGE_RXCFG_DRAIN_THRESH) 295 296#define NGE_RXDMA_1024BYTES 0x00000000 297#define NGE_RXDMA_8BYTES 0x00100000 298#define NGE_RXDMA_16BYTES 0x00200000 299#define NGE_RXDMA_32YTES 0x00300000 300#define NGE_RXDMA_64BYTES 0x00400000 301#define NGE_RXDMA_128BYTES 0x00500000 302#define NGE_RXDMA_256BYTES 0x00600000 303#define NGE_RXDMA_512BYTES 0x00700000 304 305/* 306 * DP83820/DP83821 with H/W VLAN stripping does not accept short VLAN 307 * tagged packets such as ARP, short icmp echo request, etc. It seems 308 * that MAC checks frame length for VLAN tagged packets after stripping 309 * the VLAN tag. For short VLAN tagged packets it would would be 56 310 * (64 - CRC - VLAN info) bytes in length after stripping VLAN tag. 311 * If the VLAN tag stripped frames are less than 60 bytes in length 312 * the hardware think it received runt packets! 313 * Therefore we should accept runt frames to get VLAN tagged ARP 314 * packets. In addition, it is known that some revisions of 315 * DP83820/DP83821 have another bug that prevent fragmented IP packets 316 * from accepting. So we also should accept errored frames. 317 */ 318#define NGE_RXCFG \ 319 (NGE_RXCFG_DRAIN(64) | NGE_RXDMA_256BYTES| \ 320 NGE_RXCFG_RX_RANGEERR | NGE_RXCFG_RX_BADPKTS | NGE_RXCFG_RX_RUNT | \ 321 NGE_RXCFG_RX_GIANTS | NGE_RXCFG_RX_NOCRC) 322 323/* Priority queue control */ 324#define NGE_PRIOQCTL_TXPRIO_ENB 0x00000001 325#define NGE_PRIOQCTL_TXFAIR_ENB 0x00000002 326#define NGE_PRIOQCTL_RXPRIO 0x0000000C 327 328#define NGE_RXPRIOQ_DISABLED 0x00000000 329#define NGE_RXPRIOQ_TWOQS 0x00000004 330#define NGE_RXPRIOQ_THREEQS 0x00000008 331#define NGE_RXPRIOQ_FOURQS 0x0000000C 332 333/* Wake On LAN command/status register */ 334#define NGE_WOLCSR_WAKE_ON_PHYINTR 0x00000001 335#define NGE_WOLCSR_WAKE_ON_UNICAST 0x00000002 336#define NGE_WOLCSR_WAKE_ON_MULTICAST 0x00000004 337#define NGE_WOLCSR_WAKE_ON_BROADCAST 0x00000008 338#define NGE_WOLCSR_WAKE_ON_ARP 0x00000010 339#define NGE_WOLCSR_WAKE_ON_PAT0_MATCH 0x00000020 340#define NGE_WOLCSR_WAKE_ON_PAT1_MATCH 0x00000040 341#define NGE_WOLCSR_WAKE_ON_PAT2_MATCH 0x00000080 342#define NGE_WOLCSR_WAKE_ON_PAT3_MATCH 0x00000100 343#define NGE_WOLCSR_WAKE_ON_MAGICPKT 0x00000200 344#define NGE_WOLCSR_SECUREON_ENB 0x00000400 345#define NGE_WOLCSR_SECUREON_HACK 0x00200000 346#define NGE_WOLCSR_PHYINTR 0x00400000 347#define NGE_WOLCSR_UNICAST 0x00800000 348#define NGE_WOLCSR_MULTICAST 0x01000000 349#define NGE_WOLCSR_BROADCAST 0x02000000 350#define NGE_WOLCSR_ARP_RCVD 0x04000000 351#define NGE_WOLCSR_PAT0_MATCH 0x08000000 352#define NGE_WOLCSR_PAT1_MATCH 0x10000000 353#define NGE_WOLCSR_PAT2_MATCH 0x20000000 354#define NGE_WOLCSR_PAT3_MATCH 0x40000000 355#define NGE_WOLCSR_MAGICPKT 0x80000000 356 357/* Pause control/status register */ 358#define NGE_PAUSECSR_CNT 0x0000FFFF 359#define NGE_PAUSECSR_PFRAME_SENT 0x00020000 360#define NGE_PAUSECSR_RX_DATAFIFO_THR_LO 0x000C0000 361#define NGE_PAUSECSR_RX_DATAFIFO_THR_HI 0x00300000 362#define NGE_PAUSECSR_RX_STATFIFO_THR_LO 0x00C00000 363#define NGE_PAUSECSR_RX_STATFIFO_THR_HI 0x03000000 364#define NGE_PAUSECSR_PFRAME_RCVD 0x08000000 365#define NGE_PAUSECSR_PAUSE_ACTIVE 0x10000000 366#define NGE_PAUSECSR_PAUSE_ON_DA 0x20000000 /* pause on direct addr */ 367#define NGE_PAUSECSR_PAUSE_ON_MCAST 0x40000000 /* pause on mcast */ 368#define NGE_PAUSECSR_PAUSE_ENB 0x80000000 369 370/* Receive filter/match control message */ 371#define MGE_RXFILTCTL_ADDR 0x000003FF 372#define NGE_RXFILTCTL_ULMASK 0x00080000 373#define NGE_RXFILTCTL_UCHASH 0x00100000 374#define NGE_RXFILTCTL_MCHASH 0x00200000 375#define NGE_RXFILTCTL_ARP 0x00400000 376#define NGE_RXFILTCTL_PMATCH0 0x00800000 377#define NGE_RXFILTCTL_PMATCH1 0x01000000 378#define NGE_RXFILTCTL_PMATCH2 0x02000000 379#define NGE_RXFILTCTL_PMATCH3 0x04000000 380#define NGE_RXFILTCTL_PERFECT 0x08000000 381#define NGE_RXFILTCTL_ALLPHYS 0x10000000 382#define NGE_RXFILTCTL_ALLMULTI 0x20000000 383#define NGE_RXFILTCTL_BROAD 0x40000000 384#define NGE_RXFILTCTL_ENABLE 0x80000000 385 386 387#define NGE_FILTADDR_PAR0 0x00000000 388#define NGE_FILTADDR_PAR1 0x00000002 389#define NGE_FILTADDR_PAR2 0x00000004 390#define NGE_FILTADDR_PMATCH0 0x00000006 391#define NGE_FILTADDR_PMATCH1 0x00000008 392#define NGE_FILTADDR_SOPASS0 0x0000000A 393#define NGE_FILTADDR_SOPASS1 0x0000000C 394#define NGE_FILTADDR_SOPASS2 0x0000000E 395#define NGE_FILTADDR_FMEM_LO 0x00000100 396#define NGE_FILTADDR_FMEM_HI 0x000003FE 397#define NGE_FILTADDR_MCAST_LO 0x00000100 /* start of multicast filter */ 398#define NGE_FILTADDR_MCAST_HI 0x000001FE /* end of multicast filter */ 399#define NGE_MCAST_FILTER_LEN 256 /* bytes */ 400#define NGE_FILTADDR_PBUF0 0x00000200 /* pattern buffer 0 */ 401#define NGE_FILTADDR_PBUF1 0x00000280 /* pattern buffer 1 */ 402#define NGE_FILTADDR_PBUF2 0x00000300 /* pattern buffer 2 */ 403#define NGE_FILTADDR_PBUF3 0x00000380 /* pattern buffer 3 */ 404 405/* MIB control register */ 406#define NGE_MIBCTL_WARNTEST 0x00000001 407#define NGE_MIBCTL_FREEZE_CNT 0x00000002 408#define NGE_MIBCTL_CLEAR_CNT 0x00000004 409#define NGE_MIBCTL_STROBE_CNT 0x00000008 410 411/* VLAN/IP RX control register */ 412#define NGE_VIPRXCTL_TAG_DETECT_ENB 0x00000001 413#define NGE_VIPRXCTL_TAG_STRIP_ENB 0x00000002 414#define NGE_VIPRXCTL_DROP_TAGGEDPKTS 0x00000004 415#define NGE_VIPRXCTL_DROP_UNTAGGEDPKTS 0x00000008 416#define NGE_VIPRXCTL_IPCSUM_ENB 0x00000010 417#define NGE_VIPRXCTL_REJECT_BADIPCSUM 0x00000020 418#define NGE_VIPRXCTL_REJECT_BADTCPCSUM 0x00000040 419#define NGE_VIPRXCTL_REJECT_BADUDPCSUM 0x00000080 420 421/* VLAN/IP TX control register */ 422#define NGE_VIPTXCTL_TAG_ALL 0x00000001 423#define NGE_VIPTXCTL_TAG_PER_PKT 0x00000002 424#define NGE_VIPTXCTL_CSUM_ALL 0x00000004 425#define NGE_VIPTXCTL_CSUM_PER_PKT 0x00000008 426 427/* VLAN data register */ 428#define NGE_VLANDATA_VTYPE 0x0000FFFF 429#define NGE_VLANDATA_VTCI 0xFFFF0000 430 431/* Clockrun register */ 432#define NGE_CLKRUN_PMESTS 0x00008000 433#define NGE_CLKRUN_PMEENB 0x00000100 434#define NGE_CLNRUN_CLKRUN_ENB 0x00000001 435 436 437/* TBI BMCR */ 438#define NGE_TBIBMCR_RESTART_ANEG 0x00000200 439#define NGE_TBIBMCR_ENABLE_ANEG 0x00001000 440#define NGE_TBIBMCR_LOOPBACK 0x00004000 441 442/* TBI BMSR */ 443#define NGE_TBIBMSR_ANEG_DONE 0x00000004 444#define NGE_TBIBMSR_LINKSTAT 0x00000020 445 446/* TBI ANAR */ 447#define NGE_TBIANAR_HDX 0x00000020 448#define NGE_TBIANAR_FDX 0x00000040 449#define NGE_TBIANAR_PS1 0x00000080 450#define NGE_TBIANAR_PS2 0x00000100 451#define NGE_TBIANAR_PCAP 0x00000180 452#define NGE_TBIANAR_REMFAULT 0x00003000 453#define NGE_TBIANAR_NEXTPAGE 0x00008000 454 455/* TBI ANLPAR */ 456#define NGE_TBIANLPAR_HDX 0x00000020 457#define NGE_TBIANLPAR_FDX 0x00000040 458#define NGE_TBIANAR_PS1 0x00000080 459#define NGE_TBIANAR_PS2 0x00000100 460#define NGE_TBIANLPAR_PCAP 0x00000180 461#define NGE_TBIANLPAR_REMFAULT 0x00003000 462#define NGE_TBIANLPAR_NEXTPAGE 0x00008000 463 464/* TBI ANER */ 465#define NGE_TBIANER_PAGERCVD 0x00000002 466#define NGE_TBIANER_NEXTPGABLE 0x00000004 467 468/* TBI EXTSTS */ 469#define NGE_TBIEXTSTS_HXD 0x00004000 470#define NGE_TBIEXTSTS_FXD 0x00008000 471 472/* 473 * DMA descriptor structures. The RX and TX descriptor formats are 474 * deliberately designed to be similar to facilitate passing them between 475 * RX and TX queues on multiple controllers, in the case where you have 476 * multiple MACs in a switching configuration. With the 83820, the pointer 477 * values can be either 64 bits or 32 bits depending on how the chip is 478 * configured. For the 83821, the fields are always 32-bits. There is 479 * also an optional extended status field for VLAN and TCP/IP checksum 480 * functions. We use the checksum feature so we enable the use of this 481 * field. Descriptors must be 64-bit aligned. 482 */ 483struct nge_desc_64 { 484 /* Hardware descriptor section */ 485 uint32_t nge_next_lo; 486 uint32_t nge_next_hi; 487 uint32_t nge_ptr_lo; 488 uint32_t nge_ptr_hi; 489 uint32_t nge_cmdsts; 490 uint32_t nge_extsts; 491}; 492 493struct nge_desc_32 { 494 /* Hardware descriptor section */ 495 uint32_t nge_next; 496 uint32_t nge_ptr; 497 uint32_t nge_cmdsts; 498 uint32_t nge_extsts; 499}; 500 501#define nge_desc nge_desc_32 502 503#define NGE_CMDSTS_BUFLEN 0x0000FFFF 504#define NGE_CMDSTS_PKT_OK 0x08000000 505#define NGE_CMDSTS_CRC 0x10000000 506#define NGE_CMDSTS_INTR 0x20000000 507#define NGE_CMDSTS_MORE 0x40000000 508#define NGE_CMDSTS_OWN 0x80000000 509 510#define NGE_INC(x, y) (x) = ((x) + 1) % y 511 512#define NGE_RXSTAT_RANGELENERR 0x00010000 513#define NGE_RXSTAT_LOOPBK 0x00020000 514#define NGE_RXSTAT_ALIGNERR 0x00040000 515#define NGE_RXSTAT_CRCERR 0x00080000 516#define NGE_RXSTAT_SYMBOLERR 0x00100000 517#define NGE_RXSTAT_RUNT 0x00200000 518#define NGE_RXSTAT_GIANT 0x00400000 519#define NGE_RXSTAT_DSTCLASS 0x01800000 520#define NGE_RXSTAT_OVERRUN 0x02000000 521#define NGE_RXSTAT_RX_ABORT 0x04000000 522 523#define NGE_DSTCLASS_REJECT 0x00000000 524#define NGE_DSTCLASS_UNICAST 0x00800000 525#define NGE_DSTCLASS_MULTICAST 0x01000000 526#define NGE_DSTCLASS_BROADCAST 0x02000000 527 528#define NGE_TXSTAT_COLLCNT 0x000F0000 529#define NGE_TXSTAT_EXCESSCOLLS 0x00100000 530#define NGE_TXSTAT_OUTOFWINCOLL 0x00200000 531#define NGE_TXSTAT_EXCESS_DEFER 0x00400000 532#define NGE_TXSTAT_DEFERED 0x00800000 533#define NGE_TXSTAT_CARR_LOST 0x01000000 534#define NGE_TXSTAT_UNDERRUN 0x02000000 535#define NGE_TXSTAT_TX_ABORT 0x04000000 536 537#define NGE_TXEXTSTS_VLAN_TCI 0x0000FFFF 538#define NGE_TXEXTSTS_VLANPKT 0x00010000 539#define NGE_TXEXTSTS_IPCSUM 0x00020000 540#define NGE_TXEXTSTS_TCPCSUM 0x00080000 541#define NGE_TXEXTSTS_UDPCSUM 0x00200000 542 543#define NGE_RXEXTSTS_VTCI 0x0000FFFF 544#define NGE_RXEXTSTS_VLANPKT 0x00010000 545#define NGE_RXEXTSTS_IPPKT 0x00020000 546#define NGE_RXEXTSTS_IPCSUMERR 0x00040000 547#define NGE_RXEXTSTS_TCPPKT 0x00080000 548#define NGE_RXEXTSTS_TCPCSUMERR 0x00100000 549#define NGE_RXEXTSTS_UDPPKT 0x00200000 550#define NGE_RXEXTSTS_UDPCSUMERR 0x00400000 551 552#define NGE_TX_RING_CNT 256 553#define NGE_RX_RING_CNT 256 554#define NGE_TX_RING_SIZE sizeof(struct nge_desc) * NGE_TX_RING_CNT 555#define NGE_RX_RING_SIZE sizeof(struct nge_desc) * NGE_RX_RING_CNT 556#define NGE_RING_ALIGN sizeof(uint64_t) 557#define NGE_RX_ALIGN sizeof(uint64_t) 558#define NGE_MAXTXSEGS 16 559 560#define NGE_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 561#define NGE_ADDR_HI(x) ((uint64_t)(x) >> 32) 562#define NGE_TX_RING_ADDR(sc, i) \ 563 ((sc)->nge_rdata.nge_tx_ring_paddr + sizeof(struct nge_desc) * (i)) 564#define NGE_RX_RING_ADDR(sc, i) \ 565 ((sc)->nge_rdata.nge_rx_ring_paddr + sizeof(struct nge_desc) * (i)) 566 567struct nge_txdesc { 568 struct mbuf *tx_m; 569 bus_dmamap_t tx_dmamap; 570}; 571 572struct nge_rxdesc { 573 struct mbuf *rx_m; 574 bus_dmamap_t rx_dmamap; 575}; 576 577struct nge_chain_data { 578 bus_dma_tag_t nge_parent_tag; 579 bus_dma_tag_t nge_tx_tag; 580 struct nge_txdesc nge_txdesc[NGE_TX_RING_CNT]; 581 bus_dma_tag_t nge_rx_tag; 582 struct nge_rxdesc nge_rxdesc[NGE_RX_RING_CNT]; 583 bus_dma_tag_t nge_tx_ring_tag; 584 bus_dma_tag_t nge_rx_ring_tag; 585 bus_dmamap_t nge_tx_ring_map; 586 bus_dmamap_t nge_rx_ring_map; 587 bus_dmamap_t nge_rx_sparemap; 588 int nge_tx_prod; 589 int nge_tx_cons; 590 int nge_tx_cnt; 591 int nge_rx_cons; 592}; 593 594struct nge_ring_data { 595 struct nge_desc *nge_tx_ring; 596 bus_addr_t nge_tx_ring_paddr; 597 struct nge_desc *nge_rx_ring; 598 bus_addr_t nge_rx_ring_paddr; 599}; 600 601/* 602 * NatSemi PCI vendor ID. 603 */ 604#define NGE_VENDORID 0x100B 605 606/* 607 * 83820/83821 PCI device IDs 608 */ 609#define NGE_DEVICEID 0x0022 610 611struct nge_type { 612 uint16_t nge_vid; 613 uint16_t nge_did; 614 const char *nge_name; 615}; 616 617#define NGE_JUMBO_FRAMELEN 9022 618#define NGE_JUMBO_MTU \ 619 (NGE_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) 620 621/* Statistics counters. */ 622struct nge_stats { 623 uint32_t rx_pkts_errs; 624 uint32_t rx_crc_errs; 625 uint32_t rx_fifo_oflows; 626 uint32_t rx_align_errs; 627 uint32_t rx_sym_errs; 628 uint32_t rx_pkts_jumbos; 629 uint32_t rx_len_errs; 630 uint32_t rx_unctl_frames; 631 uint32_t rx_pause; 632 uint32_t tx_pause; 633 uint32_t tx_seq_errs; 634}; 635 636struct nge_softc { 637 struct ifnet *nge_ifp; 638 device_t nge_dev; 639 struct resource *nge_res; 640 int nge_res_type; 641 int nge_res_id; 642 struct resource *nge_irq; 643 void *nge_intrhand; 644 device_t nge_miibus; 645 int nge_if_flags; 646 uint32_t nge_flags; 647#define NGE_FLAG_TBI 0x0002 648#define NGE_FLAG_SUSPENDED 0x2000 649#define NGE_FLAG_DETACH 0x4000 650#define NGE_FLAG_LINK 0x8000 651 struct nge_chain_data nge_cdata; 652 struct nge_ring_data nge_rdata; 653 struct callout nge_stat_ch; 654 struct nge_stats nge_stats; 655 struct mtx nge_mtx; 656#ifdef DEVICE_POLLING 657 int rxcycles; 658#endif 659 int nge_watchdog_timer; 660 int nge_int_holdoff; 661 struct mbuf *nge_head; 662 struct mbuf *nge_tail; 663}; 664 665#define NGE_LOCK_INIT(_sc, _name) \ 666 mtx_init(&(_sc)->nge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 667#define NGE_LOCK(_sc) mtx_lock(&(_sc)->nge_mtx) 668#define NGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nge_mtx, MA_OWNED) 669#define NGE_UNLOCK(_sc) mtx_unlock(&(_sc)->nge_mtx) 670#define NGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->nge_mtx) 671 672/* 673 * register space access macros 674 */ 675#define CSR_WRITE_4(sc, reg, val) \ 676 bus_write_4((sc)->nge_res, reg, val) 677 678#define CSR_BARRIER_4(sc, reg, flags) \ 679 bus_barrier((sc)->nge_res, reg, 4, flags) 680 681#define CSR_READ_4(sc, reg) \ 682 bus_read_4((sc)->nge_res, reg) 683 684#define NGE_TIMEOUT 1000 685 686#define NGE_INT_HOLDOFF_DEFAULT 1 687#define NGE_INT_HOLDOFF_MIN 0 688#define NGE_INT_HOLDOFF_MAX 255 689 690/* 691 * PCI low memory base and low I/O base register, and 692 * other PCI registers. 693 */ 694 695#define NGE_PCI_VENDOR_ID 0x00 696#define NGE_PCI_DEVICE_ID 0x02 697#define NGE_PCI_COMMAND 0x04 698#define NGE_PCI_STATUS 0x06 699#define NGE_PCI_REVID 0x08 700#define NGE_PCI_CLASSCODE 0x09 701#define NGE_PCI_CACHELEN 0x0C 702#define NGE_PCI_LATENCY_TIMER 0x0D 703#define NGE_PCI_HEADER_TYPE 0x0E 704#define NGE_PCI_LOIO 0x10 705#define NGE_PCI_LOMEM 0x14 706#define NGE_PCI_BIOSROM 0x30 707#define NGE_PCI_INTLINE 0x3C 708#define NGE_PCI_INTPIN 0x3D 709#define NGE_PCI_MINGNT 0x3E 710#define NGE_PCI_MINLAT 0x0F 711#define NGE_PCI_RESETOPT 0x48 712#define NGE_PCI_EEPROM_DATA 0x4C 713 714/* power management registers */ 715#define NGE_PCI_CAPID 0x50 /* 8 bits */ 716#define NGE_PCI_NEXTPTR 0x51 /* 8 bits */ 717#define NGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 718#define NGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 719 720#define NGE_PSTATE_MASK 0x0003 721#define NGE_PSTATE_D0 0x0000 722#define NGE_PSTATE_D1 0x0001 723#define NGE_PSTATE_D2 0x0002 724#define NGE_PSTATE_D3 0x0003 725#define NGE_PME_EN 0x0010 726#define NGE_PME_STATUS 0x8000 727