ns16550.h revision 128019
11844Swollman/*- 250476Speter * Copyright (c) 1991 The Regents of the University of California. 323549Swosch * All rights reserved. 423549Swosch * 535784Swosch * Redistribution and use in source and binary forms, with or without 623549Swosch * modification, are permitted provided that the following conditions 723549Swosch * are met: 823549Swosch * 1. Redistributions of source code must retain the above copyright 923549Swosch * notice, this list of conditions and the following disclaimer. 1023549Swosch * 2. Redistributions in binary form must reproduce the above copyright 1123549Swosch * notice, this list of conditions and the following disclaimer in the 1223549Swosch * documentation and/or other materials provided with the distribution. 1323549Swosch * 4. Neither the name of the University nor the names of its contributors 1423549Swosch * may be used to endorse or promote products derived from this software 1523549Swosch * without specific prior written permission. 1623549Swosch * 1723549Swosch * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 1823549Swosch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1923549Swosch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2023549Swosch * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2123549Swosch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2223549Swosch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2323549Swosch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2423549Swosch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2523549Swosch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2623549Swosch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2774842Sru * SUCH DAMAGE. 2823549Swosch * 2944922Sbde * from: @(#)ns16550.h 7.1 (Berkeley) 5/9/91 3023549Swosch * $FreeBSD: head/sys/dev/ic/ns16550.h 128019 2004-04-07 20:46:16Z imp $ 311638Srgrimes */ 3294940Sru 3323549Swosch/* 341638Srgrimes * NS8250... UART registers. 3590311Sru */ 3690311Sru 3790311Sru/* 8250 registers #[0-6]. */ 3890311Sru 3990311Sru#define com_data 0 /* data register (R/W) */ 4090311Sru#define com_thr com_data /* transmitter holding register (W) */ 4190311Sru#define com_rhr com_data /* receiver holding register (R) */ 4290311Sru 4390311Sru#define com_ier 1 /* interrupt enable register (W) */ 4490311Sru#define IER_ERXRDY 0x1 4590311Sru#define IER_ETXRDY 0x2 4690311Sru#define IER_ERLS 0x4 471638Srgrimes#define IER_EMSC 0x8 481638Srgrimes 491638Srgrimes#define com_iir 2 /* interrupt identification register (R) */ 5053152Smarcel#define com_isr com_iir /* interrupt status register (R) */ 5153152Smarcel#define IIR_IMASK 0xf 521638Srgrimes#define IIR_RXTOUT 0xc 531638Srgrimes#define IIR_RLS 0x6 541638Srgrimes#define IIR_RXRDY 0x4 551638Srgrimes#define IIR_TXRDY 0x2 561638Srgrimes#define IIR_NOPEND 0x1 571638Srgrimes#define IIR_MLSC 0x0 5874842Sru#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 5985570Sdes 6085570Sdes#define com_lcr 3 /* line control register (R/W) */ 6131177Swosch#define com_lctl com_lcr 6215061Swosch#define com_cfcr com_lcr /* character format control register (R/W) */ 631638Srgrimes#define LCR_DLAB 0x80 6415061Swosch#define CFCR_DLAB LCR_DLAB 651638Srgrimes#define LCR_EFR_ENABLE 0xbf /* magic to enable EFR on 16650 up */ 661638Srgrimes#define CFCR_EFR_ENABLE LCR_EFR_ENABLE 671638Srgrimes#define CFCR_SBREAK 0x40 681638Srgrimes#define CFCR_PZERO 0x30 691638Srgrimes#define CFCR_PONE 0x20 701638Srgrimes#define CFCR_PEVEN 0x10 711638Srgrimes#define CFCR_PODD 0x00 721638Srgrimes#define CFCR_PENAB 0x08 731638Srgrimes#define CFCR_STOPB 0x04 741638Srgrimes#define CFCR_8BITS 0x03 751638Srgrimes#define CFCR_7BITS 0x02 761638Srgrimes#define CFCR_6BITS 0x01 771638Srgrimes#define CFCR_5BITS 0x00 7815061Swosch 7915061Swosch#define com_mcr 4 /* modem control register (R/W) */ 8015061Swosch#define MCR_PRESCALE 0x80 /* only available on 16650 up */ 811638Srgrimes#define MCR_LOOPBACK 0x10 8215061Swosch#define MCR_IENABLE 0x08 8323549Swosch#define MCR_DRS 0x04 8426760Sjkh#define MCR_RTS 0x02 8526760Sjkh#define MCR_DTR 0x01 8626760Sjkh 871638Srgrimes#define com_lsr 5 /* line status register (R/W) */ 88#define LSR_RCV_FIFO 0x80 89#define LSR_TSRE 0x40 90#define LSR_TXRDY 0x20 91#define LSR_BI 0x10 92#define LSR_FE 0x08 93#define LSR_PE 0x04 94#define LSR_OE 0x02 95#define LSR_RXRDY 0x01 96#define LSR_RCV_MASK 0x1f 97 98#define com_msr 6 /* modem status register (R/W) */ 99#define MSR_DCD 0x80 100#define MSR_RI 0x40 101#define MSR_DSR 0x20 102#define MSR_CTS 0x10 103#define MSR_DDCD 0x08 104#define MSR_TERI 0x04 105#define MSR_DDSR 0x02 106#define MSR_DCTS 0x01 107 108/* 8250 multiplexed registers #[0-1]. Access enabled by LCR[7]. */ 109#define com_dll 0 /* divisor latch low (R/W) */ 110#define com_dlbl com_dll 111#define com_dlm 1 /* divisor latch high (R/W) */ 112#define com_dlbh com_dlm 113 114/* 16450 register #7. Not multiplexed. */ 115#define com_scr 7 /* scratch register (R/W) */ 116 117/* 16550 register #2. Not multiplexed. */ 118#define com_fcr 2 /* FIFO control register (W) */ 119#define com_fifo com_fcr 120#define FIFO_ENABLE 0x01 121#define FIFO_RCV_RST 0x02 122#define FIFO_XMT_RST 0x04 123#define FIFO_DMA_MODE 0x08 124#define FIFO_RX_LOW 0x00 125#define FIFO_RX_MEDL 0x40 126#define FIFO_RX_MEDH 0x80 127#define FIFO_RX_HIGH 0xc0 128 129/* 16650 registers #2,[4-7]. Access enabled by LCR_EFR_ENABLE. */ 130 131#define com_efr 2 /* enhanced features register (R/W) */ 132#define EFR_AUTOCTS 0x80 133#define EFR_AUTORTS 0x40 134#define EFR_EFE 0x10 /* enhanced functions enable */ 135 136#define com_xon1 4 /* XON 1 character (R/W) */ 137#define com_xon2 5 /* XON 2 character (R/W) */ 138#define com_xoff1 6 /* XOFF 1 character (R/W) */ 139#define com_xoff2 7 /* XOFF 2 character (R/W) */ 140 141/* 16950 register #1. Access enabled by ACR[7]. Also requires !LCR[7]. */ 142#define com_asr 1 /* additional status register (R[0-7]/W[0-1]) */ 143 144/* 16950 register #3. R/W access enabled by ACR[7]. */ 145#define com_rfl 3 /* receiver fifo level (R) */ 146 147/* 148 * 16950 register #4. Access enabled by ACR[7]. Also requires 149 * !LCR_EFR_ENABLE. 150 */ 151#define com_tfl 4 /* transmitter fifo level (R) */ 152 153/* 154 * 16950 register #5. Accessible if !LCR_EFR_ENABLE. Read access also 155 * requires ACR[6]. 156 */ 157#define com_icr 5 /* index control register (R/W) */ 158 159/* 160 * 16950 register #7. It is the same as com_scr except it has a different 161 * abbreviation in the manufacturer's data sheet and it also serves as an 162 * index into the Indexed Control register set. 163 */ 164#define com_spr com_scr /* scratch pad (and index) register (R/W) */ 165 166/* 167 * 16950 indexed control registers #[0-0x13]. Access is via index in SPR, 168 * data in ICR (if ICR is accessible). 169 */ 170 171#define com_acr 0 /* additional control register (R/W) */ 172#define ACR_ASE 0x80 /* ASR/RFL/TFL enable */ 173#define ACR_ICRE 0x40 /* ICR enable */ 174#define ACR_TLE 0x20 /* TTL/RTL enable */ 175 176#define com_cpr 1 /* clock prescaler register (R/W) */ 177#define com_tcr 2 /* times clock register (R/W) */ 178#define com_ttl 4 /* transmitter trigger level (R/W) */ 179#define com_rtl 5 /* receiver trigger level (R/W) */ 180/* ... */ 181 182#ifdef PC98 183/* Hardware extension mode register for RSB-2000/3000. */ 184#define com_emr com_msr 185#define EMR_EXBUFF 0x04 186#define EMR_CTSFLW 0x08 187#define EMR_DSRFLW 0x10 188#define EMR_RTSFLW 0x20 189#define EMR_DTRFLW 0x40 190#define EMR_EFMODE 0x80 191#endif 192