1/*- 2 * Copyright (c) 2005, M. Warner Losh 3 * Copyright (c) 1995, David Greenman 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31/* 32 * Notes for adding media support. Each chipset is somewhat different 33 * from the others. Linux has a table of OIDs that it uses to see what 34 * supports the misc register of the NS83903. But a sampling of datasheets 35 * I could dig up on cards I own paints a different picture. 36 * 37 * Chipset specific details: 38 * NS 83903/902A paired 39 * ccr base 0x1020 40 * id register at 0x1000: 7-3 = 0, 2-0 = 1. 41 * (maybe this test is too week) 42 * misc register at 0x018: 43 * 6 WAIT_TOUTENABLE enable watchdog timeout 44 * 3 AUI/TPI 1 AUX, 0 TPI 45 * 2 loopback 46 * 1 gdlink (tpi mode only) 1 tp good, 0 tp bad 47 * 0 0-no mam, 1 mam connected 48 * 49 * NS83926 appears to be a NS pcmcia glue chip used on the IBM Ethernet II 50 * and the NEC PC9801N-J12 ccr base 0x2000! 51 * 52 * winbond 289c926 53 * ccr base 0xfd0 54 * cfb (am 0xff2): 55 * 0-1 PHY01 00 TPI, 01 10B2, 10 10B5, 11 TPI (reduced squ) 56 * 2 LNKEN 0 - enable link and auto switch, 1 disable 57 * 3 LNKSTS TPI + LNKEN=0 + link good == 1, else 0 58 * sr (am 0xff4) 59 * 88 00 88 00 88 00, etc 60 * 61 * TMI tc3299a (cr PHY01 == 0) 62 * ccr base 0x3f8 63 * cra (io 0xa) 64 * crb (io 0xb) 65 * 0-1 PHY01 00 auto, 01 res, 10 10B5, 11 TPI 66 * 2 GDLINK 1 disable checking of link 67 * 6 LINK 0 bad link, 1 good link 68 * 69 * EN5017A, EN5020 no data, but very popular 70 * Other chips? 71 * NetBSD supports RTL8019, but none have surfaced that I can see 72 */ 73 74#include <sys/param.h> 75#include <sys/systm.h> 76#include <sys/socket.h> 77#include <sys/kernel.h> 78#include <sys/module.h> 79#include <sys/bus.h> 80#include <machine/bus.h> 81#include <sys/rman.h> 82#include <machine/resource.h> 83 84#include <net/ethernet.h> 85#include <net/if.h> 86#include <net/if_arp.h> 87#include <net/if_mib.h> 88#include <net/if_media.h> 89 90#include <dev/ed/if_edreg.h> 91#include <dev/ed/if_edvar.h> 92#include <dev/ed/ax88x90reg.h> 93#include <dev/ed/dl100xxreg.h> 94#include <dev/ed/tc5299jreg.h> 95#include <dev/pccard/pccardvar.h> 96#include <dev/pccard/pccardreg.h> 97#include <dev/pccard/pccard_cis.h> 98#include <dev/mii/mii.h> 99#include <dev/mii/miivar.h> 100 101#include "card_if.h" 102/* "device miibus" required. See GENERIC if you get errors here. */ 103#include "miibus_if.h" 104#include "pccarddevs.h" 105 106/* 107 * NE-2000 based PC Cards have a number of ways to get the MAC address. 108 * Some cards encode this as a FUNCE. Others have this in the ROMs the 109 * same way that ISA cards do. Some have it encoded in the attribute 110 * memory somewhere that isn't in the CIS. Some new chipsets have it 111 * in special registers in the ASIC part of the chip. 112 * 113 * For those cards that have the MAC adress stored in attribute memory 114 * outside of a FUNCE entry in the CIS, nearly all of them have it at 115 * a fixed offset (0xff0). We use that offset as a source of last 116 * resource if other offsets have failed. This is the address of the 117 * National Semiconductor DP83903A, which is the only chip's datasheet 118 * I've found. 119 */ 120#define ED_DEFAULT_MAC_OFFSET 0xff0 121 122static const struct ed_product { 123 struct pccard_product prod; 124 int flags; 125#define NE2000DVF_DL100XX 0x0001 /* chip is D-Link DL10019/22 */ 126#define NE2000DVF_AX88X90 0x0002 /* chip is ASIX AX88[17]90 */ 127#define NE2000DVF_TC5299J 0x0004 /* chip is Tamarack TC5299J */ 128#define NE2000DVF_TOSHIBA 0x0008 /* Toshiba DP83902A */ 129#define NE2000DVF_ENADDR 0x0100 /* Get MAC from attr mem */ 130#define NE2000DVF_ANYFUNC 0x0200 /* Allow any function type */ 131#define NE2000DVF_MODEM 0x0400 /* Has a modem/serial */ 132 int enoff; 133} ed_pccard_products[] = { 134 { PCMCIA_CARD(ACCTON, EN2212), 0}, 135 { PCMCIA_CARD(ACCTON, EN2216), 0}, 136 { PCMCIA_CARD(ALLIEDTELESIS, LA_PCM), 0}, 137 { PCMCIA_CARD(AMBICOM, AMB8002), 0}, 138 { PCMCIA_CARD(AMBICOM, AMB8002T), 0}, 139 { PCMCIA_CARD(AMBICOM, AMB8010), 0}, 140 { PCMCIA_CARD(AMBICOM, AMB8010_ALT), 0}, 141 { PCMCIA_CARD(AMBICOM, AMB8610), 0}, 142 { PCMCIA_CARD(BILLIONTON, CFLT10N), 0}, 143 { PCMCIA_CARD(BILLIONTON, LNA100B), NE2000DVF_AX88X90}, 144 { PCMCIA_CARD(BILLIONTON, LNT10TB), 0}, 145 { PCMCIA_CARD(BILLIONTON, LNT10TN), 0}, 146 { PCMCIA_CARD(BROMAX, AXNET), NE2000DVF_AX88X90}, 147 { PCMCIA_CARD(BROMAX, IPORT), 0}, 148 { PCMCIA_CARD(BROMAX, IPORT2), 0}, 149 { PCMCIA_CARD(BUFFALO, LPC2_CLT), 0}, 150 { PCMCIA_CARD(BUFFALO, LPC3_CLT), 0}, 151 { PCMCIA_CARD(BUFFALO, LPC3_CLX), NE2000DVF_AX88X90}, 152 { PCMCIA_CARD(BUFFALO, LPC4_TX), NE2000DVF_AX88X90}, 153 { PCMCIA_CARD(BUFFALO, LPC4_CLX), NE2000DVF_AX88X90}, 154 { PCMCIA_CARD(BUFFALO, LPC_CF_CLT), 0}, 155 { PCMCIA_CARD(CNET, NE2000), 0}, 156 { PCMCIA_CARD(COMPEX, AX88190), NE2000DVF_AX88X90}, 157 { PCMCIA_CARD(COMPEX, LANMODEM), 0}, 158 { PCMCIA_CARD(COMPEX, LINKPORT_ENET_B), 0}, 159 { PCMCIA_CARD(COREGA, ETHER_II_PCC_T), 0}, 160 { PCMCIA_CARD(COREGA, ETHER_II_PCC_TD), 0}, 161 { PCMCIA_CARD(COREGA, ETHER_PCC_T), 0}, 162 { PCMCIA_CARD(COREGA, ETHER_PCC_TD), 0}, 163 { PCMCIA_CARD(COREGA, FAST_ETHER_PCC_TX), NE2000DVF_DL100XX}, 164 { PCMCIA_CARD(COREGA, FETHER_PCC_TXD), NE2000DVF_AX88X90}, 165 { PCMCIA_CARD(COREGA, FETHER_PCC_TXF), NE2000DVF_DL100XX}, 166 { PCMCIA_CARD(COREGA, FETHER_II_PCC_TXD), NE2000DVF_AX88X90}, 167 { PCMCIA_CARD(COREGA, LAPCCTXD), 0}, 168 { PCMCIA_CARD(DAYNA, COMMUNICARD_E_1), 0}, 169 { PCMCIA_CARD(DAYNA, COMMUNICARD_E_2), 0}, 170 { PCMCIA_CARD(DLINK, DE650), NE2000DVF_ANYFUNC }, 171 { PCMCIA_CARD(DLINK, DE660), 0 }, 172 { PCMCIA_CARD(DLINK, DE660PLUS), 0}, 173 { PCMCIA_CARD(DYNALINK, L10C), 0}, 174 { PCMCIA_CARD(EDIMAX, EP4000A), 0}, 175 { PCMCIA_CARD(EPSON, EEN10B), 0}, 176 { PCMCIA_CARD(EXP, THINLANCOMBO), 0}, 177 { PCMCIA_CARD(GLOBALVILLAGE, LANMODEM), 0}, 178 { PCMCIA_CARD(GREY_CELL, TDK3000), 0}, 179 { PCMCIA_CARD(GREY_CELL, DMF650TX), 180 NE2000DVF_ANYFUNC | NE2000DVF_DL100XX | NE2000DVF_MODEM}, 181 { PCMCIA_CARD(GVC, NIC_2000P), 0}, 182 { PCMCIA_CARD(IBM, HOME_AND_AWAY), 0}, 183 { PCMCIA_CARD(IBM, INFOMOVER), 0}, 184 { PCMCIA_CARD(IODATA3, PCLAT), 0}, 185 { PCMCIA_CARD(KINGSTON, CIO10T), 0}, 186 { PCMCIA_CARD(KINGSTON, KNE2), 0}, 187 { PCMCIA_CARD(LANTECH, FASTNETTX), NE2000DVF_AX88X90}, 188 /* Same ID for many different cards, including generic NE2000 */ 189 { PCMCIA_CARD(LINKSYS, COMBO_ECARD), 190 NE2000DVF_DL100XX | NE2000DVF_AX88X90}, 191 { PCMCIA_CARD(LINKSYS, ECARD_1), 0}, 192 { PCMCIA_CARD(LINKSYS, ECARD_2), 0}, 193 { PCMCIA_CARD(LINKSYS, ETHERFAST), NE2000DVF_DL100XX}, 194 { PCMCIA_CARD(LINKSYS, TRUST_COMBO_ECARD), 0}, 195 { PCMCIA_CARD(MACNICA, ME1_JEIDA), 0}, 196 { PCMCIA_CARD(MAGICRAM, ETHER), 0}, 197 { PCMCIA_CARD(MELCO, LPC3_CLX), NE2000DVF_AX88X90}, 198 { PCMCIA_CARD(MELCO, LPC3_TX), NE2000DVF_AX88X90}, 199 { PCMCIA_CARD(MELCO2, LPC2_T), 0}, 200 { PCMCIA_CARD(MELCO2, LPC2_TX), 0}, 201 { PCMCIA_CARD(MITSUBISHI, B8895), NE2000DVF_ANYFUNC}, /* NG */ 202 { PCMCIA_CARD(MICRORESEARCH, MR10TPC), 0}, 203 { PCMCIA_CARD(NDC, ND5100_E), 0}, 204 { PCMCIA_CARD(NETGEAR, FA410TXC), NE2000DVF_DL100XX}, 205 /* Same ID as DLINK DFE-670TXD. 670 has DL10022, fa411 has ax88790 */ 206 { PCMCIA_CARD(NETGEAR, FA411), NE2000DVF_AX88X90 | NE2000DVF_DL100XX}, 207 { PCMCIA_CARD(NEXTCOM, NEXTHAWK), 0}, 208 { PCMCIA_CARD(NEWMEDIA, LANSURFER), NE2000DVF_ANYFUNC}, 209 { PCMCIA_CARD(NEWMEDIA, LIVEWIRE), 0}, 210 { PCMCIA_CARD(OEM2, 100BASE), NE2000DVF_AX88X90}, 211 { PCMCIA_CARD(OEM2, ETHERNET), 0}, 212 { PCMCIA_CARD(OEM2, FAST_ETHERNET), NE2000DVF_AX88X90}, 213 { PCMCIA_CARD(OEM2, NE2000), 0}, 214 { PCMCIA_CARD(PLANET, SMARTCOM2000), 0 }, 215 { PCMCIA_CARD(PREMAX, PE200), 0}, 216 { PCMCIA_CARD(PSION, LANGLOBAL), 217 NE2000DVF_ANYFUNC | NE2000DVF_AX88X90 | NE2000DVF_MODEM}, 218 { PCMCIA_CARD(RACORE, ETHERNET), 0}, 219 { PCMCIA_CARD(RACORE, FASTENET), NE2000DVF_AX88X90}, 220 { PCMCIA_CARD(RACORE, 8041TX), NE2000DVF_AX88X90 | NE2000DVF_TC5299J}, 221 { PCMCIA_CARD(RELIA, COMBO), 0}, 222 { PCMCIA_CARD(RIOS, PCCARD3), 0}, 223 { PCMCIA_CARD(RPTI, EP400), 0}, 224 { PCMCIA_CARD(RPTI, EP401), 0}, 225 { PCMCIA_CARD(SMC, EZCARD), 0}, 226 { PCMCIA_CARD(SOCKET, EA_ETHER), 0}, 227 { PCMCIA_CARD(SOCKET, ES_1000), 0}, 228 { PCMCIA_CARD(SOCKET, LP_ETHER), 0}, 229 { PCMCIA_CARD(SOCKET, LP_ETHER_CF), 0}, 230 { PCMCIA_CARD(SOCKET, LP_ETH_10_100_CF), NE2000DVF_DL100XX}, 231 { PCMCIA_CARD(SVEC, COMBOCARD), 0}, 232 { PCMCIA_CARD(SVEC, LANCARD), 0}, 233 { PCMCIA_CARD(TAMARACK, ETHERNET), 0}, 234 { PCMCIA_CARD(TDK, CFE_10), 0}, 235 { PCMCIA_CARD(TDK, LAK_CD031), 0}, 236 { PCMCIA_CARD(TDK, DFL5610WS), 0}, 237 { PCMCIA_CARD(TELECOMDEVICE, LM5LT), 0 }, 238 { PCMCIA_CARD(TELECOMDEVICE, TCD_HPC100), NE2000DVF_AX88X90}, 239 { PCMCIA_CARD(TJ, PTJ_LAN_T), 0 }, 240 { PCMCIA_CARD(TOSHIBA2, LANCT00A), NE2000DVF_ANYFUNC | NE2000DVF_TOSHIBA}, 241 { PCMCIA_CARD(ZONET, ZEN), 0}, 242 { { NULL } } 243}; 244 245/* 246 * MII bit-bang glue 247 */ 248static uint32_t ed_pccard_dl100xx_mii_bitbang_read(device_t dev); 249static void ed_pccard_dl100xx_mii_bitbang_write(device_t dev, uint32_t val); 250 251static const struct mii_bitbang_ops ed_pccard_dl100xx_mii_bitbang_ops = { 252 ed_pccard_dl100xx_mii_bitbang_read, 253 ed_pccard_dl100xx_mii_bitbang_write, 254 { 255 ED_DL100XX_MII_DATAOUT, /* MII_BIT_MDO */ 256 ED_DL100XX_MII_DATAIN, /* MII_BIT_MDI */ 257 ED_DL100XX_MII_CLK, /* MII_BIT_MDC */ 258 ED_DL100XX_MII_DIROUT, /* MII_BIT_DIR_HOST_PHY */ 259 0 /* MII_BIT_DIR_PHY_HOST */ 260 } 261}; 262 263static uint32_t ed_pccard_ax88x90_mii_bitbang_read(device_t dev); 264static void ed_pccard_ax88x90_mii_bitbang_write(device_t dev, uint32_t val); 265 266static const struct mii_bitbang_ops ed_pccard_ax88x90_mii_bitbang_ops = { 267 ed_pccard_ax88x90_mii_bitbang_read, 268 ed_pccard_ax88x90_mii_bitbang_write, 269 { 270 ED_AX88X90_MII_DATAOUT, /* MII_BIT_MDO */ 271 ED_AX88X90_MII_DATAIN, /* MII_BIT_MDI */ 272 ED_AX88X90_MII_CLK, /* MII_BIT_MDC */ 273 0, /* MII_BIT_DIR_HOST_PHY */ 274 ED_AX88X90_MII_DIRIN /* MII_BIT_DIR_PHY_HOST */ 275 } 276}; 277 278static uint32_t ed_pccard_tc5299j_mii_bitbang_read(device_t dev); 279static void ed_pccard_tc5299j_mii_bitbang_write(device_t dev, uint32_t val); 280 281static const struct mii_bitbang_ops ed_pccard_tc5299j_mii_bitbang_ops = { 282 ed_pccard_tc5299j_mii_bitbang_read, 283 ed_pccard_tc5299j_mii_bitbang_write, 284 { 285 ED_TC5299J_MII_DATAOUT, /* MII_BIT_MDO */ 286 ED_TC5299J_MII_DATAIN, /* MII_BIT_MDI */ 287 ED_TC5299J_MII_CLK, /* MII_BIT_MDC */ 288 0, /* MII_BIT_DIR_HOST_PHY */ 289 ED_AX88X90_MII_DIRIN /* MII_BIT_DIR_PHY_HOST */ 290 } 291}; 292 293/* 294 * PC Card (PCMCIA) specific code. 295 */ 296static int ed_pccard_probe(device_t); 297static int ed_pccard_attach(device_t); 298static void ed_pccard_tick(struct ed_softc *); 299 300static int ed_pccard_dl100xx(device_t dev, const struct ed_product *); 301static void ed_pccard_dl100xx_mii_reset(struct ed_softc *sc); 302 303static int ed_pccard_ax88x90(device_t dev, const struct ed_product *); 304 305static int ed_miibus_readreg(device_t dev, int phy, int reg); 306static int ed_ifmedia_upd(struct ifnet *); 307static void ed_ifmedia_sts(struct ifnet *, struct ifmediareq *); 308 309static int ed_pccard_tc5299j(device_t dev, const struct ed_product *); 310 311static void 312ed_pccard_print_entry(const struct ed_product *pp) 313{ 314 int i; 315 316 printf("Product entry: "); 317 if (pp->prod.pp_name) 318 printf("name='%s',", pp->prod.pp_name); 319 printf("vendor=%#x,product=%#x", pp->prod.pp_vendor, 320 pp->prod.pp_product); 321 for (i = 0; i < 4; i++) 322 if (pp->prod.pp_cis[i]) 323 printf(",CIS%d='%s'", i, pp->prod.pp_cis[i]); 324 printf("\n"); 325} 326 327static int 328ed_pccard_probe(device_t dev) 329{ 330 const struct ed_product *pp, *pp2; 331 int error, first = 1; 332 uint32_t fcn = PCCARD_FUNCTION_UNSPEC; 333 334 /* Make sure we're a network function */ 335 error = pccard_get_function(dev, &fcn); 336 if (error != 0) 337 return (error); 338 339 if ((pp = (const struct ed_product *) pccard_product_lookup(dev, 340 (const struct pccard_product *) ed_pccard_products, 341 sizeof(ed_pccard_products[0]), NULL)) != NULL) { 342 if (pp->prod.pp_name != NULL) 343 device_set_desc(dev, pp->prod.pp_name); 344 /* 345 * Some devices don't ID themselves as network, but 346 * that's OK if the flags say so. 347 */ 348 if (!(pp->flags & NE2000DVF_ANYFUNC) && 349 fcn != PCCARD_FUNCTION_NETWORK) 350 return (ENXIO); 351 /* 352 * Some devices match multiple entries. Report that 353 * as a warning to help cull the table 354 */ 355 pp2 = pp; 356 while ((pp2 = (const struct ed_product *)pccard_product_lookup( 357 dev, (const struct pccard_product *)(pp2 + 1), 358 sizeof(ed_pccard_products[0]), NULL)) != NULL) { 359 if (first) { 360 device_printf(dev, 361 "Warning: card matches multiple entries. Report to imp@freebsd.org\n"); 362 ed_pccard_print_entry(pp); 363 first = 0; 364 } 365 ed_pccard_print_entry(pp2); 366 } 367 368 return (0); 369 } 370 return (ENXIO); 371} 372 373static int 374ed_pccard_rom_mac(device_t dev, uint8_t *enaddr) 375{ 376 struct ed_softc *sc = device_get_softc(dev); 377 uint8_t romdata[32], sum; 378 int i; 379 380 /* 381 * Read in the rom data at location 0. Since there are no 382 * NE-1000 based PC Card devices, we'll assume we're 16-bit. 383 * 384 * In researching what format this takes, I've found that the 385 * following appears to be true for multiple cards based on 386 * observation as well as datasheet digging. 387 * 388 * Data is stored in some ROM and is copied out 8 bits at a time 389 * into 16-bit wide locations. This means that the odd locations 390 * of the ROM are not used (and can be either 0 or ff). 391 * 392 * The contents appears to be as follows: 393 * PROM RAM 394 * Offset Offset What 395 * 0 0 ENETADDR 0 396 * 1 2 ENETADDR 1 397 * 2 4 ENETADDR 2 398 * 3 6 ENETADDR 3 399 * 4 8 ENETADDR 4 400 * 5 10 ENETADDR 5 401 * 6-13 12-26 Reserved (varies by manufacturer) 402 * 14 28 0x57 403 * 15 30 0x57 404 * 405 * Some manufacturers have another image of enetaddr from 406 * PROM offset 0x10 to 0x15 with 0x42 in 0x1e and 0x1f, but 407 * this doesn't appear to be universally documented in the 408 * datasheets. Some manufactuers have a card type, card config 409 * checksums, etc encoded into PROM offset 6-13, but deciphering it 410 * requires more knowledge about the exact underlying chipset than 411 * we possess (and maybe can possess). 412 */ 413 ed_pio_readmem(sc, 0, romdata, 32); 414 if (bootverbose) 415 device_printf(dev, "ROM DATA: %32D\n", romdata, " "); 416 if (romdata[28] != 0x57 || romdata[30] != 0x57) 417 return (0); 418 for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) 419 sum |= romdata[i * 2]; 420 if (sum == 0) 421 return (0); 422 for (i = 0; i < ETHER_ADDR_LEN; i++) 423 enaddr[i] = romdata[i * 2]; 424 return (1); 425} 426 427static int 428ed_pccard_add_modem(device_t dev) 429{ 430 device_printf(dev, "Need to write this code\n"); 431 return 0; 432} 433 434static int 435ed_pccard_kick_phy(struct ed_softc *sc) 436{ 437 struct mii_softc *miisc; 438 struct mii_data *mii; 439 440 mii = device_get_softc(sc->miibus); 441 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 442 PHY_RESET(miisc); 443 return (mii_mediachg(mii)); 444} 445 446static int 447ed_pccard_media_ioctl(struct ed_softc *sc, struct ifreq *ifr, u_long command) 448{ 449 struct mii_data *mii; 450 451 if (sc->miibus == NULL) 452 return (EINVAL); 453 mii = device_get_softc(sc->miibus); 454 return (ifmedia_ioctl(sc->ifp, ifr, &mii->mii_media, command)); 455} 456 457 458static void 459ed_pccard_mediachg(struct ed_softc *sc) 460{ 461 struct mii_data *mii; 462 463 if (sc->miibus == NULL) 464 return; 465 mii = device_get_softc(sc->miibus); 466 mii_mediachg(mii); 467} 468 469static int 470ed_pccard_attach(device_t dev) 471{ 472 u_char sum; 473 u_char enaddr[ETHER_ADDR_LEN]; 474 const struct ed_product *pp; 475 int error, i, flags, port_rid, modem_rid; 476 struct ed_softc *sc = device_get_softc(dev); 477 u_long size; 478 static uint16_t *intr_vals[] = {NULL, NULL}; 479 480 sc->dev = dev; 481 if ((pp = (const struct ed_product *) pccard_product_lookup(dev, 482 (const struct pccard_product *) ed_pccard_products, 483 sizeof(ed_pccard_products[0]), NULL)) == NULL) { 484 printf("Can't find\n"); 485 return (ENXIO); 486 } 487 modem_rid = port_rid = -1; 488 if (pp->flags & NE2000DVF_MODEM) { 489 for (i = 0; i < 4; i++) { 490 size = bus_get_resource_count(dev, SYS_RES_IOPORT, i); 491 if (size == ED_NOVELL_IO_PORTS) 492 port_rid = i; 493 else if (size == 8) 494 modem_rid = i; 495 } 496 if (port_rid == -1) { 497 device_printf(dev, "Cannot locate my ports!\n"); 498 return (ENXIO); 499 } 500 } else { 501 port_rid = 0; 502 } 503 /* Allocate the port resource during setup. */ 504 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 505 if (error) { 506 printf("alloc_port failed\n"); 507 return (error); 508 } 509 if (rman_get_size(sc->port_res) == ED_NOVELL_IO_PORTS / 2) { 510 port_rid++; 511 sc->port_res2 = bus_alloc_resource(dev, SYS_RES_IOPORT, 512 &port_rid, 0ul, ~0ul, 1, RF_ACTIVE); 513 if (sc->port_res2 == NULL || 514 rman_get_size(sc->port_res2) != ED_NOVELL_IO_PORTS / 2) { 515 error = ENXIO; 516 goto bad; 517 } 518 } 519 error = ed_alloc_irq(dev, 0, 0); 520 if (error) 521 goto bad; 522 523 /* 524 * Determine which chipset we are. Almost all the PC Card chipsets 525 * have the Novel ASIC and NIC offsets. There's 2 known cards that 526 * follow the WD80x3 conventions, which are handled as a special case. 527 */ 528 sc->asic_offset = ED_NOVELL_ASIC_OFFSET; 529 sc->nic_offset = ED_NOVELL_NIC_OFFSET; 530 error = ENXIO; 531 flags = device_get_flags(dev); 532 if (error != 0) 533 error = ed_pccard_dl100xx(dev, pp); 534 if (error != 0) 535 error = ed_pccard_ax88x90(dev, pp); 536 if (error != 0) 537 error = ed_pccard_tc5299j(dev, pp); 538 if (error != 0) { 539 error = ed_probe_Novell_generic(dev, flags); 540 printf("Novell generic probe failed: %d\n", error); 541 } 542 if (error != 0 && (pp->flags & NE2000DVF_TOSHIBA)) { 543 flags |= ED_FLAGS_TOSH_ETHER; 544 flags |= ED_FLAGS_PCCARD; 545 sc->asic_offset = ED_WD_ASIC_OFFSET; 546 sc->nic_offset = ED_WD_NIC_OFFSET; 547 error = ed_probe_WD80x3_generic(dev, flags, intr_vals); 548 } 549 if (error) 550 goto bad; 551 552 /* 553 * There are several ways to get the MAC address for the card. 554 * Some of the above probe routines can fill in the enaddr. If 555 * not, we run through a number of 'well known' locations: 556 * (1) From the PC Card FUNCE 557 * (2) From offset 0 in the shared memory 558 * (3) From a hinted offset in attribute memory 559 * (4) From 0xff0 in attribute memory 560 * If we can't get a non-zero MAC address from this list, we fail. 561 */ 562 for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) 563 sum |= sc->enaddr[i]; 564 if (sum == 0) { 565 pccard_get_ether(dev, enaddr); 566 if (bootverbose) 567 device_printf(dev, "CIS MAC %6D\n", enaddr, ":"); 568 for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) 569 sum |= enaddr[i]; 570 if (sum == 0 && ed_pccard_rom_mac(dev, enaddr)) { 571 if (bootverbose) 572 device_printf(dev, "ROM mac %6D\n", enaddr, 573 ":"); 574 sum++; 575 } 576 if (sum == 0 && pp->flags & NE2000DVF_ENADDR) { 577 for (i = 0; i < ETHER_ADDR_LEN; i++) { 578 pccard_attr_read_1(dev, pp->enoff + i * 2, 579 enaddr + i); 580 sum |= enaddr[i]; 581 } 582 if (bootverbose) 583 device_printf(dev, "Hint %x MAC %6D\n", 584 pp->enoff, enaddr, ":"); 585 } 586 if (sum == 0) { 587 for (i = 0; i < ETHER_ADDR_LEN; i++) { 588 pccard_attr_read_1(dev, ED_DEFAULT_MAC_OFFSET + 589 i * 2, enaddr + i); 590 sum |= enaddr[i]; 591 } 592 if (bootverbose) 593 device_printf(dev, "Fallback MAC %6D\n", 594 enaddr, ":"); 595 } 596 if (sum == 0) { 597 device_printf(dev, "Cannot extract MAC address.\n"); 598 ed_release_resources(dev); 599 return (ENXIO); 600 } 601 bcopy(enaddr, sc->enaddr, ETHER_ADDR_LEN); 602 } 603 604 error = ed_attach(dev); 605 if (error) 606 goto bad; 607 if (sc->chip_type == ED_CHIP_TYPE_DL10019 || 608 sc->chip_type == ED_CHIP_TYPE_DL10022) { 609 /* Try to attach an MII bus, but ignore errors. */ 610 ed_pccard_dl100xx_mii_reset(sc); 611 (void)mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, 612 ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 613 MII_OFFSET_ANY, MIIF_FORCEANEG); 614 } else if (sc->chip_type == ED_CHIP_TYPE_AX88190 || 615 sc->chip_type == ED_CHIP_TYPE_AX88790 || 616 sc->chip_type == ED_CHIP_TYPE_TC5299J) { 617 error = mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, 618 ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, 619 MII_OFFSET_ANY, MIIF_FORCEANEG); 620 if (error != 0) { 621 device_printf(dev, "attaching PHYs failed\n"); 622 goto bad; 623 } 624 } 625 if (sc->miibus != NULL) { 626 sc->sc_tick = ed_pccard_tick; 627 sc->sc_mediachg = ed_pccard_mediachg; 628 sc->sc_media_ioctl = ed_pccard_media_ioctl; 629 ed_pccard_kick_phy(sc); 630 } else { 631 ed_gen_ifmedia_init(sc); 632 } 633 if (modem_rid != -1) 634 ed_pccard_add_modem(dev); 635 636 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, 637 NULL, edintr, sc, &sc->irq_handle); 638 if (error) { 639 device_printf(dev, "setup intr failed %d \n", error); 640 goto bad; 641 } 642 643 return (0); 644bad: 645 ed_detach(dev); 646 return (error); 647} 648 649/* 650 * Probe the Ethernet MAC addrees for PCMCIA Linksys EtherFast 10/100 651 * and compatible cards (DL10019C Ethernet controller). 652 */ 653static int 654ed_pccard_dl100xx(device_t dev, const struct ed_product *pp) 655{ 656 struct ed_softc *sc = device_get_softc(dev); 657 u_char sum; 658 uint8_t id; 659 u_int memsize; 660 int i, error; 661 662 if (!(pp->flags & NE2000DVF_DL100XX)) 663 return (ENXIO); 664 if (bootverbose) 665 device_printf(dev, "Trying DL100xx\n"); 666 error = ed_probe_Novell_generic(dev, device_get_flags(dev)); 667 if (bootverbose && error) 668 device_printf(dev, "Novell generic probe failed: %d\n", error); 669 if (error != 0) 670 return (error); 671 672 /* 673 * Linksys registers(offset from ASIC base) 674 * 675 * 0x04-0x09 : Physical Address Register 0-5 (PAR0-PAR5) 676 * 0x0A : Card ID Register (CIR) 677 * 0x0B : Check Sum Register (SR) 678 */ 679 for (sum = 0, i = 0x04; i < 0x0c; i++) 680 sum += ed_asic_inb(sc, i); 681 if (sum != 0xff) { 682 if (bootverbose) 683 device_printf(dev, "Bad checksum %#x\n", sum); 684 return (ENXIO); /* invalid DL10019C */ 685 } 686 if (bootverbose) 687 device_printf(dev, "CIR is %d\n", ed_asic_inb(sc, 0xa)); 688 for (i = 0; i < ETHER_ADDR_LEN; i++) 689 sc->enaddr[i] = ed_asic_inb(sc, 0x04 + i); 690 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 691 id = ed_asic_inb(sc, 0xf); 692 sc->isa16bit = 1; 693 /* 694 * Hard code values based on the datasheet. We're NE-2000 compatible 695 * NIC with 24kb of packet memory starting at 24k offset. These 696 * cards also work with 16k at 16k, but don't work with 24k at 16k 697 * or 32k at 16k. 698 */ 699 sc->type = ED_TYPE_NE2000; 700 sc->mem_start = 24 * 1024; 701 memsize = sc->mem_size = 24 * 1024; 702 sc->mem_end = sc->mem_start + memsize; 703 sc->tx_page_start = memsize / ED_PAGE_SIZE; 704 sc->txb_cnt = 3; 705 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 706 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 707 708 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 709 710 ed_nic_outb(sc, ED_P0_PSTART, sc->mem_start / ED_PAGE_SIZE); 711 ed_nic_outb(sc, ED_P0_PSTOP, sc->mem_end / ED_PAGE_SIZE); 712 sc->vendor = ED_VENDOR_NOVELL; 713 sc->chip_type = (id & 0x90) == 0x90 ? 714 ED_CHIP_TYPE_DL10022 : ED_CHIP_TYPE_DL10019; 715 sc->type_str = ((id & 0x90) == 0x90) ? "DL10022" : "DL10019"; 716 sc->mii_bitbang_ops = &ed_pccard_dl100xx_mii_bitbang_ops; 717 return (0); 718} 719 720/* MII bit-twiddling routines for cards using Dlink chipset */ 721 722static void 723ed_pccard_dl100xx_mii_reset(struct ed_softc *sc) 724{ 725 if (sc->chip_type != ED_CHIP_TYPE_DL10022) 726 return; 727 728 ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2); 729 DELAY(10); 730 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 731 ED_DL10022_MII_RESET2 | ED_DL10022_MII_RESET1); 732 DELAY(10); 733 ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2); 734 DELAY(10); 735 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 736 ED_DL10022_MII_RESET2 | ED_DL10022_MII_RESET1); 737 DELAY(10); 738 ed_asic_outb(sc, ED_DL100XX_MIIBUS, 0); 739} 740 741static void 742ed_pccard_dl100xx_mii_bitbang_write(device_t dev, uint32_t val) 743{ 744 struct ed_softc *sc; 745 746 sc = device_get_softc(dev); 747 748 ed_asic_outb(sc, ED_DL100XX_MIIBUS, val); 749 ed_asic_barrier(sc, ED_DL100XX_MIIBUS, 1, 750 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 751} 752 753static uint32_t 754ed_pccard_dl100xx_mii_bitbang_read(device_t dev) 755{ 756 struct ed_softc *sc; 757 uint32_t val; 758 759 sc = device_get_softc(dev); 760 761 val = ed_asic_inb(sc, ED_DL100XX_MIIBUS); 762 ed_asic_barrier(sc, ED_DL100XX_MIIBUS, 1, 763 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 764 return (val); 765} 766 767static void 768ed_pccard_ax88x90_reset(struct ed_softc *sc) 769{ 770 int i; 771 772 /* Reset Card */ 773 ed_nic_barrier(sc, ED_P0_CR, 1, 774 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 775 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP | ED_CR_PAGE_0); 776 ed_nic_barrier(sc, ED_P0_CR, 1, 777 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 778 ed_asic_outb(sc, ED_NOVELL_RESET, ed_asic_inb(sc, ED_NOVELL_RESET)); 779 780 /* Wait for the RST bit to assert, but cap it at 10ms */ 781 for (i = 10000; !(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) && i > 0; 782 i--) 783 continue; 784 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RST); /* ACK INTR */ 785 if (i == 0) 786 device_printf(sc->dev, "Reset didn't finish\n"); 787} 788 789/* 790 * Probe and vendor-specific initialization routine for ax88x90 boards 791 */ 792static int 793ed_probe_ax88x90_generic(device_t dev, int flags) 794{ 795 struct ed_softc *sc = device_get_softc(dev); 796 u_int memsize; 797 static char test_pattern[32] = "THIS is A memory TEST pattern"; 798 char test_buffer[32]; 799 800 ed_pccard_ax88x90_reset(sc); 801 DELAY(10*1000); 802 803 /* Make sure that we really have an 8390 based board */ 804 if (!ed_probe_generic8390(sc)) 805 return (ENXIO); 806 807 sc->vendor = ED_VENDOR_NOVELL; 808 sc->mem_shared = 0; 809 sc->cr_proto = ED_CR_RD2; 810 811 /* 812 * This prevents packets from being stored in the NIC memory when the 813 * readmem routine turns on the start bit in the CR. We write some 814 * bytes in word mode and verify we can read them back. If we can't 815 * then we don't have an AX88x90 chip here. 816 */ 817 sc->isa16bit = 1; 818 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 819 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 820 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 821 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 822 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) != 0) 823 return (ENXIO); 824 825 /* 826 * Hard code values based on the datasheet. We're NE-2000 compatible 827 * NIC with 16kb of packet memory starting at 16k offset. 828 */ 829 sc->type = ED_TYPE_NE2000; 830 memsize = sc->mem_size = 16*1024; 831 sc->mem_start = 16 * 1024; 832 if (ed_asic_inb(sc, ED_AX88X90_TEST) != 0) 833 sc->chip_type = ED_CHIP_TYPE_AX88790; 834 else { 835 sc->chip_type = ED_CHIP_TYPE_AX88190; 836 /* 837 * The AX88190 (not A) has external 64k SRAM. Probe for this 838 * here. Most of the cards I have either use the AX88190A 839 * part, or have only 32k SRAM for some reason, so I don't 840 * know if this works or not. 841 */ 842 ed_pio_writemem(sc, test_pattern, 32768, sizeof(test_pattern)); 843 ed_pio_readmem(sc, 32768, test_buffer, sizeof(test_pattern)); 844 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 845 sc->mem_start = 2*1024; 846 memsize = sc->mem_size = 62 * 1024; 847 } 848 } 849 sc->mem_end = sc->mem_start + memsize; 850 sc->tx_page_start = memsize / ED_PAGE_SIZE; 851 if (sc->mem_size > 16 * 1024) 852 sc->txb_cnt = 3; 853 else 854 sc->txb_cnt = 2; 855 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 856 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 857 858 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 859 860 ed_nic_outb(sc, ED_P0_PSTART, sc->mem_start / ED_PAGE_SIZE); 861 ed_nic_outb(sc, ED_P0_PSTOP, sc->mem_end / ED_PAGE_SIZE); 862 863 /* Get the mac before we go -- It's just at 0x400 in "SRAM" */ 864 ed_pio_readmem(sc, 0x400, sc->enaddr, ETHER_ADDR_LEN); 865 866 /* clear any pending interrupts that might have occurred above */ 867 ed_nic_outb(sc, ED_P0_ISR, 0xff); 868 sc->sc_write_mbufs = ed_pio_write_mbufs; 869 return (0); 870} 871 872static int 873ed_pccard_ax88x90_check_mii(device_t dev, struct ed_softc *sc) 874{ 875 int i, id; 876 877 /* 878 * All AX88x90 devices have MII and a PHY, so we use this to weed out 879 * chips that would otherwise make it through the tests we have after 880 * this point. 881 */ 882 for (i = 0; i < 32; i++) { 883 id = ed_miibus_readreg(dev, i, MII_BMSR); 884 if (id != 0 && id != 0xffff) 885 break; 886 } 887 /* 888 * Found one, we're good. 889 */ 890 if (i != 32) 891 return (0); 892 /* 893 * Didn't find anything, so try to power up and try again. The PHY 894 * may be not responding because we're in power down mode. 895 */ 896 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 897 return (ENXIO); 898 pccard_ccr_write_1(dev, PCCARD_CCR_STATUS, PCCARD_CCR_STATUS_PWRDWN); 899 for (i = 0; i < 32; i++) { 900 id = ed_miibus_readreg(dev, i, MII_BMSR); 901 if (id != 0 && id != 0xffff) 902 break; 903 } 904 /* 905 * Still no joy? We're AFU, punt. 906 */ 907 if (i == 32) 908 return (ENXIO); 909 return (0); 910} 911 912/* 913 * Special setup for AX88[17]90 914 */ 915static int 916ed_pccard_ax88x90(device_t dev, const struct ed_product *pp) 917{ 918 int error; 919 int iobase; 920 struct ed_softc *sc = device_get_softc(dev); 921 922 if (!(pp->flags & NE2000DVF_AX88X90)) 923 return (ENXIO); 924 925 if (bootverbose) 926 device_printf(dev, "Checking AX88x90\n"); 927 928 /* 929 * Set the IOBASE Register. The AX88x90 cards are potentially 930 * multifunction cards, and thus requires a slight workaround. 931 * We write the address the card is at, on the off chance that this 932 * card is not MFC. 933 * XXX I'm not sure that this is still needed... 934 */ 935 iobase = rman_get_start(sc->port_res); 936 pccard_ccr_write_1(dev, PCCARD_CCR_IOBASE0, iobase & 0xff); 937 pccard_ccr_write_1(dev, PCCARD_CCR_IOBASE1, (iobase >> 8) & 0xff); 938 939 error = ed_probe_ax88x90_generic(dev, device_get_flags(dev)); 940 if (error) { 941 if (bootverbose) 942 device_printf(dev, "probe ax88x90 failed %d\n", 943 error); 944 return (error); 945 } 946 sc->mii_bitbang_ops = &ed_pccard_ax88x90_mii_bitbang_ops; 947 error = ed_pccard_ax88x90_check_mii(dev, sc); 948 if (error) 949 return (error); 950 sc->vendor = ED_VENDOR_NOVELL; 951 sc->type = ED_TYPE_NE2000; 952 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 953 sc->type_str = "AX88190"; 954 else 955 sc->type_str = "AX88790"; 956 return (0); 957} 958 959static void 960ed_pccard_ax88x90_mii_bitbang_write(device_t dev, uint32_t val) 961{ 962 struct ed_softc *sc; 963 964 sc = device_get_softc(dev); 965 966 ed_asic_outb(sc, ED_AX88X90_MIIBUS, val); 967 ed_asic_barrier(sc, ED_AX88X90_MIIBUS, 1, 968 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 969} 970 971static uint32_t 972ed_pccard_ax88x90_mii_bitbang_read(device_t dev) 973{ 974 struct ed_softc *sc; 975 uint32_t val; 976 977 sc = device_get_softc(dev); 978 979 val = ed_asic_inb(sc, ED_AX88X90_MIIBUS); 980 ed_asic_barrier(sc, ED_AX88X90_MIIBUS, 1, 981 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 982 return (val); 983} 984 985/* 986 * Special setup for TC5299J 987 */ 988static int 989ed_pccard_tc5299j(device_t dev, const struct ed_product *pp) 990{ 991 int error, i, id; 992 char *ts; 993 struct ed_softc *sc = device_get_softc(dev); 994 995 if (!(pp->flags & NE2000DVF_TC5299J)) 996 return (ENXIO); 997 998 if (bootverbose) 999 device_printf(dev, "Checking Tc5299j\n"); 1000 1001 error = ed_probe_Novell_generic(dev, device_get_flags(dev)); 1002 if (bootverbose) 1003 device_printf(dev, "Novell generic probe failed: %d\n", error); 1004 if (error != 0) 1005 return (error); 1006 1007 /* 1008 * Check to see if we have a MII PHY ID at any address. All TC5299J 1009 * devices have MII and a PHY, so we use this to weed out chips that 1010 * would otherwise make it through the tests we have after this point. 1011 */ 1012 sc->mii_bitbang_ops = &ed_pccard_tc5299j_mii_bitbang_ops; 1013 for (i = 0; i < 32; i++) { 1014 id = ed_miibus_readreg(dev, i, MII_PHYIDR1); 1015 if (id != 0 && id != 0xffff) 1016 break; 1017 } 1018 if (i == 32) 1019 return (ENXIO); 1020 ts = "TC5299J"; 1021 if (ed_pccard_rom_mac(dev, sc->enaddr) == 0) 1022 return (ENXIO); 1023 sc->vendor = ED_VENDOR_NOVELL; 1024 sc->type = ED_TYPE_NE2000; 1025 sc->chip_type = ED_CHIP_TYPE_TC5299J; 1026 sc->type_str = ts; 1027 return (0); 1028} 1029 1030static void 1031ed_pccard_tc5299j_mii_bitbang_write(device_t dev, uint32_t val) 1032{ 1033 struct ed_softc *sc; 1034 1035 sc = device_get_softc(dev); 1036 1037 /* We are already on page 3. */ 1038 ed_nic_outb(sc, ED_TC5299J_MIIBUS, val); 1039 ed_nic_barrier(sc, ED_TC5299J_MIIBUS, 1, 1040 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1041} 1042 1043static uint32_t 1044ed_pccard_tc5299j_mii_bitbang_read(device_t dev) 1045{ 1046 struct ed_softc *sc; 1047 uint32_t val; 1048 1049 sc = device_get_softc(dev); 1050 1051 /* We are already on page 3. */ 1052 val = ed_asic_inb(sc, ED_TC5299J_MIIBUS); 1053 ed_nic_barrier(sc, ED_TC5299J_MIIBUS, 1, 1054 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1055 return (val); 1056} 1057 1058/* 1059 * MII bus support routines. 1060 */ 1061static int 1062ed_miibus_readreg(device_t dev, int phy, int reg) 1063{ 1064 struct ed_softc *sc; 1065 int val; 1066 uint8_t cr = 0; 1067 1068 sc = device_get_softc(dev); 1069 /* 1070 * The AX88790 has an interesting quirk. It has an internal phy that 1071 * needs a special bit set to access, but can also have additional 1072 * external PHYs set for things like HomeNET media. When accessing 1073 * the internal PHY, a bit has to be set, when accessing the external 1074 * PHYs, it must be clear. See Errata 1, page 51, in the AX88790 1075 * datasheet for more details. 1076 * 1077 * Also, PHYs above 16 appear to be phantoms on some cards, but not 1078 * others. Registers read for this are often the same as prior values 1079 * read. Filter all register requests to 17-31. 1080 */ 1081 if (sc->chip_type == ED_CHIP_TYPE_AX88790) { 1082 if (phy > 0x10) 1083 return (0); 1084 if (phy == 0x10) 1085 ed_asic_outb(sc, ED_AX88X90_GPIO, 1086 ED_AX88X90_GPIO_INT_PHY); 1087 else 1088 ed_asic_outb(sc, ED_AX88X90_GPIO, 0); 1089 ed_asic_barrier(sc, ED_AX88X90_GPIO, 1, 1090 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1091 } else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1092 /* Select page 3. */ 1093 ed_nic_barrier(sc, ED_P0_CR, 1, 1094 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1095 cr = ed_nic_inb(sc, ED_P0_CR); 1096 ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3); 1097 ed_nic_barrier(sc, ED_P0_CR, 1, 1098 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1099 } 1100 val = mii_bitbang_readreg(dev, sc->mii_bitbang_ops, phy, reg); 1101 if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1102 /* Restore prior page. */ 1103 ed_nic_outb(sc, ED_P0_CR, cr); 1104 ed_nic_barrier(sc, ED_P0_CR, 1, 1105 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1106 } 1107 return (val); 1108} 1109 1110static int 1111ed_miibus_writereg(device_t dev, int phy, int reg, int data) 1112{ 1113 struct ed_softc *sc; 1114 uint8_t cr = 0; 1115 1116 sc = device_get_softc(dev); 1117 /* See ed_miibus_readreg for details */ 1118 if (sc->chip_type == ED_CHIP_TYPE_AX88790) { 1119 if (phy > 0x10) 1120 return (0); 1121 if (phy == 0x10) 1122 ed_asic_outb(sc, ED_AX88X90_GPIO, 1123 ED_AX88X90_GPIO_INT_PHY); 1124 else 1125 ed_asic_outb(sc, ED_AX88X90_GPIO, 0); 1126 ed_asic_barrier(sc, ED_AX88X90_GPIO, 1, 1127 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1128 } else if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1129 /* Select page 3. */ 1130 ed_nic_barrier(sc, ED_P0_CR, 1, 1131 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1132 cr = ed_nic_inb(sc, ED_P0_CR); 1133 ed_nic_outb(sc, ED_P0_CR, cr | ED_CR_PAGE_3); 1134 ed_nic_barrier(sc, ED_P0_CR, 1, 1135 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1136 } 1137 mii_bitbang_writereg(dev, sc->mii_bitbang_ops, phy, reg, data); 1138 if (sc->chip_type == ED_CHIP_TYPE_TC5299J) { 1139 /* Restore prior page. */ 1140 ed_nic_outb(sc, ED_P0_CR, cr); 1141 ed_nic_barrier(sc, ED_P0_CR, 1, 1142 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1143 } 1144 return (0); 1145} 1146 1147static int 1148ed_ifmedia_upd(struct ifnet *ifp) 1149{ 1150 struct ed_softc *sc; 1151 int error; 1152 1153 sc = ifp->if_softc; 1154 ED_LOCK(sc); 1155 if (sc->miibus == NULL) { 1156 ED_UNLOCK(sc); 1157 return (ENXIO); 1158 } 1159 1160 error = ed_pccard_kick_phy(sc); 1161 ED_UNLOCK(sc); 1162 return (error); 1163} 1164 1165static void 1166ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1167{ 1168 struct ed_softc *sc; 1169 struct mii_data *mii; 1170 1171 sc = ifp->if_softc; 1172 ED_LOCK(sc); 1173 if (sc->miibus == NULL) { 1174 return; 1175 ED_UNLOCK(sc); 1176 } 1177 1178 mii = device_get_softc(sc->miibus); 1179 mii_pollstat(mii); 1180 ifmr->ifm_active = mii->mii_media_active; 1181 ifmr->ifm_status = mii->mii_media_status; 1182 ED_UNLOCK(sc); 1183} 1184 1185static void 1186ed_child_detached(device_t dev, device_t child) 1187{ 1188 struct ed_softc *sc; 1189 1190 sc = device_get_softc(dev); 1191 if (child == sc->miibus) 1192 sc->miibus = NULL; 1193} 1194 1195static void 1196ed_pccard_tick(struct ed_softc *sc) 1197{ 1198 struct mii_data *mii; 1199 int media = 0; 1200 1201 ED_ASSERT_LOCKED(sc); 1202 if (sc->miibus != NULL) { 1203 mii = device_get_softc(sc->miibus); 1204 media = mii->mii_media_status; 1205 mii_tick(mii); 1206 if (mii->mii_media_status & IFM_ACTIVE && 1207 media != mii->mii_media_status) { 1208 if (sc->chip_type == ED_CHIP_TYPE_DL10022) { 1209 ed_asic_outb(sc, ED_DL10022_DIAG, 1210 (mii->mii_media_active & IFM_FDX) ? 1211 ED_DL10022_COLLISON_DIS : 0); 1212#ifdef notyet 1213 } else if (sc->chip_type == ED_CHIP_TYPE_DL10019) { 1214 write_asic(sc, ED_DL10019_MAGIC, 1215 (mii->mii_media_active & IFM_FDX) ? 1216 DL19FDUPLX : 0); 1217#endif 1218 } 1219 } 1220 1221 } 1222} 1223 1224static device_method_t ed_pccard_methods[] = { 1225 /* Device interface */ 1226 DEVMETHOD(device_probe, ed_pccard_probe), 1227 DEVMETHOD(device_attach, ed_pccard_attach), 1228 DEVMETHOD(device_detach, ed_detach), 1229 1230 /* Bus interface */ 1231 DEVMETHOD(bus_child_detached, ed_child_detached), 1232 1233 /* MII interface */ 1234 DEVMETHOD(miibus_readreg, ed_miibus_readreg), 1235 DEVMETHOD(miibus_writereg, ed_miibus_writereg), 1236 1237 DEVMETHOD_END 1238}; 1239 1240static driver_t ed_pccard_driver = { 1241 "ed", 1242 ed_pccard_methods, 1243 sizeof(struct ed_softc) 1244}; 1245 1246DRIVER_MODULE(ed, pccard, ed_pccard_driver, ed_devclass, 0, NULL); 1247DRIVER_MODULE(miibus, ed, miibus_driver, miibus_devclass, 0, NULL); 1248MODULE_DEPEND(ed, miibus, 1, 1, 1); 1249MODULE_DEPEND(ed, ether, 1, 1, 1); 1250