1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <dev/drm2/drmP.h> 33#include "radeon.h" 34#include "radeon_asic.h" 35#include "rs400d.h" 36 37/* This files gather functions specifics to : rs400,rs480 */ 38static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 39 40void rs400_gart_adjust_size(struct radeon_device *rdev) 41{ 42 /* Check gart size */ 43 switch (rdev->mc.gtt_size/(1024*1024)) { 44 case 32: 45 case 64: 46 case 128: 47 case 256: 48 case 512: 49 case 1024: 50 case 2048: 51 break; 52 default: 53 DRM_ERROR("Unable to use IGP GART size %uM\n", 54 (unsigned)(rdev->mc.gtt_size >> 20)); 55 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); 56 DRM_ERROR("Forcing to 32M GART size\n"); 57 rdev->mc.gtt_size = 32 * 1024 * 1024; 58 return; 59 } 60} 61 62void rs400_gart_tlb_flush(struct radeon_device *rdev) 63{ 64 uint32_t tmp; 65 unsigned int timeout = rdev->usec_timeout; 66 67 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); 68 do { 69 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 70 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) 71 break; 72 DRM_UDELAY(1); 73 timeout--; 74 } while (timeout > 0); 75 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); 76} 77 78int rs400_gart_init(struct radeon_device *rdev) 79{ 80 int r; 81 82 if (rdev->gart.ptr) { 83 DRM_ERROR("RS400 GART already initialized\n"); 84 return 0; 85 } 86 /* Check gart size */ 87 switch(rdev->mc.gtt_size / (1024 * 1024)) { 88 case 32: 89 case 64: 90 case 128: 91 case 256: 92 case 512: 93 case 1024: 94 case 2048: 95 break; 96 default: 97 return -EINVAL; 98 } 99 /* Initialize common gart structure */ 100 r = radeon_gart_init(rdev); 101 if (r) 102 return r; 103 if (rs400_debugfs_pcie_gart_info_init(rdev)) 104 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); 105 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 106 return radeon_gart_table_ram_alloc(rdev); 107} 108 109int rs400_gart_enable(struct radeon_device *rdev) 110{ 111 uint32_t size_reg; 112 uint32_t tmp; 113 114 radeon_gart_restore(rdev); 115 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 116 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 117 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 118 /* Check gart size */ 119 switch(rdev->mc.gtt_size / (1024 * 1024)) { 120 case 32: 121 size_reg = RS480_VA_SIZE_32MB; 122 break; 123 case 64: 124 size_reg = RS480_VA_SIZE_64MB; 125 break; 126 case 128: 127 size_reg = RS480_VA_SIZE_128MB; 128 break; 129 case 256: 130 size_reg = RS480_VA_SIZE_256MB; 131 break; 132 case 512: 133 size_reg = RS480_VA_SIZE_512MB; 134 break; 135 case 1024: 136 size_reg = RS480_VA_SIZE_1GB; 137 break; 138 case 2048: 139 size_reg = RS480_VA_SIZE_2GB; 140 break; 141 default: 142 return -EINVAL; 143 } 144 /* It should be fine to program it to max value */ 145 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 146 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); 147 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); 148 } else { 149 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); 150 WREG32(RS480_AGP_BASE_2, 0); 151 } 152 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); 153 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); 154 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 155 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); 156 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 157 WREG32(RADEON_BUS_CNTL, tmp); 158 } else { 159 WREG32(RADEON_MC_AGP_LOCATION, tmp); 160 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 161 WREG32(RADEON_BUS_CNTL, tmp); 162 } 163 /* Table should be in 32bits address space so ignore bits above. */ 164 tmp = (u32)rdev->gart.table_addr & 0xfffff000; 165 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; 166 167 WREG32_MC(RS480_GART_BASE, tmp); 168 /* TODO: more tweaking here */ 169 WREG32_MC(RS480_GART_FEATURE_ID, 170 (RS480_TLB_ENABLE | 171 RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); 172 /* Disable snooping */ 173 WREG32_MC(RS480_AGP_MODE_CNTL, 174 (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); 175 /* Disable AGP mode */ 176 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { 177 tmp = RREG32_MC(RS690_MC_NB_CNTL); 178 tmp &= ~(RS690_HIDE_MMCFG_BAR | 179 RS690_AGPMODE30 | 180 RS690_AGP30ENHANCED); 181 WREG32_MC(RS690_MC_NB_CNTL, tmp); 182 WREG32_MC(RS480_MC_MISC_CNTL, 183 (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); 184 } else { 185 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 186 } 187 /* Enable gart */ 188 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); 189 rs400_gart_tlb_flush(rdev); 190 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 191 (unsigned)(rdev->mc.gtt_size >> 20), 192 (unsigned long long)rdev->gart.table_addr); 193 rdev->gart.ready = true; 194 return 0; 195} 196 197void rs400_gart_disable(struct radeon_device *rdev) 198{ 199 uint32_t tmp; 200 201 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 202 tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; 203 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); 204 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 205} 206 207void rs400_gart_fini(struct radeon_device *rdev) 208{ 209 radeon_gart_fini(rdev); 210 rs400_gart_disable(rdev); 211 radeon_gart_table_ram_free(rdev); 212} 213 214#define RS400_PTE_WRITEABLE (1 << 2) 215#define RS400_PTE_READABLE (1 << 3) 216 217int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 218{ 219 uint32_t entry; 220 u32 *gtt = rdev->gart.ptr; 221 222 if (i < 0 || i > rdev->gart.num_gpu_pages) { 223 return -EINVAL; 224 } 225 226 entry = (lower_32_bits(addr) & 0xfffff000) | 227 ((upper_32_bits(addr) & 0xff) << 4) | 228 RS400_PTE_WRITEABLE | RS400_PTE_READABLE; 229 entry = cpu_to_le32(entry); 230 gtt[i] = entry; 231 return 0; 232} 233 234int rs400_mc_wait_for_idle(struct radeon_device *rdev) 235{ 236 unsigned i; 237 uint32_t tmp; 238 239 for (i = 0; i < rdev->usec_timeout; i++) { 240 /* read MC_STATUS */ 241 tmp = RREG32(RADEON_MC_STATUS); 242 if (tmp & RADEON_MC_IDLE) { 243 return 0; 244 } 245 DRM_UDELAY(1); 246 } 247 return -1; 248} 249 250static void rs400_gpu_init(struct radeon_device *rdev) 251{ 252 /* FIXME: is this correct ? */ 253 r420_pipes_init(rdev); 254 if (rs400_mc_wait_for_idle(rdev)) { 255 DRM_ERROR("rs400: Failed to wait MC idle while " 256 "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); 257 } 258} 259 260static void rs400_mc_init(struct radeon_device *rdev) 261{ 262 u64 base; 263 264 rs400_gart_adjust_size(rdev); 265 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); 266 /* DDR for all card after R300 & IGP */ 267 rdev->mc.vram_is_ddr = true; 268 rdev->mc.vram_width = 128; 269 r100_vram_init_sizes(rdev); 270 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 271 radeon_vram_location(rdev, &rdev->mc, base); 272 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 273 radeon_gtt_location(rdev, &rdev->mc); 274 radeon_update_bandwidth_info(rdev); 275} 276 277uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) 278{ 279 uint32_t r; 280 281 WREG32(RS480_NB_MC_INDEX, reg & 0xff); 282 r = RREG32(RS480_NB_MC_DATA); 283 WREG32(RS480_NB_MC_INDEX, 0xff); 284 return r; 285} 286 287void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 288{ 289 WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); 290 WREG32(RS480_NB_MC_DATA, (v)); 291 WREG32(RS480_NB_MC_INDEX, 0xff); 292} 293 294#if defined(CONFIG_DEBUG_FS) 295static int rs400_debugfs_gart_info(struct seq_file *m, void *data) 296{ 297 struct drm_info_node *node = (struct drm_info_node *) m->private; 298 struct drm_device *dev = node->minor->dev; 299 struct radeon_device *rdev = dev->dev_private; 300 uint32_t tmp; 301 302 tmp = RREG32(RADEON_HOST_PATH_CNTL); 303 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 304 tmp = RREG32(RADEON_BUS_CNTL); 305 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 306 tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); 307 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); 308 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { 309 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); 310 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); 311 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); 312 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); 313 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); 314 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); 315 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); 316 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); 317 tmp = RREG32(RS690_HDP_FB_LOCATION); 318 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); 319 } else { 320 tmp = RREG32(RADEON_AGP_BASE); 321 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 322 tmp = RREG32(RS480_AGP_BASE_2); 323 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); 324 tmp = RREG32(RADEON_MC_AGP_LOCATION); 325 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 326 } 327 tmp = RREG32_MC(RS480_GART_BASE); 328 seq_printf(m, "GART_BASE 0x%08x\n", tmp); 329 tmp = RREG32_MC(RS480_GART_FEATURE_ID); 330 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); 331 tmp = RREG32_MC(RS480_AGP_MODE_CNTL); 332 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); 333 tmp = RREG32_MC(RS480_MC_MISC_CNTL); 334 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); 335 tmp = RREG32_MC(0x5F); 336 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); 337 tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); 338 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); 339 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); 340 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); 341 tmp = RREG32_MC(0x3B); 342 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); 343 tmp = RREG32_MC(0x3C); 344 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); 345 tmp = RREG32_MC(0x30); 346 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); 347 tmp = RREG32_MC(0x31); 348 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); 349 tmp = RREG32_MC(0x32); 350 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); 351 tmp = RREG32_MC(0x33); 352 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); 353 tmp = RREG32_MC(0x34); 354 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); 355 tmp = RREG32_MC(0x35); 356 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); 357 tmp = RREG32_MC(0x36); 358 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); 359 tmp = RREG32_MC(0x37); 360 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); 361 return 0; 362} 363 364static struct drm_info_list rs400_gart_info_list[] = { 365 {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, 366}; 367#endif 368 369static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 370{ 371#if defined(CONFIG_DEBUG_FS) 372 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); 373#else 374 return 0; 375#endif 376} 377 378static void rs400_mc_program(struct radeon_device *rdev) 379{ 380 struct r100_mc_save save; 381 382 /* Stops all mc clients */ 383 r100_mc_stop(rdev, &save); 384 385 /* Wait for mc idle */ 386 if (rs400_mc_wait_for_idle(rdev)) 387 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); 388 WREG32(R_000148_MC_FB_LOCATION, 389 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 390 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 391 392 r100_mc_resume(rdev, &save); 393} 394 395static int rs400_startup(struct radeon_device *rdev) 396{ 397 int r; 398 399 r100_set_common_regs(rdev); 400 401 rs400_mc_program(rdev); 402 /* Resume clock */ 403 r300_clock_startup(rdev); 404 /* Initialize GPU configuration (# pipes, ...) */ 405 rs400_gpu_init(rdev); 406 r100_enable_bm(rdev); 407 /* Initialize GART (initialize after TTM so we can allocate 408 * memory through TTM but finalize after TTM) */ 409 r = rs400_gart_enable(rdev); 410 if (r) 411 return r; 412 413 /* allocate wb buffer */ 414 r = radeon_wb_init(rdev); 415 if (r) 416 return r; 417 418 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 419 if (r) { 420 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 421 return r; 422 } 423 424 /* Enable IRQ */ 425 r100_irq_set(rdev); 426 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 427 /* 1M ring buffer */ 428 r = r100_cp_init(rdev, 1024 * 1024); 429 if (r) { 430 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 431 return r; 432 } 433 434 r = radeon_ib_pool_init(rdev); 435 if (r) { 436 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 437 return r; 438 } 439 440 return 0; 441} 442 443int rs400_resume(struct radeon_device *rdev) 444{ 445 int r; 446 447 /* Make sur GART are not working */ 448 rs400_gart_disable(rdev); 449 /* Resume clock before doing reset */ 450 r300_clock_startup(rdev); 451 /* setup MC before calling post tables */ 452 rs400_mc_program(rdev); 453 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 454 if (radeon_asic_reset(rdev)) { 455 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 456 RREG32(R_000E40_RBBM_STATUS), 457 RREG32(R_0007C0_CP_STAT)); 458 } 459 /* post */ 460 radeon_combios_asic_init(rdev->ddev); 461 /* Resume clock after posting */ 462 r300_clock_startup(rdev); 463 /* Initialize surface registers */ 464 radeon_surface_init(rdev); 465 466 rdev->accel_working = true; 467 r = rs400_startup(rdev); 468 if (r) { 469 rdev->accel_working = false; 470 } 471 return r; 472} 473 474int rs400_suspend(struct radeon_device *rdev) 475{ 476 r100_cp_disable(rdev); 477 radeon_wb_disable(rdev); 478 r100_irq_disable(rdev); 479 rs400_gart_disable(rdev); 480 return 0; 481} 482 483void rs400_fini(struct radeon_device *rdev) 484{ 485 r100_cp_fini(rdev); 486 radeon_wb_fini(rdev); 487 radeon_ib_pool_fini(rdev); 488 radeon_gem_fini(rdev); 489 rs400_gart_fini(rdev); 490 radeon_irq_kms_fini(rdev); 491 radeon_fence_driver_fini(rdev); 492 radeon_bo_fini(rdev); 493 radeon_atombios_fini(rdev); 494 free(rdev->bios, DRM_MEM_DRIVER); 495 rdev->bios = NULL; 496} 497 498int rs400_init(struct radeon_device *rdev) 499{ 500 int r; 501 502 /* Disable VGA */ 503 r100_vga_render_disable(rdev); 504 /* Initialize scratch registers */ 505 radeon_scratch_init(rdev); 506 /* Initialize surface registers */ 507 radeon_surface_init(rdev); 508 /* TODO: disable VGA need to use VGA request */ 509 /* restore some register to sane defaults */ 510 r100_restore_sanity(rdev); 511 /* BIOS*/ 512 if (!radeon_get_bios(rdev)) { 513 if (ASIC_IS_AVIVO(rdev)) 514 return -EINVAL; 515 } 516 if (rdev->is_atom_bios) { 517 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 518 return -EINVAL; 519 } else { 520 r = radeon_combios_init(rdev); 521 if (r) 522 return r; 523 } 524 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 525 if (radeon_asic_reset(rdev)) { 526 dev_warn(rdev->dev, 527 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 528 RREG32(R_000E40_RBBM_STATUS), 529 RREG32(R_0007C0_CP_STAT)); 530 } 531 /* check if cards are posted or not */ 532 if (radeon_boot_test_post_card(rdev) == false) 533 return -EINVAL; 534 535 /* Initialize clocks */ 536 radeon_get_clock_info(rdev->ddev); 537 /* initialize memory controller */ 538 rs400_mc_init(rdev); 539 /* Fence driver */ 540 r = radeon_fence_driver_init(rdev); 541 if (r) 542 return r; 543 r = radeon_irq_kms_init(rdev); 544 if (r) 545 return r; 546 /* Memory manager */ 547 r = radeon_bo_init(rdev); 548 if (r) 549 return r; 550 r = rs400_gart_init(rdev); 551 if (r) 552 return r; 553 r300_set_reg_safe(rdev); 554 555 rdev->accel_working = true; 556 r = rs400_startup(rdev); 557 if (r) { 558 /* Somethings want wront with the accel init stop accel */ 559 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 560 r100_cp_fini(rdev); 561 radeon_wb_fini(rdev); 562 radeon_ib_pool_fini(rdev); 563 rs400_gart_fini(rdev); 564 radeon_irq_kms_fini(rdev); 565 rdev->accel_working = false; 566 } 567 return 0; 568} 569