1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 *
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD$");
28
29#include <dev/drm2/drmP.h>
30#include <dev/drm2/radeon/radeon_drm.h>
31#include <dev/iicbus/iic.h>
32#include <dev/iicbus/iiconf.h>
33#include <dev/iicbus/iicbus.h>
34#include "radeon.h"
35#include "atom.h"
36#include "iicbus_if.h"
37#include "iicbb_if.h"
38
39#define TARGET_HW_I2C_CLOCK 50
40
41/* these are a limitation of ProcessI2cChannelTransaction not the hw */
42#define ATOM_MAX_HW_I2C_WRITE 2
43#define ATOM_MAX_HW_I2C_READ  255
44
45static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
46				 u8 slave_addr, u8 flags,
47				 u8 *buf, u8 num)
48{
49	struct drm_device *dev = chan->dev;
50	struct radeon_device *rdev = dev->dev_private;
51	PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
52	int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
53	unsigned char *base;
54	u16 out;
55
56	memset(&args, 0, sizeof(args));
57
58	base = (unsigned char *)rdev->mode_info.atom_context->scratch;
59
60	if (flags & HW_I2C_WRITE) {
61		if (num > ATOM_MAX_HW_I2C_WRITE) {
62			DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 2)\n", num);
63			return EINVAL;
64		}
65		memcpy(&out, buf, num);
66		args.lpI2CDataOut = cpu_to_le16(out);
67	}
68
69	args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
70	args.ucRegIndex = 0;
71	args.ucTransBytes = num;
72	args.ucSlaveAddr = slave_addr << 1;
73	args.ucLineNumber = chan->rec.i2c_id;
74
75	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
76
77	/* error */
78	if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
79		DRM_DEBUG_KMS("hw_i2c error\n");
80		return EIO;
81	}
82
83	if (!(flags & HW_I2C_WRITE))
84		memcpy(buf, base, num);
85
86	return 0;
87}
88
89static int
90radeon_atom_hw_i2c_xfer(device_t dev, struct iic_msg *msgs, u_int num)
91{
92	struct radeon_i2c_chan *i2c = device_get_softc(dev);
93	struct iic_msg *p;
94	int i, remaining, current_count, buffer_offset, max_bytes, ret;
95	u8 buf = 0, flags;
96
97	/* check for bus probe */
98	p = &msgs[0];
99	if ((num == 1) && (p->len == 0)) {
100		ret = radeon_process_i2c_ch(i2c,
101					    p->slave, HW_I2C_WRITE,
102					    &buf, 1);
103		if (ret)
104			return ret;
105		else
106			return (0);
107	}
108
109	for (i = 0; i < num; i++) {
110		p = &msgs[i];
111		remaining = p->len;
112		buffer_offset = 0;
113		/* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
114		if (p->flags & IIC_M_RD) {
115			max_bytes = ATOM_MAX_HW_I2C_READ;
116			flags = HW_I2C_READ;
117		} else {
118			max_bytes = ATOM_MAX_HW_I2C_WRITE;
119			flags = HW_I2C_WRITE;
120		}
121		while (remaining) {
122			if (remaining > max_bytes)
123				current_count = max_bytes;
124			else
125				current_count = remaining;
126			ret = radeon_process_i2c_ch(i2c,
127						    p->slave, flags,
128						    &p->buf[buffer_offset], current_count);
129			if (ret)
130				return ret;
131			remaining -= current_count;
132			buffer_offset += current_count;
133		}
134	}
135
136	return (0);
137}
138
139static int
140radeon_atom_hw_i2c_probe(device_t dev)
141{
142
143	return (BUS_PROBE_SPECIFIC);
144}
145
146static int
147radeon_atom_hw_i2c_attach(device_t dev)
148{
149	struct radeon_i2c_chan *i2c;
150	device_t iic_dev;
151
152	i2c = device_get_softc(dev);
153	device_set_desc(dev, i2c->name);
154
155	/* add generic bit-banging code */
156	iic_dev = device_add_child(dev, "iicbus", -1);
157	if (iic_dev == NULL)
158		return (ENXIO);
159	device_quiet(iic_dev);
160
161	/* attach and probe added child */
162	bus_generic_attach(dev);
163
164	return (0);
165}
166
167static int
168radeon_atom_hw_i2c_detach(device_t dev)
169{
170	/* detach bit-banding code. */
171	bus_generic_detach(dev);
172
173	/* delete bit-banding code. */
174	device_delete_children(dev);
175	return (0);
176}
177
178static int
179radeon_atom_hw_i2c_reset(device_t dev, u_char speed,
180    u_char addr, u_char *oldaddr)
181{
182
183	return (0);
184}
185
186static device_method_t radeon_atom_hw_i2c_methods[] = {
187	DEVMETHOD(device_probe,		radeon_atom_hw_i2c_probe),
188	DEVMETHOD(device_attach,	radeon_atom_hw_i2c_attach),
189	DEVMETHOD(device_detach,	radeon_atom_hw_i2c_detach),
190	DEVMETHOD(iicbus_reset,		radeon_atom_hw_i2c_reset),
191	DEVMETHOD(iicbus_transfer,	radeon_atom_hw_i2c_xfer),
192	DEVMETHOD_END
193};
194
195static driver_t radeon_atom_hw_i2c_driver = {
196	"radeon_atom_hw_i2c",
197	radeon_atom_hw_i2c_methods,
198	0
199};
200
201static devclass_t radeon_atom_hw_i2c_devclass;
202DRIVER_MODULE_ORDERED(radeon_atom_hw_i2c, drmn, radeon_atom_hw_i2c_driver,
203    radeon_atom_hw_i2c_devclass, 0, 0, SI_ORDER_ANY);
204