1/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*- 2 * Created: Thu Nov 30 20:04:32 2000 by gareth@valinux.com 3 */ 4/*- 5 * Copyright 2000 Gareth Hughes 6 * Copyright 2002 Frank C. Earl 7 * Copyright 2002-2003 Leif Delgass 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the "Software"), 12 * to deal in the Software without restriction, including without limitation 13 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 14 * and/or sell copies of the Software, and to permit persons to whom the 15 * Software is furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice (including the next 18 * paragraph) shall be included in all copies or substantial portions of the 19 * Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 25 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 26 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Gareth Hughes <gareth@valinux.com> 30 * Frank C. Earl <fearl@airmail.net> 31 * Leif Delgass <ldelgass@retinalburn.net> 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD$"); 36 37#ifndef __MACH64_DRM_H__ 38#define __MACH64_DRM_H__ 39 40/* WARNING: If you change any of these defines, make sure to change the 41 * defines in the Xserver file (mach64_sarea.h) 42 */ 43#ifndef __MACH64_SAREA_DEFINES__ 44#define __MACH64_SAREA_DEFINES__ 45 46/* What needs to be changed for the current vertex buffer? 47 * GH: We're going to be pedantic about this. We want the card to do as 48 * little as possible, so let's avoid having it fetch a whole bunch of 49 * register values that don't change all that often, if at all. 50 */ 51#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001 52#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002 53#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004 54#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008 55#define MACH64_UPLOAD_DP_FOG_CLR 0x0010 56#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020 57#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040 58#define MACH64_UPLOAD_SETUP_CNTL 0x0080 59#define MACH64_UPLOAD_MISC 0x0100 60#define MACH64_UPLOAD_TEXTURE 0x0200 61#define MACH64_UPLOAD_TEX0IMAGE 0x0400 62#define MACH64_UPLOAD_TEX1IMAGE 0x0800 63#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */ 64#define MACH64_UPLOAD_CONTEXT 0x00ff 65#define MACH64_UPLOAD_ALL 0x1fff 66 67/* DMA buffer size 68 */ 69#define MACH64_BUFFER_SIZE 16384 70 71/* Max number of swaps allowed on the ring 72 * before the client must wait 73 */ 74#define MACH64_MAX_QUEUED_FRAMES 3U 75 76/* Byte offsets for host blit buffer data 77 */ 78#define MACH64_HOSTDATA_BLIT_OFFSET 104 79 80/* Keep these small for testing. 81 */ 82#define MACH64_NR_SAREA_CLIPRECTS 8 83 84#define MACH64_CARD_HEAP 0 85#define MACH64_AGP_HEAP 1 86#define MACH64_NR_TEX_HEAPS 2 87#define MACH64_NR_TEX_REGIONS 64 88#define MACH64_LOG_TEX_GRANULARITY 16 89 90#define MACH64_TEX_MAXLEVELS 1 91 92#define MACH64_NR_CONTEXT_REGS 15 93#define MACH64_NR_TEXTURE_REGS 4 94 95#endif /* __MACH64_SAREA_DEFINES__ */ 96 97typedef struct { 98 unsigned int dst_off_pitch; 99 100 unsigned int z_off_pitch; 101 unsigned int z_cntl; 102 unsigned int alpha_tst_cntl; 103 104 unsigned int scale_3d_cntl; 105 106 unsigned int sc_left_right; 107 unsigned int sc_top_bottom; 108 109 unsigned int dp_fog_clr; 110 unsigned int dp_write_mask; 111 unsigned int dp_pix_width; 112 unsigned int dp_mix; 113 unsigned int dp_src; 114 115 unsigned int clr_cmp_cntl; 116 unsigned int gui_traj_cntl; 117 118 unsigned int setup_cntl; 119 120 unsigned int tex_size_pitch; 121 unsigned int tex_cntl; 122 unsigned int secondary_tex_off; 123 unsigned int tex_offset; 124} drm_mach64_context_regs_t; 125 126typedef struct drm_mach64_sarea { 127 /* The channel for communication of state information to the kernel 128 * on firing a vertex dma buffer. 129 */ 130 drm_mach64_context_regs_t context_state; 131 unsigned int dirty; 132 unsigned int vertsize; 133 134 /* The current cliprects, or a subset thereof. 135 */ 136 struct drm_clip_rect boxes[MACH64_NR_SAREA_CLIPRECTS]; 137 unsigned int nbox; 138 139 /* Counters for client-side throttling of rendering clients. 140 */ 141 unsigned int frames_queued; 142 143 /* Texture memory LRU. 144 */ 145 struct drm_tex_region tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS + 146 1]; 147 unsigned int tex_age[MACH64_NR_TEX_HEAPS]; 148 int ctx_owner; 149} drm_mach64_sarea_t; 150 151/* WARNING: If you change any of these defines, make sure to change the 152 * defines in the Xserver file (mach64_common.h) 153 */ 154 155/* Mach64 specific ioctls 156 * The device specific ioctl range is 0x40 to 0x79. 157 */ 158 159#define DRM_MACH64_INIT 0x00 160#define DRM_MACH64_IDLE 0x01 161#define DRM_MACH64_RESET 0x02 162#define DRM_MACH64_SWAP 0x03 163#define DRM_MACH64_CLEAR 0x04 164#define DRM_MACH64_VERTEX 0x05 165#define DRM_MACH64_BLIT 0x06 166#define DRM_MACH64_FLUSH 0x07 167#define DRM_MACH64_GETPARAM 0x08 168 169#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t) 170#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE ) 171#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET ) 172#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP ) 173#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t) 174#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t) 175#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t) 176#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH ) 177#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t) 178 179/* Buffer flags for clears 180 */ 181#define MACH64_FRONT 0x1 182#define MACH64_BACK 0x2 183#define MACH64_DEPTH 0x4 184 185/* Primitive types for vertex buffers 186 */ 187#define MACH64_PRIM_POINTS 0x00000000 188#define MACH64_PRIM_LINES 0x00000001 189#define MACH64_PRIM_LINE_LOOP 0x00000002 190#define MACH64_PRIM_LINE_STRIP 0x00000003 191#define MACH64_PRIM_TRIANGLES 0x00000004 192#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005 193#define MACH64_PRIM_TRIANGLE_FAN 0x00000006 194#define MACH64_PRIM_QUADS 0x00000007 195#define MACH64_PRIM_QUAD_STRIP 0x00000008 196#define MACH64_PRIM_POLYGON 0x00000009 197 198typedef enum _drm_mach64_dma_mode_t { 199 MACH64_MODE_DMA_ASYNC, 200 MACH64_MODE_DMA_SYNC, 201 MACH64_MODE_MMIO 202} drm_mach64_dma_mode_t; 203 204typedef struct drm_mach64_init { 205 enum { 206 DRM_MACH64_INIT_DMA = 0x01, 207 DRM_MACH64_CLEANUP_DMA = 0x02 208 } func; 209 210 unsigned long sarea_priv_offset; 211 int is_pci; 212 drm_mach64_dma_mode_t dma_mode; 213 214 unsigned int fb_bpp; 215 unsigned int front_offset, front_pitch; 216 unsigned int back_offset, back_pitch; 217 218 unsigned int depth_bpp; 219 unsigned int depth_offset, depth_pitch; 220 221 unsigned long fb_offset; 222 unsigned long mmio_offset; 223 unsigned long ring_offset; 224 unsigned long buffers_offset; 225 unsigned long agp_textures_offset; 226} drm_mach64_init_t; 227 228typedef struct drm_mach64_clear { 229 unsigned int flags; 230 int x, y, w, h; 231 unsigned int clear_color; 232 unsigned int clear_depth; 233} drm_mach64_clear_t; 234 235typedef struct drm_mach64_vertex { 236 int prim; 237 void *buf; /* Address of vertex buffer */ 238 unsigned long used; /* Number of bytes in buffer */ 239 int discard; /* Client finished with buffer? */ 240} drm_mach64_vertex_t; 241 242typedef struct drm_mach64_blit { 243 void *buf; 244 int pitch; 245 int offset; 246 int format; 247 unsigned short x, y; 248 unsigned short width, height; 249} drm_mach64_blit_t; 250 251typedef struct drm_mach64_getparam { 252 enum { 253 MACH64_PARAM_FRAMES_QUEUED = 0x01, 254 MACH64_PARAM_IRQ_NR = 0x02 255 } param; 256 void *value; 257} drm_mach64_getparam_t; 258 259#endif 260