1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer,
10 *    without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 *    redistribution must be conditioned upon including a substantially
14 *    similar Disclaimer requirement for further binary redistribution.
15 *
16 * NO WARRANTY
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 *
29 * $FreeBSD$
30 */
31#ifndef	__IF_ATH_DEBUG_H__
32#define	__IF_ATH_DEBUG_H__
33
34#ifdef	ATH_DEBUG
35
36enum {
37	ATH_DEBUG_XMIT		= 0x000000001ULL,	/* basic xmit operation */
38	ATH_DEBUG_XMIT_DESC	= 0x000000002ULL,	/* xmit descriptors */
39	ATH_DEBUG_RECV		= 0x000000004ULL,	/* basic recv operation */
40	ATH_DEBUG_RECV_DESC	= 0x000000008ULL,	/* recv descriptors */
41	ATH_DEBUG_RATE		= 0x000000010ULL,	/* rate control */
42	ATH_DEBUG_RESET		= 0x000000020ULL,	/* reset processing */
43	ATH_DEBUG_MODE		= 0x000000040ULL,	/* mode init/setup */
44	ATH_DEBUG_BEACON	= 0x000000080ULL,	/* beacon handling */
45	ATH_DEBUG_WATCHDOG	= 0x000000100ULL,	/* watchdog timeout */
46	ATH_DEBUG_INTR		= 0x000001000ULL,	/* ISR */
47	ATH_DEBUG_TX_PROC	= 0x000002000ULL,	/* tx ISR proc */
48	ATH_DEBUG_RX_PROC	= 0x000004000ULL,	/* rx ISR proc */
49	ATH_DEBUG_BEACON_PROC	= 0x000008000ULL,	/* beacon ISR proc */
50	ATH_DEBUG_CALIBRATE	= 0x000010000ULL,	/* periodic calibration */
51	ATH_DEBUG_KEYCACHE	= 0x000020000ULL,	/* key cache management */
52	ATH_DEBUG_STATE		= 0x000040000ULL,	/* 802.11 state transitions */
53	ATH_DEBUG_NODE		= 0x000080000ULL,	/* node management */
54	ATH_DEBUG_LED		= 0x000100000ULL,	/* led management */
55	ATH_DEBUG_FF		= 0x000200000ULL,	/* fast frames */
56	ATH_DEBUG_DFS		= 0x000400000ULL,	/* DFS processing */
57	ATH_DEBUG_TDMA		= 0x000800000ULL,	/* TDMA processing */
58	ATH_DEBUG_TDMA_TIMER	= 0x001000000ULL,	/* TDMA timer processing */
59	ATH_DEBUG_REGDOMAIN	= 0x002000000ULL,	/* regulatory processing */
60	ATH_DEBUG_SW_TX		= 0x004000000ULL,	/* per-packet software TX */
61	ATH_DEBUG_SW_TX_BAW	= 0x008000000ULL,	/* BAW handling */
62	ATH_DEBUG_SW_TX_CTRL	= 0x010000000ULL,	/* queue control */
63	ATH_DEBUG_SW_TX_AGGR	= 0x020000000ULL,	/* aggregate TX */
64	ATH_DEBUG_SW_TX_RETRIES	= 0x040000000ULL,	/* software TX retries */
65	ATH_DEBUG_FATAL		= 0x080000000ULL,	/* fatal errors */
66	ATH_DEBUG_SW_TX_BAR	= 0x100000000ULL,	/* BAR TX */
67	ATH_DEBUG_EDMA_RX	= 0x200000000ULL,	/* RX EDMA state */
68	ATH_DEBUG_SW_TX_FILT	= 0x400000000ULL,	/* SW TX FF */
69	ATH_DEBUG_NODE_PWRSAVE	= 0x800000000ULL,	/* node powersave */
70	ATH_DEBUG_DIVERSITY	= 0x1000000000ULL,	/* Diversity logic */
71
72	ATH_DEBUG_ANY		= 0xffffffffffffffffULL
73};
74
75enum {
76	ATH_KTR_RXPROC		= 0x00000001,
77	ATH_KTR_TXPROC		= 0x00000002,
78	ATH_KTR_TXCOMP		= 0x00000004,
79	ATH_KTR_SWQ		= 0x00000008,
80	ATH_KTR_INTERRUPTS	= 0x00000010,
81	ATH_KTR_ERROR		= 0x00000020,
82	ATH_KTR_NODE		= 0x00000040,
83	ATH_KTR_TX		= 0x00000080,
84};
85
86#define	ATH_KTR(_sc, _km, _kf, ...)	do {	\
87	if (sc->sc_ktrdebug & (_km))		\
88		CTR##_kf(KTR_DEV, __VA_ARGS__);	\
89	} while (0)
90
91extern uint64_t ath_debug;
92
93#define	IFF_DUMPPKTS(sc, m) \
94	((sc->sc_debug & (m)) || \
95	    (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
96#define	DPRINTF(sc, m, fmt, ...) do {				\
97	if (sc->sc_debug & (m))					\
98		device_printf(sc->sc_dev, fmt, __VA_ARGS__);		\
99} while (0)
100#define	KEYPRINTF(sc, ix, hk, mac) do {				\
101	if (sc->sc_debug & ATH_DEBUG_KEYCACHE)			\
102		ath_keyprint(sc, __func__, ix, hk, mac);	\
103} while (0)
104
105extern	void ath_printrxbuf(struct ath_softc *, const struct ath_buf *bf,
106	u_int ix, int);
107extern	void ath_printtxbuf(struct ath_softc *, const struct ath_buf *bf,
108	u_int qnum, u_int ix, int done);
109extern	void ath_printtxstatbuf(struct ath_softc *sc, const struct ath_buf *bf,
110	const uint32_t *ds, u_int qnum, u_int ix, int done);
111#else	/* ATH_DEBUG */
112#define	ATH_KTR(_sc, _km, _kf, ...)	do { } while (0)
113
114#define	IFF_DUMPPKTS(sc, m) \
115	((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
116#define	DPRINTF(sc, m, fmt, ...) do {				\
117	(void) sc;						\
118} while (0)
119#define	KEYPRINTF(sc, k, ix, mac) do {				\
120	(void) sc;						\
121} while (0)
122#endif	/* ATH_DEBUG */
123
124#endif
125