1/*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/module.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/ata.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/malloc.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/sema.h> 41#include <sys/taskqueue.h> 42#include <vm/uma.h> 43#include <machine/stdarg.h> 44#include <machine/resource.h> 45#include <machine/bus.h> 46#include <sys/rman.h> 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/ata/ata-all.h> 50#include <dev/ata/ata-pci.h> 51#include <ata_if.h> 52 53/* local prototypes */ 54static int ata_intel_chipinit(device_t dev); 55static int ata_intel_chipdeinit(device_t dev); 56static int ata_intel_ch_attach(device_t dev); 57static void ata_intel_reset(device_t dev); 58static int ata_intel_old_setmode(device_t dev, int target, int mode); 59static int ata_intel_new_setmode(device_t dev, int target, int mode); 60static int ata_intel_sch_setmode(device_t dev, int target, int mode); 61static int ata_intel_sata_getrev(device_t dev, int target); 62static int ata_intel_sata_status(device_t dev); 63static int ata_intel_sata_ahci_read(device_t dev, int port, 64 int reg, u_int32_t *result); 65static int ata_intel_sata_cscr_read(device_t dev, int port, 66 int reg, u_int32_t *result); 67static int ata_intel_sata_sidpr_read(device_t dev, int port, 68 int reg, u_int32_t *result); 69static int ata_intel_sata_ahci_write(device_t dev, int port, 70 int reg, u_int32_t result); 71static int ata_intel_sata_cscr_write(device_t dev, int port, 72 int reg, u_int32_t result); 73static int ata_intel_sata_sidpr_write(device_t dev, int port, 74 int reg, u_int32_t result); 75static int ata_intel_sata_sidpr_test(device_t dev); 76static int ata_intel_31244_ch_attach(device_t dev); 77static int ata_intel_31244_ch_detach(device_t dev); 78static int ata_intel_31244_status(device_t dev); 79static void ata_intel_31244_tf_write(struct ata_request *request); 80static void ata_intel_31244_reset(device_t dev); 81 82/* misc defines */ 83#define INTEL_AHCI 1 84#define INTEL_ICH5 2 85#define INTEL_6CH 4 86#define INTEL_6CH2 8 87#define INTEL_ICH7 16 88 89struct ata_intel_data { 90 struct mtx lock; 91 u_char smap[4]; 92}; 93 94#define ATA_INTEL_SMAP(ctlr, ch) \ 95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2] 96#define ATA_INTEL_LOCK(ctlr) \ 97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 98#define ATA_INTEL_UNLOCK(ctlr) \ 99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock) 100 101/* 102 * Intel chipset support functions 103 */ 104static int 105ata_intel_probe(device_t dev) 106{ 107 struct ata_pci_controller *ctlr = device_get_softc(dev); 108 static const struct ata_chip_id ids[] = 109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" }, 110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" }, 111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" }, 114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" }, 115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" }, 116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" }, 117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" }, 118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" }, 119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" }, 120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" }, 121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" }, 122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" }, 123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" }, 124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" }, 126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" }, 127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" }, 129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" }, 130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" }, 132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" }, 133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" }, 134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" }, 135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" }, 137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" }, 138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" }, 140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" }, 141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" }, 142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" }, 145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" }, 146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" }, 147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" }, 150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" }, 151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" }, 152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" }, 154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" }, 155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" }, 157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" }, 160 { ATA_I82801IBM_S1, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 161 { ATA_I82801IBM_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 162 { ATA_I82801IBM_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9M" }, 163 { ATA_I82801IBM_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9M" }, 164 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 165 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 166 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 167 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 168 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 169 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 170 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 171 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 172 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" }, 173 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 174 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" }, 175 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" }, 176 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 177 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 178 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 179 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 180 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 181 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 182 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 183 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 184 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 185 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 186 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 187 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" }, 188 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 189 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" }, 190 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 191 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 192 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 193 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" }, 194 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 195 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" }, 196 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" }, 197 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 198 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 199 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 200 { ATA_PBG_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" }, 201 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" }, 202 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 203 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" }, 204 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 205 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 206 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 207 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 208 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 209 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 210 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 211 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" }, 212 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 213 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" }, 214 { ATA_AVOTON_S1, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, 215 { ATA_AVOTON_S2, 0, INTEL_6CH, 0, ATA_SA300, "Avoton" }, 216 { ATA_AVOTON_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 217 { ATA_AVOTON_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Avoton" }, 218 { ATA_LPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 219 { ATA_LPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point" }, 220 { ATA_LPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 221 { ATA_LPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 222 { ATA_LPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 223 { ATA_LPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 224 { ATA_LPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 225 { ATA_LPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 226 { ATA_LPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 227 { ATA_LPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point" }, 228 { ATA_LPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 229 { ATA_LPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Lynx Point" }, 230 { ATA_WELLS_S1, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, 231 { ATA_WELLS_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, 232 { ATA_WELLS_S3, 0, INTEL_6CH, 0, ATA_SA300, "Wellsburg" }, 233 { ATA_WELLS_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Wellsburg" }, 234 { ATA_LPTLP_S1, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, 235 { ATA_LPTLP_S2, 0, INTEL_6CH, 0, ATA_SA300, "Lynx Point-LP" }, 236 { ATA_LPTLP_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 237 { ATA_LPTLP_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Lynx Point-LP" }, 238 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" }, 239 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" }, 240 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" }, 241 { ATA_COLETOCRK_S1, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 242 { ATA_COLETOCRK_S2, 0, INTEL_6CH2, 0, ATA_SA300, "COLETOCRK" }, 243 { ATA_COLETOCRK_AH1,0, INTEL_AHCI, 0, ATA_SA300, "COLETOCRK" }, 244 { 0, 0, 0, 0, 0, 0}}; 245 246 if (pci_get_vendor(dev) != ATA_INTEL_ID) 247 return ENXIO; 248 249 if (!(ctlr->chip = ata_match_chip(dev, ids))) 250 return ENXIO; 251 252 ata_set_desc(dev); 253 ctlr->chipinit = ata_intel_chipinit; 254 ctlr->chipdeinit = ata_intel_chipdeinit; 255 return (BUS_PROBE_DEFAULT); 256} 257 258static int 259ata_intel_chipinit(device_t dev) 260{ 261 struct ata_pci_controller *ctlr = device_get_softc(dev); 262 struct ata_intel_data *data; 263 264 if (ata_setup_interrupt(dev, ata_generic_intr)) 265 return ENXIO; 266 267 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO); 268 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF); 269 ctlr->chipset_data = (void *)data; 270 271 /* good old PIIX needs special treatment (not implemented) */ 272 if (ctlr->chip->chipid == ATA_I82371FB) { 273 ctlr->setmode = ata_intel_old_setmode; 274 } 275 276 /* the intel 31244 needs special care if in DPA mode */ 277 else if (ctlr->chip->chipid == ATA_I31244) { 278 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) { 279 ctlr->r_type2 = SYS_RES_MEMORY; 280 ctlr->r_rid2 = PCIR_BAR(0); 281 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 282 &ctlr->r_rid2, 283 RF_ACTIVE))) 284 return ENXIO; 285 ctlr->channels = 4; 286 ctlr->ch_attach = ata_intel_31244_ch_attach; 287 ctlr->ch_detach = ata_intel_31244_ch_detach; 288 ctlr->reset = ata_intel_31244_reset; 289 } 290 ctlr->setmode = ata_sata_setmode; 291 ctlr->getrev = ata_sata_getrev; 292 } 293 /* SCH */ 294 else if (ctlr->chip->chipid == ATA_ISCH) { 295 ctlr->channels = 1; 296 ctlr->ch_attach = ata_intel_ch_attach; 297 ctlr->ch_detach = ata_pci_ch_detach; 298 ctlr->setmode = ata_intel_sch_setmode; 299 } 300 /* non SATA intel chips goes here */ 301 else if (ctlr->chip->max_dma < ATA_SA150) { 302 ctlr->channels = ctlr->chip->cfg2; 303 ctlr->ch_attach = ata_intel_ch_attach; 304 ctlr->ch_detach = ata_pci_ch_detach; 305 ctlr->setmode = ata_intel_new_setmode; 306 } 307 308 /* SATA parts can be either compat or AHCI */ 309 else { 310 /* force all ports active "the legacy way" */ 311 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2); 312 313 ctlr->ch_attach = ata_intel_ch_attach; 314 ctlr->ch_detach = ata_pci_ch_detach; 315 ctlr->reset = ata_intel_reset; 316 317 /* 318 * if we have AHCI capability and AHCI or RAID mode enabled 319 * in BIOS we try for AHCI mode 320 */ 321 if ((ctlr->chip->cfg1 & INTEL_AHCI) && 322 (pci_read_config(dev, 0x90, 1) & 0xc0) && 323 (ata_ahci_chipinit(dev) != ENXIO)) 324 return 0; 325 326 /* BAR(5) may point to SATA interface registers */ 327 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 328 ctlr->r_type2 = SYS_RES_MEMORY; 329 ctlr->r_rid2 = PCIR_BAR(5); 330 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 331 &ctlr->r_rid2, RF_ACTIVE); 332 if (ctlr->r_res2 != NULL) { 333 /* Set SCRAE bit to enable registers access. */ 334 pci_write_config(dev, 0x94, 335 pci_read_config(dev, 0x94, 4) | (1 << 9), 4); 336 /* Set Ports Implemented register bits. */ 337 ATA_OUTL(ctlr->r_res2, 0x0C, 338 ATA_INL(ctlr->r_res2, 0x0C) | 0xf); 339 } 340 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */ 341 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 || 342 pci_get_subvendor(dev) != 0x106b) { 343 ctlr->r_type2 = SYS_RES_IOPORT; 344 ctlr->r_rid2 = PCIR_BAR(5); 345 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 346 &ctlr->r_rid2, RF_ACTIVE); 347 } 348 if (ctlr->r_res2 != NULL || 349 (ctlr->chip->cfg1 & INTEL_ICH5)) 350 ctlr->getrev = ata_intel_sata_getrev; 351 ctlr->setmode = ata_sata_setmode; 352 } 353 return 0; 354} 355 356static int 357ata_intel_chipdeinit(device_t dev) 358{ 359 struct ata_pci_controller *ctlr = device_get_softc(dev); 360 struct ata_intel_data *data; 361 362 data = ctlr->chipset_data; 363 mtx_destroy(&data->lock); 364 free(data, M_ATAPCI); 365 ctlr->chipset_data = NULL; 366 return (0); 367} 368 369static int 370ata_intel_ch_attach(device_t dev) 371{ 372 struct ata_pci_controller *ctlr; 373 struct ata_channel *ch; 374 u_char *smap; 375 u_int map; 376 377 /* setup the usual register normal pci style */ 378 if (ata_pci_ch_attach(dev)) 379 return (ENXIO); 380 381 ctlr = device_get_softc(device_get_parent(dev)); 382 ch = device_get_softc(dev); 383 384 /* if r_res2 is valid it points to SATA interface registers */ 385 if (ctlr->r_res2) { 386 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 387 ch->r_io[ATA_IDX_ADDR].offset = 0x00; 388 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2; 389 ch->r_io[ATA_IDX_DATA].offset = 0x04; 390 } 391 392 ch->flags |= ATA_ALWAYS_DMASTAT; 393 if (ctlr->chip->max_dma >= ATA_SA150) { 394 smap = ATA_INTEL_SMAP(ctlr, ch); 395 map = pci_read_config(device_get_parent(dev), 0x90, 1); 396 if (ctlr->chip->cfg1 & INTEL_ICH5) { 397 map &= 0x07; 398 if ((map & 0x04) == 0) { 399 ch->flags |= ATA_SATA; 400 ch->flags |= ATA_NO_SLAVE; 401 smap[0] = (map & 0x01) ^ ch->unit; 402 smap[1] = 0; 403 } else if ((map & 0x02) == 0 && ch->unit == 0) { 404 ch->flags |= ATA_SATA; 405 smap[0] = (map & 0x01) ? 1 : 0; 406 smap[1] = (map & 0x01) ? 0 : 1; 407 } else if ((map & 0x02) != 0 && ch->unit == 1) { 408 ch->flags |= ATA_SATA; 409 smap[0] = (map & 0x01) ? 1 : 0; 410 smap[1] = (map & 0x01) ? 0 : 1; 411 } 412 } else if (ctlr->chip->cfg1 & INTEL_6CH2) { 413 ch->flags |= ATA_SATA; 414 ch->flags |= ATA_NO_SLAVE; 415 smap[0] = (ch->unit == 0) ? 0 : 1; 416 smap[1] = 0; 417 } else { 418 map &= 0x03; 419 if (map == 0x00) { 420 ch->flags |= ATA_SATA; 421 smap[0] = (ch->unit == 0) ? 0 : 1; 422 smap[1] = (ch->unit == 0) ? 2 : 3; 423 } else if (map == 0x02 && ch->unit == 0) { 424 ch->flags |= ATA_SATA; 425 smap[0] = 0; 426 smap[1] = 2; 427 } else if (map == 0x01 && ch->unit == 1) { 428 ch->flags |= ATA_SATA; 429 smap[0] = 1; 430 smap[1] = 3; 431 } 432 } 433 if (ch->flags & ATA_SATA) { 434 if ((ctlr->chip->cfg1 & INTEL_ICH5)) { 435 ch->hw.pm_read = ata_intel_sata_cscr_read; 436 ch->hw.pm_write = ata_intel_sata_cscr_write; 437 } else if (ctlr->r_res2) { 438 if ((ctlr->chip->cfg1 & INTEL_ICH7)) { 439 ch->hw.pm_read = ata_intel_sata_ahci_read; 440 ch->hw.pm_write = ata_intel_sata_ahci_write; 441 } else if (ata_intel_sata_sidpr_test(dev)) { 442 ch->hw.pm_read = ata_intel_sata_sidpr_read; 443 ch->hw.pm_write = ata_intel_sata_sidpr_write; 444 }; 445 } 446 if (ch->hw.pm_write != NULL) { 447 ch->flags |= ATA_PERIODIC_POLL; 448 ch->hw.status = ata_intel_sata_status; 449 ata_sata_scr_write(ch, 0, 450 ATA_SERROR, 0xffffffff); 451 if ((ch->flags & ATA_NO_SLAVE) == 0) { 452 ata_sata_scr_write(ch, 1, 453 ATA_SERROR, 0xffffffff); 454 } 455 } 456 } else 457 ctlr->setmode = ata_intel_new_setmode; 458 } else if (ctlr->chip->chipid != ATA_ISCH) 459 ch->flags |= ATA_CHECKS_CABLE; 460 return (0); 461} 462 463static void 464ata_intel_reset(device_t dev) 465{ 466 device_t parent = device_get_parent(dev); 467 struct ata_pci_controller *ctlr = device_get_softc(parent); 468 struct ata_channel *ch = device_get_softc(dev); 469 int mask, pshift, timeout, devs; 470 u_char *smap; 471 uint16_t pcs; 472 473 /* In combined mode, skip SATA stuff for PATA channel. */ 474 if ((ch->flags & ATA_SATA) == 0) 475 return (ata_generic_reset(dev)); 476 477 /* Do hard-reset on respective SATA ports. */ 478 smap = ATA_INTEL_SMAP(ctlr, ch); 479 mask = 1 << smap[0]; 480 if ((ch->flags & ATA_NO_SLAVE) == 0) 481 mask |= (1 << smap[1]); 482 pci_write_config(parent, 0x92, 483 pci_read_config(parent, 0x92, 2) & ~mask, 2); 484 DELAY(10); 485 pci_write_config(parent, 0x92, 486 pci_read_config(parent, 0x92, 2) | mask, 2); 487 488 /* Wait up to 1 sec for "connect well". */ 489 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2)) 490 pshift = 8; 491 else 492 pshift = 4; 493 for (timeout = 0; timeout < 100 ; timeout++) { 494 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask; 495 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff)) 496 break; 497 ata_udelay(10000); 498 } 499 500 if (bootverbose) 501 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs); 502 /* If any device found, do soft-reset. */ 503 if (ch->hw.pm_read != NULL) { 504 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0; 505 if ((ch->flags & ATA_NO_SLAVE) == 0) 506 devs |= ata_sata_phy_reset(dev, 1, 2) ? 507 ATA_ATA_SLAVE : 0; 508 } else { 509 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0; 510 if ((ch->flags & ATA_NO_SLAVE) == 0) 511 devs |= (pcs & (1 << smap[1])) ? 512 ATA_ATA_SLAVE : 0; 513 } 514 if (devs) { 515 ata_generic_reset(dev); 516 /* Reset may give fake slave when only ATAPI master present. */ 517 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER)); 518 } else 519 ch->devices = 0; 520} 521 522static int 523ata_intel_old_setmode(device_t dev, int target, int mode) 524{ 525 device_t parent = device_get_parent(dev); 526 struct ata_pci_controller *ctlr = device_get_softc(parent); 527 528 mode = min(mode, ctlr->chip->max_dma); 529 return (mode); 530} 531 532static int 533ata_intel_new_setmode(device_t dev, int target, int mode) 534{ 535 device_t parent = device_get_parent(dev); 536 struct ata_pci_controller *ctlr = device_get_softc(parent); 537 struct ata_channel *ch = device_get_softc(dev); 538 int devno = (ch->unit << 1) + target; 539 int piomode; 540 u_int32_t reg40 = pci_read_config(parent, 0x40, 4); 541 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 542 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 543 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 544 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 545 u_int32_t mask40 = 0, new40 = 0; 546 u_int8_t mask44 = 0, new44 = 0; 547 static const uint8_t timings[] = 548 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 549 static const uint8_t utimings[] = 550 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 551 552 /* In combined mode, skip PATA stuff for SATA channel. */ 553 if (ch->flags & ATA_SATA) 554 return (ata_sata_setmode(dev, target, mode)); 555 556 mode = min(mode, ctlr->chip->max_dma); 557 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 558 !(reg54 & (0x10 << devno))) { 559 ata_print_cable(dev, "controller"); 560 mode = ATA_UDMA2; 561 } 562 /* Enable/disable UDMA and set timings. */ 563 if (mode >= ATA_UDMA0) { 564 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2); 565 pci_write_config(parent, 0x4a, 566 (reg4a & ~(0x3 << (devno << 2))) | 567 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2); 568 piomode = ATA_PIO4; 569 } else { 570 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2); 571 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2); 572 piomode = mode; 573 } 574 reg54 |= 0x0400; 575 /* Set UDMA reference clock (33/66/133MHz). */ 576 reg54 &= ~(0x1001 << devno); 577 if (mode >= ATA_UDMA5) 578 reg54 |= (0x1000 << devno); 579 else if (mode >= ATA_UDMA3) 580 reg54 |= (0x1 << devno); 581 pci_write_config(parent, 0x54, reg54, 2); 582 /* Allow PIO/WDMA timing controls. */ 583 reg40 &= ~0x00ff00ff; 584 reg40 |= 0x40774077; 585 /* Set PIO/WDMA timings. */ 586 if (target == 0) { 587 mask40 = 0x3300; 588 new40 = timings[ata_mode2idx(piomode)] << 8; 589 } else { 590 mask44 = 0x0f; 591 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 592 (timings[ata_mode2idx(piomode)] & 0x03); 593 } 594 if (ch->unit) { 595 mask40 <<= 16; 596 new40 <<= 16; 597 mask44 <<= 4; 598 new44 <<= 4; 599 } 600 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 601 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 602 return (mode); 603} 604 605static int 606ata_intel_sch_setmode(device_t dev, int target, int mode) 607{ 608 device_t parent = device_get_parent(dev); 609 struct ata_pci_controller *ctlr = device_get_softc(parent); 610 u_int8_t dtim = 0x80 + (target << 2); 611 u_int32_t tim = pci_read_config(parent, dtim, 4); 612 int piomode; 613 614 mode = min(mode, ctlr->chip->max_dma); 615 if (mode >= ATA_UDMA0) { 616 tim |= (0x1 << 31); 617 tim &= ~(0x7 << 16); 618 tim |= ((mode & ATA_MODE_MASK) << 16); 619 piomode = ATA_PIO4; 620 } else if (mode >= ATA_WDMA0) { 621 tim &= ~(0x1 << 31); 622 tim &= ~(0x3 << 8); 623 tim |= ((mode & ATA_MODE_MASK) << 8); 624 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 625 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 626 } else 627 piomode = mode; 628 tim &= ~(0x7); 629 tim |= (piomode & 0x7); 630 pci_write_config(parent, dtim, tim, 4); 631 return (mode); 632} 633 634static int 635ata_intel_sata_getrev(device_t dev, int target) 636{ 637 struct ata_channel *ch = device_get_softc(dev); 638 uint32_t status; 639 640 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0) 641 return ((status & 0x0f0) >> 4); 642 return (0xff); 643} 644 645static int 646ata_intel_sata_status(device_t dev) 647{ 648 struct ata_channel *ch = device_get_softc(dev); 649 650 ata_sata_phy_check_events(dev, 0); 651 if ((ch->flags & ATA_NO_SLAVE) == 0) 652 ata_sata_phy_check_events(dev, 1); 653 654 return ata_pci_status(dev); 655} 656 657static int 658ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result) 659{ 660 struct ata_pci_controller *ctlr; 661 struct ata_channel *ch; 662 device_t parent; 663 u_char *smap; 664 int offset; 665 666 parent = device_get_parent(dev); 667 ctlr = device_get_softc(parent); 668 ch = device_get_softc(dev); 669 port = (port == 1) ? 1 : 0; 670 smap = ATA_INTEL_SMAP(ctlr, ch); 671 offset = 0x100 + smap[port] * 0x80; 672 switch (reg) { 673 case ATA_SSTATUS: 674 reg = 0x28; 675 break; 676 case ATA_SCONTROL: 677 reg = 0x2c; 678 break; 679 case ATA_SERROR: 680 reg = 0x30; 681 break; 682 default: 683 return (EINVAL); 684 } 685 *result = ATA_INL(ctlr->r_res2, offset + reg); 686 return (0); 687} 688 689static int 690ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result) 691{ 692 struct ata_pci_controller *ctlr; 693 struct ata_channel *ch; 694 device_t parent; 695 u_char *smap; 696 697 parent = device_get_parent(dev); 698 ctlr = device_get_softc(parent); 699 ch = device_get_softc(dev); 700 smap = ATA_INTEL_SMAP(ctlr, ch); 701 port = (port == 1) ? 1 : 0; 702 switch (reg) { 703 case ATA_SSTATUS: 704 reg = 0; 705 break; 706 case ATA_SERROR: 707 reg = 1; 708 break; 709 case ATA_SCONTROL: 710 reg = 2; 711 break; 712 default: 713 return (EINVAL); 714 } 715 ATA_INTEL_LOCK(ctlr); 716 pci_write_config(parent, 0xa0, 717 0x50 + smap[port] * 0x10 + reg * 4, 4); 718 *result = pci_read_config(parent, 0xa4, 4); 719 ATA_INTEL_UNLOCK(ctlr); 720 return (0); 721} 722 723static int 724ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result) 725{ 726 struct ata_pci_controller *ctlr; 727 struct ata_channel *ch; 728 device_t parent; 729 730 parent = device_get_parent(dev); 731 ctlr = device_get_softc(parent); 732 ch = device_get_softc(dev); 733 port = (port == 1) ? 1 : 0; 734 switch (reg) { 735 case ATA_SSTATUS: 736 reg = 0; 737 break; 738 case ATA_SCONTROL: 739 reg = 1; 740 break; 741 case ATA_SERROR: 742 reg = 2; 743 break; 744 default: 745 return (EINVAL); 746 } 747 ATA_INTEL_LOCK(ctlr); 748 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 749 *result = ATA_IDX_INL(ch, ATA_IDX_DATA); 750 ATA_INTEL_UNLOCK(ctlr); 751 return (0); 752} 753 754static int 755ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value) 756{ 757 struct ata_pci_controller *ctlr; 758 struct ata_channel *ch; 759 device_t parent; 760 u_char *smap; 761 int offset; 762 763 parent = device_get_parent(dev); 764 ctlr = device_get_softc(parent); 765 ch = device_get_softc(dev); 766 port = (port == 1) ? 1 : 0; 767 smap = ATA_INTEL_SMAP(ctlr, ch); 768 offset = 0x100 + smap[port] * 0x80; 769 switch (reg) { 770 case ATA_SSTATUS: 771 reg = 0x28; 772 break; 773 case ATA_SCONTROL: 774 reg = 0x2c; 775 break; 776 case ATA_SERROR: 777 reg = 0x30; 778 break; 779 default: 780 return (EINVAL); 781 } 782 ATA_OUTL(ctlr->r_res2, offset + reg, value); 783 return (0); 784} 785 786static int 787ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value) 788{ 789 struct ata_pci_controller *ctlr; 790 struct ata_channel *ch; 791 device_t parent; 792 u_char *smap; 793 794 parent = device_get_parent(dev); 795 ctlr = device_get_softc(parent); 796 ch = device_get_softc(dev); 797 smap = ATA_INTEL_SMAP(ctlr, ch); 798 port = (port == 1) ? 1 : 0; 799 switch (reg) { 800 case ATA_SSTATUS: 801 reg = 0; 802 break; 803 case ATA_SERROR: 804 reg = 1; 805 break; 806 case ATA_SCONTROL: 807 reg = 2; 808 break; 809 default: 810 return (EINVAL); 811 } 812 ATA_INTEL_LOCK(ctlr); 813 pci_write_config(parent, 0xa0, 814 0x50 + smap[port] * 0x10 + reg * 4, 4); 815 pci_write_config(parent, 0xa4, value, 4); 816 ATA_INTEL_UNLOCK(ctlr); 817 return (0); 818} 819 820static int 821ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value) 822{ 823 struct ata_pci_controller *ctlr; 824 struct ata_channel *ch; 825 device_t parent; 826 827 parent = device_get_parent(dev); 828 ctlr = device_get_softc(parent); 829 ch = device_get_softc(dev); 830 port = (port == 1) ? 1 : 0; 831 switch (reg) { 832 case ATA_SSTATUS: 833 reg = 0; 834 break; 835 case ATA_SCONTROL: 836 reg = 1; 837 break; 838 case ATA_SERROR: 839 reg = 2; 840 break; 841 default: 842 return (EINVAL); 843 } 844 ATA_INTEL_LOCK(ctlr); 845 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg); 846 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value); 847 ATA_INTEL_UNLOCK(ctlr); 848 return (0); 849} 850 851static int 852ata_intel_sata_sidpr_test(device_t dev) 853{ 854 struct ata_channel *ch = device_get_softc(dev); 855 int port; 856 uint32_t val; 857 858 port = (ch->flags & ATA_NO_SLAVE) ? 0 : 1; 859 for (; port >= 0; port--) { 860 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 861 if ((val & ATA_SC_IPM_MASK) == 862 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 863 return (1); 864 val |= ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER; 865 ata_intel_sata_sidpr_write(dev, port, ATA_SCONTROL, val); 866 ata_intel_sata_sidpr_read(dev, port, ATA_SCONTROL, &val); 867 if ((val & ATA_SC_IPM_MASK) == 868 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)) 869 return (1); 870 } 871 if (bootverbose) 872 device_printf(dev, 873 "SControl registers are not functional: %08x\n", val); 874 return (0); 875} 876 877static int 878ata_intel_31244_ch_attach(device_t dev) 879{ 880 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 881 struct ata_channel *ch = device_get_softc(dev); 882 int i; 883 int ch_offset; 884 885 ata_pci_dmainit(dev); 886 887 ch_offset = 0x200 + ch->unit * 0x200; 888 889 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 890 ch->r_io[i].res = ctlr->r_res2; 891 892 /* setup ATA registers */ 893 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 894 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06; 895 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 896 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 897 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 898 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 899 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 900 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d; 901 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04; 902 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c; 903 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28; 904 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29; 905 906 /* setup DMA registers */ 907 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100; 908 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104; 909 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108; 910 911 /* setup SATA registers */ 912 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70; 913 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72; 914 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74; 915 916 ch->flags |= ATA_NO_SLAVE; 917 ch->flags |= ATA_SATA; 918 ata_pci_hw(dev); 919 ch->hw.status = ata_intel_31244_status; 920 ch->hw.tf_write = ata_intel_31244_tf_write; 921 922 /* enable PHY state change interrupt */ 923 ATA_OUTL(ctlr->r_res2, 0x4, 924 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3))); 925 return 0; 926} 927 928static int 929ata_intel_31244_ch_detach(device_t dev) 930{ 931 932 ata_pci_dmafini(dev); 933 return (0); 934} 935 936static int 937ata_intel_31244_status(device_t dev) 938{ 939 /* do we have any PHY events ? */ 940 ata_sata_phy_check_events(dev, -1); 941 942 /* any drive action to take care of ? */ 943 return ata_pci_status(dev); 944} 945 946static void 947ata_intel_31244_tf_write(struct ata_request *request) 948{ 949 struct ata_channel *ch = device_get_softc(request->parent); 950 951 if (request->flags & ATA_R_48BIT) { 952 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 953 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 954 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 955 (request->u.ata.lba & 0x00ff)); 956 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 957 ((request->u.ata.lba >> 8) & 0x00ff)); 958 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 959 ((request->u.ata.lba >> 16) & 0x00ff)); 960 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 961 } 962 else { 963 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature); 964 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count); 965 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba); 966 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 967 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 968 ATA_IDX_OUTB(ch, ATA_DRIVE, 969 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 970 ((request->u.ata.lba >> 24) & 0x0f)); 971 } 972} 973 974static void 975ata_intel_31244_reset(device_t dev) 976{ 977 struct ata_channel *ch = device_get_softc(dev); 978 979 if (ata_sata_phy_reset(dev, -1, 1)) 980 ata_generic_reset(dev); 981 else 982 ch->devices = 0; 983} 984 985ATA_DECLARE_DRIVER(ata_intel); 986MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1); 987