1/*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/malloc.h> 39#include <sys/mbuf.h> 40#include <sys/module.h> 41#include <sys/rman.h> 42#include <sys/queue.h> 43#include <sys/socket.h> 44#include <sys/sockio.h> 45#include <sys/sysctl.h> 46#include <sys/taskqueue.h> 47 48#include <net/bpf.h> 49#include <net/if.h> 50#include <net/if_arp.h> 51#include <net/ethernet.h> 52#include <net/if_dl.h> 53#include <net/if_llc.h> 54#include <net/if_media.h> 55#include <net/if_types.h> 56#include <net/if_vlan_var.h> 57 58#include <netinet/in.h> 59#include <netinet/in_systm.h> 60#include <netinet/ip.h> 61#include <netinet/tcp.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/pci/pcireg.h> 67#include <dev/pci/pcivar.h> 68 69#include <machine/bus.h> 70#include <machine/in_cksum.h> 71 72#include <dev/ale/if_alereg.h> 73#include <dev/ale/if_alevar.h> 74 75/* "device miibus" required. See GENERIC if you get errors here. */ 76#include "miibus_if.h" 77 78/* For more information about Tx checksum offload issues see ale_encap(). */ 79#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80 81MODULE_DEPEND(ale, pci, 1, 1, 1); 82MODULE_DEPEND(ale, ether, 1, 1, 1); 83MODULE_DEPEND(ale, miibus, 1, 1, 1); 84 85/* Tunables. */ 86static int msi_disable = 0; 87static int msix_disable = 0; 88TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90 91/* 92 * Devices supported by this driver. 93 */ 94static const struct ale_dev { 95 uint16_t ale_vendorid; 96 uint16_t ale_deviceid; 97 const char *ale_name; 98} ale_devs[] = { 99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101}; 102 103static int ale_attach(device_t); 104static int ale_check_boundary(struct ale_softc *); 105static int ale_detach(device_t); 106static int ale_dma_alloc(struct ale_softc *); 107static void ale_dma_free(struct ale_softc *); 108static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109static int ale_encap(struct ale_softc *, struct mbuf **); 110static void ale_get_macaddr(struct ale_softc *); 111static void ale_init(void *); 112static void ale_init_locked(struct ale_softc *); 113static void ale_init_rx_pages(struct ale_softc *); 114static void ale_init_tx_ring(struct ale_softc *); 115static void ale_int_task(void *, int); 116static int ale_intr(void *); 117static int ale_ioctl(struct ifnet *, u_long, caddr_t); 118static void ale_mac_config(struct ale_softc *); 119static int ale_miibus_readreg(device_t, int, int); 120static void ale_miibus_statchg(device_t); 121static int ale_miibus_writereg(device_t, int, int, int); 122static int ale_mediachange(struct ifnet *); 123static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 124static void ale_phy_reset(struct ale_softc *); 125static int ale_probe(device_t); 126static void ale_reset(struct ale_softc *); 127static int ale_resume(device_t); 128static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 129 uint32_t, uint32_t *); 130static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 131static int ale_rxeof(struct ale_softc *sc, int); 132static void ale_rxfilter(struct ale_softc *); 133static void ale_rxvlan(struct ale_softc *); 134static void ale_setlinkspeed(struct ale_softc *); 135static void ale_setwol(struct ale_softc *); 136static int ale_shutdown(device_t); 137static void ale_start(struct ifnet *); 138static void ale_start_locked(struct ifnet *); 139static void ale_stats_clear(struct ale_softc *); 140static void ale_stats_update(struct ale_softc *); 141static void ale_stop(struct ale_softc *); 142static void ale_stop_mac(struct ale_softc *); 143static int ale_suspend(device_t); 144static void ale_sysctl_node(struct ale_softc *); 145static void ale_tick(void *); 146static void ale_txeof(struct ale_softc *); 147static void ale_watchdog(struct ale_softc *); 148static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 149static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 150static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 151 152static device_method_t ale_methods[] = { 153 /* Device interface. */ 154 DEVMETHOD(device_probe, ale_probe), 155 DEVMETHOD(device_attach, ale_attach), 156 DEVMETHOD(device_detach, ale_detach), 157 DEVMETHOD(device_shutdown, ale_shutdown), 158 DEVMETHOD(device_suspend, ale_suspend), 159 DEVMETHOD(device_resume, ale_resume), 160 161 /* MII interface. */ 162 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 163 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 164 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 165 166 DEVMETHOD_END 167}; 168 169static driver_t ale_driver = { 170 "ale", 171 ale_methods, 172 sizeof(struct ale_softc) 173}; 174 175static devclass_t ale_devclass; 176 177DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 178DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 179 180static struct resource_spec ale_res_spec_mem[] = { 181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 182 { -1, 0, 0 } 183}; 184 185static struct resource_spec ale_irq_spec_legacy[] = { 186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 187 { -1, 0, 0 } 188}; 189 190static struct resource_spec ale_irq_spec_msi[] = { 191 { SYS_RES_IRQ, 1, RF_ACTIVE }, 192 { -1, 0, 0 } 193}; 194 195static struct resource_spec ale_irq_spec_msix[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198}; 199 200static int 201ale_miibus_readreg(device_t dev, int phy, int reg) 202{ 203 struct ale_softc *sc; 204 uint32_t v; 205 int i; 206 207 sc = device_get_softc(dev); 208 209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 212 DELAY(5); 213 v = CSR_READ_4(sc, ALE_MDIO); 214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 215 break; 216 } 217 218 if (i == 0) { 219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 220 return (0); 221 } 222 223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 224} 225 226static int 227ale_miibus_writereg(device_t dev, int phy, int reg, int val) 228{ 229 struct ale_softc *sc; 230 uint32_t v; 231 int i; 232 233 sc = device_get_softc(dev); 234 235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 239 DELAY(5); 240 v = CSR_READ_4(sc, ALE_MDIO); 241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 242 break; 243 } 244 245 if (i == 0) 246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 247 248 return (0); 249} 250 251static void 252ale_miibus_statchg(device_t dev) 253{ 254 struct ale_softc *sc; 255 struct mii_data *mii; 256 struct ifnet *ifp; 257 uint32_t reg; 258 259 sc = device_get_softc(dev); 260 mii = device_get_softc(sc->ale_miibus); 261 ifp = sc->ale_ifp; 262 if (mii == NULL || ifp == NULL || 263 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 264 return; 265 266 sc->ale_flags &= ~ALE_FLAG_LINK; 267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 268 (IFM_ACTIVE | IFM_AVALID)) { 269 switch (IFM_SUBTYPE(mii->mii_media_active)) { 270 case IFM_10_T: 271 case IFM_100_TX: 272 sc->ale_flags |= ALE_FLAG_LINK; 273 break; 274 case IFM_1000_T: 275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 276 sc->ale_flags |= ALE_FLAG_LINK; 277 break; 278 default: 279 break; 280 } 281 } 282 283 /* Stop Rx/Tx MACs. */ 284 ale_stop_mac(sc); 285 286 /* Program MACs with resolved speed/duplex/flow-control. */ 287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 288 ale_mac_config(sc); 289 /* Reenable Tx/Rx MACs. */ 290 reg = CSR_READ_4(sc, ALE_MAC_CFG); 291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 293 } 294} 295 296static void 297ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 298{ 299 struct ale_softc *sc; 300 struct mii_data *mii; 301 302 sc = ifp->if_softc; 303 ALE_LOCK(sc); 304 if ((ifp->if_flags & IFF_UP) == 0) { 305 ALE_UNLOCK(sc); 306 return; 307 } 308 mii = device_get_softc(sc->ale_miibus); 309 310 mii_pollstat(mii); 311 ifmr->ifm_status = mii->mii_media_status; 312 ifmr->ifm_active = mii->mii_media_active; 313 ALE_UNLOCK(sc); 314} 315 316static int 317ale_mediachange(struct ifnet *ifp) 318{ 319 struct ale_softc *sc; 320 struct mii_data *mii; 321 struct mii_softc *miisc; 322 int error; 323 324 sc = ifp->if_softc; 325 ALE_LOCK(sc); 326 mii = device_get_softc(sc->ale_miibus); 327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 328 PHY_RESET(miisc); 329 error = mii_mediachg(mii); 330 ALE_UNLOCK(sc); 331 332 return (error); 333} 334 335static int 336ale_probe(device_t dev) 337{ 338 const struct ale_dev *sp; 339 int i; 340 uint16_t vendor, devid; 341 342 vendor = pci_get_vendor(dev); 343 devid = pci_get_device(dev); 344 sp = ale_devs; 345 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 346 if (vendor == sp->ale_vendorid && 347 devid == sp->ale_deviceid) { 348 device_set_desc(dev, sp->ale_name); 349 return (BUS_PROBE_DEFAULT); 350 } 351 sp++; 352 } 353 354 return (ENXIO); 355} 356 357static void 358ale_get_macaddr(struct ale_softc *sc) 359{ 360 uint32_t ea[2], reg; 361 int i, vpdc; 362 363 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 364 if ((reg & SPI_VPD_ENB) != 0) { 365 reg &= ~SPI_VPD_ENB; 366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 367 } 368 369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 370 /* 371 * PCI VPD capability found, let TWSI reload EEPROM. 372 * This will set ethernet address of controller. 373 */ 374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 375 TWSI_CTRL_SW_LD_START); 376 for (i = 100; i > 0; i--) { 377 DELAY(1000); 378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 379 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 380 break; 381 } 382 if (i == 0) 383 device_printf(sc->ale_dev, 384 "reloading EEPROM timeout!\n"); 385 } else { 386 if (bootverbose) 387 device_printf(sc->ale_dev, 388 "PCI VPD capability not found!\n"); 389 } 390 391 ea[0] = CSR_READ_4(sc, ALE_PAR0); 392 ea[1] = CSR_READ_4(sc, ALE_PAR1); 393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 399} 400 401static void 402ale_phy_reset(struct ale_softc *sc) 403{ 404 405 /* Reset magic from Linux. */ 406 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 408 GPHY_CTRL_PHY_PLL_ON); 409 DELAY(1000); 410 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 413 DELAY(1000); 414 415#define ATPHY_DBG_ADDR 0x1D 416#define ATPHY_DBG_DATA 0x1E 417 418 /* Enable hibernation mode. */ 419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 420 ATPHY_DBG_ADDR, 0x0B); 421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 422 ATPHY_DBG_DATA, 0xBC00); 423 /* Set Class A/B for all modes. */ 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_ADDR, 0x00); 426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 427 ATPHY_DBG_DATA, 0x02EF); 428 /* Enable 10BT power saving. */ 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_ADDR, 0x12); 431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 432 ATPHY_DBG_DATA, 0x4C04); 433 /* Adjust 1000T power. */ 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_ADDR, 0x04); 436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 437 ATPHY_DBG_ADDR, 0x8BBB); 438 /* 10BT center tap voltage. */ 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x05); 441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 442 ATPHY_DBG_ADDR, 0x2C46); 443 444#undef ATPHY_DBG_ADDR 445#undef ATPHY_DBG_DATA 446 DELAY(1000); 447} 448 449static int 450ale_attach(device_t dev) 451{ 452 struct ale_softc *sc; 453 struct ifnet *ifp; 454 uint16_t burst; 455 int error, i, msic, msixc, pmc; 456 uint32_t rxf_len, txf_len; 457 458 error = 0; 459 sc = device_get_softc(dev); 460 sc->ale_dev = dev; 461 462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 463 MTX_DEF); 464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 465 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 466 467 /* Map the device. */ 468 pci_enable_busmaster(dev); 469 sc->ale_res_spec = ale_res_spec_mem; 470 sc->ale_irq_spec = ale_irq_spec_legacy; 471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 472 if (error != 0) { 473 device_printf(dev, "cannot allocate memory resources.\n"); 474 goto fail; 475 } 476 477 /* Set PHY address. */ 478 sc->ale_phyaddr = ALE_PHY_ADDR; 479 480 /* Reset PHY. */ 481 ale_phy_reset(sc); 482 483 /* Reset the ethernet controller. */ 484 ale_reset(sc); 485 486 /* Get PCI and chip id/revision. */ 487 sc->ale_rev = pci_get_revid(dev); 488 if (sc->ale_rev >= 0xF0) { 489 /* L2E Rev. B. AR8114 */ 490 sc->ale_flags |= ALE_FLAG_FASTETHER; 491 } else { 492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 493 /* L1E AR8121 */ 494 sc->ale_flags |= ALE_FLAG_JUMBO; 495 } else { 496 /* L2E Rev. A. AR8113 */ 497 sc->ale_flags |= ALE_FLAG_FASTETHER; 498 } 499 } 500 /* 501 * All known controllers seems to require 4 bytes alignment 502 * of Tx buffers to make Tx checksum offload with custom 503 * checksum generation method work. 504 */ 505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 506 /* 507 * All known controllers seems to have issues on Rx checksum 508 * offload for fragmented IP datagrams. 509 */ 510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 511 /* 512 * Don't use Tx CMB. It is known to cause RRS update failure 513 * under certain circumstances. Typical phenomenon of the 514 * issue would be unexpected sequence number encountered in 515 * Rx handler. 516 */ 517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 519 MASTER_CHIP_REV_SHIFT; 520 if (bootverbose) { 521 device_printf(dev, "PCI device revision : 0x%04x\n", 522 sc->ale_rev); 523 device_printf(dev, "Chip id/revision : 0x%04x\n", 524 sc->ale_chip_rev); 525 } 526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 528 /* 529 * Uninitialized hardware returns an invalid chip id/revision 530 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 531 */ 532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 533 rxf_len == 0xFFFFFFF) { 534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 536 txf_len, rxf_len); 537 error = ENXIO; 538 goto fail; 539 } 540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 541 542 /* Allocate IRQ resources. */ 543 msixc = pci_msix_count(dev); 544 msic = pci_msi_count(dev); 545 if (bootverbose) { 546 device_printf(dev, "MSIX count : %d\n", msixc); 547 device_printf(dev, "MSI count : %d\n", msic); 548 } 549 550 /* Prefer MSIX over MSI. */ 551 if (msix_disable == 0 || msi_disable == 0) { 552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 553 pci_alloc_msix(dev, &msixc) == 0) { 554 if (msixc == ALE_MSIX_MESSAGES) { 555 device_printf(dev, "Using %d MSIX messages.\n", 556 msixc); 557 sc->ale_flags |= ALE_FLAG_MSIX; 558 sc->ale_irq_spec = ale_irq_spec_msix; 559 } else 560 pci_release_msi(dev); 561 } 562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 563 msic == ALE_MSI_MESSAGES && 564 pci_alloc_msi(dev, &msic) == 0) { 565 if (msic == ALE_MSI_MESSAGES) { 566 device_printf(dev, "Using %d MSI messages.\n", 567 msic); 568 sc->ale_flags |= ALE_FLAG_MSI; 569 sc->ale_irq_spec = ale_irq_spec_msi; 570 } else 571 pci_release_msi(dev); 572 } 573 } 574 575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 576 if (error != 0) { 577 device_printf(dev, "cannot allocate IRQ resources.\n"); 578 goto fail; 579 } 580 581 /* Get DMA parameters from PCIe device control register. */ 582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 583 sc->ale_flags |= ALE_FLAG_PCIE; 584 burst = pci_read_config(dev, i + 0x08, 2); 585 /* Max read request size. */ 586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 587 DMA_CFG_RD_BURST_SHIFT; 588 /* Max payload size. */ 589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 590 DMA_CFG_WR_BURST_SHIFT; 591 if (bootverbose) { 592 device_printf(dev, "Read request size : %d bytes.\n", 593 128 << ((burst >> 12) & 0x07)); 594 device_printf(dev, "TLP payload size : %d bytes.\n", 595 128 << ((burst >> 5) & 0x07)); 596 } 597 } else { 598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 600 } 601 602 /* Create device sysctl node. */ 603 ale_sysctl_node(sc); 604 605 if ((error = ale_dma_alloc(sc) != 0)) 606 goto fail; 607 608 /* Load station address. */ 609 ale_get_macaddr(sc); 610 611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 612 if (ifp == NULL) { 613 device_printf(dev, "cannot allocate ifnet structure.\n"); 614 error = ENXIO; 615 goto fail; 616 } 617 618 ifp->if_softc = sc; 619 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_ioctl = ale_ioctl; 622 ifp->if_start = ale_start; 623 ifp->if_init = ale_init; 624 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 625 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 626 IFQ_SET_READY(&ifp->if_snd); 627 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 628 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 629 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 630 sc->ale_flags |= ALE_FLAG_PMCAP; 631 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 632 } 633 ifp->if_capenable = ifp->if_capabilities; 634 635 /* Set up MII bus. */ 636 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 637 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 638 MIIF_DOPAUSE); 639 if (error != 0) { 640 device_printf(dev, "attaching PHYs failed\n"); 641 goto fail; 642 } 643 644 ether_ifattach(ifp, sc->ale_eaddr); 645 646 /* VLAN capability setup. */ 647 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 648 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 649 ifp->if_capenable = ifp->if_capabilities; 650 /* 651 * Even though controllers supported by ale(3) have Rx checksum 652 * offload bug the workaround for fragmented frames seemed to 653 * work so far. However it seems Rx checksum offload does not 654 * work under certain conditions. So disable Rx checksum offload 655 * until I find more clue about it but allow users to override it. 656 */ 657 ifp->if_capenable &= ~IFCAP_RXCSUM; 658 659 /* Tell the upper layer(s) we support long frames. */ 660 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 661 662 /* Create local taskq. */ 663 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 664 taskqueue_thread_enqueue, &sc->ale_tq); 665 if (sc->ale_tq == NULL) { 666 device_printf(dev, "could not create taskqueue.\n"); 667 ether_ifdetach(ifp); 668 error = ENXIO; 669 goto fail; 670 } 671 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 672 device_get_nameunit(sc->ale_dev)); 673 674 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 675 msic = ALE_MSIX_MESSAGES; 676 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 677 msic = ALE_MSI_MESSAGES; 678 else 679 msic = 1; 680 for (i = 0; i < msic; i++) { 681 error = bus_setup_intr(dev, sc->ale_irq[i], 682 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 683 &sc->ale_intrhand[i]); 684 if (error != 0) 685 break; 686 } 687 if (error != 0) { 688 device_printf(dev, "could not set up interrupt handler.\n"); 689 taskqueue_free(sc->ale_tq); 690 sc->ale_tq = NULL; 691 ether_ifdetach(ifp); 692 goto fail; 693 } 694 695fail: 696 if (error != 0) 697 ale_detach(dev); 698 699 return (error); 700} 701 702static int 703ale_detach(device_t dev) 704{ 705 struct ale_softc *sc; 706 struct ifnet *ifp; 707 int i, msic; 708 709 sc = device_get_softc(dev); 710 711 ifp = sc->ale_ifp; 712 if (device_is_attached(dev)) { 713 ether_ifdetach(ifp); 714 ALE_LOCK(sc); 715 ale_stop(sc); 716 ALE_UNLOCK(sc); 717 callout_drain(&sc->ale_tick_ch); 718 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 719 } 720 721 if (sc->ale_tq != NULL) { 722 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 723 taskqueue_free(sc->ale_tq); 724 sc->ale_tq = NULL; 725 } 726 727 if (sc->ale_miibus != NULL) { 728 device_delete_child(dev, sc->ale_miibus); 729 sc->ale_miibus = NULL; 730 } 731 bus_generic_detach(dev); 732 ale_dma_free(sc); 733 734 if (ifp != NULL) { 735 if_free(ifp); 736 sc->ale_ifp = NULL; 737 } 738 739 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 740 msic = ALE_MSIX_MESSAGES; 741 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 742 msic = ALE_MSI_MESSAGES; 743 else 744 msic = 1; 745 for (i = 0; i < msic; i++) { 746 if (sc->ale_intrhand[i] != NULL) { 747 bus_teardown_intr(dev, sc->ale_irq[i], 748 sc->ale_intrhand[i]); 749 sc->ale_intrhand[i] = NULL; 750 } 751 } 752 753 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 754 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 755 pci_release_msi(dev); 756 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 757 mtx_destroy(&sc->ale_mtx); 758 759 return (0); 760} 761 762#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 763 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 764 765#if __FreeBSD_version >= 900030 766#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 767 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 768#elif __FreeBSD_version > 800000 769#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 770 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 771#else 772#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 773 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 774#endif 775 776static void 777ale_sysctl_node(struct ale_softc *sc) 778{ 779 struct sysctl_ctx_list *ctx; 780 struct sysctl_oid_list *child, *parent; 781 struct sysctl_oid *tree; 782 struct ale_hw_stats *stats; 783 int error; 784 785 stats = &sc->ale_stats; 786 ctx = device_get_sysctl_ctx(sc->ale_dev); 787 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 788 789 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 790 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 791 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 792 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 793 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 794 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 795 /* Pull in device tunables. */ 796 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 797 error = resource_int_value(device_get_name(sc->ale_dev), 798 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 799 if (error == 0) { 800 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 801 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 802 device_printf(sc->ale_dev, "int_rx_mod value out of " 803 "range; using default: %d\n", 804 ALE_IM_RX_TIMER_DEFAULT); 805 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 806 } 807 } 808 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 809 error = resource_int_value(device_get_name(sc->ale_dev), 810 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 811 if (error == 0) { 812 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 813 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 814 device_printf(sc->ale_dev, "int_tx_mod value out of " 815 "range; using default: %d\n", 816 ALE_IM_TX_TIMER_DEFAULT); 817 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 818 } 819 } 820 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 821 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 822 sysctl_hw_ale_proc_limit, "I", 823 "max number of Rx events to process"); 824 /* Pull in device tunables. */ 825 sc->ale_process_limit = ALE_PROC_DEFAULT; 826 error = resource_int_value(device_get_name(sc->ale_dev), 827 device_get_unit(sc->ale_dev), "process_limit", 828 &sc->ale_process_limit); 829 if (error == 0) { 830 if (sc->ale_process_limit < ALE_PROC_MIN || 831 sc->ale_process_limit > ALE_PROC_MAX) { 832 device_printf(sc->ale_dev, 833 "process_limit value out of range; " 834 "using default: %d\n", ALE_PROC_DEFAULT); 835 sc->ale_process_limit = ALE_PROC_DEFAULT; 836 } 837 } 838 839 /* Misc statistics. */ 840 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 841 &stats->reset_brk_seq, 842 "Controller resets due to broken Rx sequnce number"); 843 844 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 845 NULL, "ATE statistics"); 846 parent = SYSCTL_CHILDREN(tree); 847 848 /* Rx statistics. */ 849 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 850 NULL, "Rx MAC statistics"); 851 child = SYSCTL_CHILDREN(tree); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 853 &stats->rx_frames, "Good frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 855 &stats->rx_bcast_frames, "Good broadcast frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 857 &stats->rx_mcast_frames, "Good multicast frames"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 859 &stats->rx_pause_frames, "Pause control frames"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 861 &stats->rx_control_frames, "Control frames"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 863 &stats->rx_crcerrs, "CRC errors"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 865 &stats->rx_lenerrs, "Frames with length mismatched"); 866 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 867 &stats->rx_bytes, "Good octets"); 868 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 869 &stats->rx_bcast_bytes, "Good broadcast octets"); 870 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 871 &stats->rx_mcast_bytes, "Good multicast octets"); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 873 &stats->rx_runts, "Too short frames"); 874 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 875 &stats->rx_fragments, "Fragmented frames"); 876 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 877 &stats->rx_pkts_64, "64 bytes frames"); 878 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 879 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 881 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 883 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 885 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 886 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 887 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 888 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 889 &stats->rx_pkts_1519_max, "1519 to max frames"); 890 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 891 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 893 &stats->rx_fifo_oflows, "FIFO overflows"); 894 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 895 &stats->rx_rrs_errs, "Return status write-back errors"); 896 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 897 &stats->rx_alignerrs, "Alignment errors"); 898 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 899 &stats->rx_pkts_filtered, 900 "Frames dropped due to address filtering"); 901 902 /* Tx statistics. */ 903 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 904 NULL, "Tx MAC statistics"); 905 child = SYSCTL_CHILDREN(tree); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 907 &stats->tx_frames, "Good frames"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 909 &stats->tx_bcast_frames, "Good broadcast frames"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 911 &stats->tx_mcast_frames, "Good multicast frames"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 913 &stats->tx_pause_frames, "Pause control frames"); 914 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 915 &stats->tx_control_frames, "Control frames"); 916 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 917 &stats->tx_excess_defer, "Frames with excessive derferrals"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 919 &stats->tx_excess_defer, "Frames with derferrals"); 920 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 921 &stats->tx_bytes, "Good octets"); 922 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 923 &stats->tx_bcast_bytes, "Good broadcast octets"); 924 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 925 &stats->tx_mcast_bytes, "Good multicast octets"); 926 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 927 &stats->tx_pkts_64, "64 bytes frames"); 928 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 929 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 930 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 931 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 932 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 933 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 934 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 935 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 936 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 937 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 938 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 939 &stats->tx_pkts_1519_max, "1519 to max frames"); 940 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 941 &stats->tx_single_colls, "Single collisions"); 942 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 943 &stats->tx_multi_colls, "Multiple collisions"); 944 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 945 &stats->tx_late_colls, "Late collisions"); 946 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 947 &stats->tx_excess_colls, "Excessive collisions"); 948 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 949 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 950 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 951 &stats->tx_underrun, "FIFO underruns"); 952 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 953 &stats->tx_desc_underrun, "Descriptor write-back errors"); 954 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 955 &stats->tx_lenerrs, "Frames with length mismatched"); 956 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 957 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 958} 959 960#undef ALE_SYSCTL_STAT_ADD32 961#undef ALE_SYSCTL_STAT_ADD64 962 963struct ale_dmamap_arg { 964 bus_addr_t ale_busaddr; 965}; 966 967static void 968ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 969{ 970 struct ale_dmamap_arg *ctx; 971 972 if (error != 0) 973 return; 974 975 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 976 977 ctx = (struct ale_dmamap_arg *)arg; 978 ctx->ale_busaddr = segs[0].ds_addr; 979} 980 981/* 982 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 983 * which specifies high address region of DMA blocks. Therefore these 984 * blocks should have the same high address of given 4GB address 985 * space(i.e. crossing 4GB boundary is not allowed). 986 */ 987static int 988ale_check_boundary(struct ale_softc *sc) 989{ 990 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 991 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 992 993 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 994 sc->ale_pagesize; 995 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 996 sc->ale_pagesize; 997 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 998 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 999 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 1000 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 1001 1002 if ((ALE_ADDR_HI(tx_ring_end) != 1003 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1004 (ALE_ADDR_HI(rx_page_end[0]) != 1005 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1006 (ALE_ADDR_HI(rx_page_end[1]) != 1007 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1008 (ALE_ADDR_HI(tx_cmb_end) != 1009 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1010 (ALE_ADDR_HI(rx_cmb_end[0]) != 1011 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1012 (ALE_ADDR_HI(rx_cmb_end[1]) != 1013 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1014 return (EFBIG); 1015 1016 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1017 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1021 return (EFBIG); 1022 1023 return (0); 1024} 1025 1026static int 1027ale_dma_alloc(struct ale_softc *sc) 1028{ 1029 struct ale_txdesc *txd; 1030 bus_addr_t lowaddr; 1031 struct ale_dmamap_arg ctx; 1032 int error, guard_size, i; 1033 1034 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1035 guard_size = ALE_JUMBO_FRAMELEN; 1036 else 1037 guard_size = ALE_MAX_FRAMELEN; 1038 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1039 ALE_RX_PAGE_ALIGN); 1040 lowaddr = BUS_SPACE_MAXADDR; 1041again: 1042 /* Create parent DMA tag. */ 1043 error = bus_dma_tag_create( 1044 bus_get_dma_tag(sc->ale_dev), /* parent */ 1045 1, 0, /* alignment, boundary */ 1046 lowaddr, /* lowaddr */ 1047 BUS_SPACE_MAXADDR, /* highaddr */ 1048 NULL, NULL, /* filter, filterarg */ 1049 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1050 0, /* nsegments */ 1051 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1052 0, /* flags */ 1053 NULL, NULL, /* lockfunc, lockarg */ 1054 &sc->ale_cdata.ale_parent_tag); 1055 if (error != 0) { 1056 device_printf(sc->ale_dev, 1057 "could not create parent DMA tag.\n"); 1058 goto fail; 1059 } 1060 1061 /* Create DMA tag for Tx descriptor ring. */ 1062 error = bus_dma_tag_create( 1063 sc->ale_cdata.ale_parent_tag, /* parent */ 1064 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1065 BUS_SPACE_MAXADDR, /* lowaddr */ 1066 BUS_SPACE_MAXADDR, /* highaddr */ 1067 NULL, NULL, /* filter, filterarg */ 1068 ALE_TX_RING_SZ, /* maxsize */ 1069 1, /* nsegments */ 1070 ALE_TX_RING_SZ, /* maxsegsize */ 1071 0, /* flags */ 1072 NULL, NULL, /* lockfunc, lockarg */ 1073 &sc->ale_cdata.ale_tx_ring_tag); 1074 if (error != 0) { 1075 device_printf(sc->ale_dev, 1076 "could not create Tx ring DMA tag.\n"); 1077 goto fail; 1078 } 1079 1080 /* Create DMA tag for Rx pages. */ 1081 for (i = 0; i < ALE_RX_PAGES; i++) { 1082 error = bus_dma_tag_create( 1083 sc->ale_cdata.ale_parent_tag, /* parent */ 1084 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1085 BUS_SPACE_MAXADDR, /* lowaddr */ 1086 BUS_SPACE_MAXADDR, /* highaddr */ 1087 NULL, NULL, /* filter, filterarg */ 1088 sc->ale_pagesize, /* maxsize */ 1089 1, /* nsegments */ 1090 sc->ale_pagesize, /* maxsegsize */ 1091 0, /* flags */ 1092 NULL, NULL, /* lockfunc, lockarg */ 1093 &sc->ale_cdata.ale_rx_page[i].page_tag); 1094 if (error != 0) { 1095 device_printf(sc->ale_dev, 1096 "could not create Rx page %d DMA tag.\n", i); 1097 goto fail; 1098 } 1099 } 1100 1101 /* Create DMA tag for Tx coalescing message block. */ 1102 error = bus_dma_tag_create( 1103 sc->ale_cdata.ale_parent_tag, /* parent */ 1104 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1105 BUS_SPACE_MAXADDR, /* lowaddr */ 1106 BUS_SPACE_MAXADDR, /* highaddr */ 1107 NULL, NULL, /* filter, filterarg */ 1108 ALE_TX_CMB_SZ, /* maxsize */ 1109 1, /* nsegments */ 1110 ALE_TX_CMB_SZ, /* maxsegsize */ 1111 0, /* flags */ 1112 NULL, NULL, /* lockfunc, lockarg */ 1113 &sc->ale_cdata.ale_tx_cmb_tag); 1114 if (error != 0) { 1115 device_printf(sc->ale_dev, 1116 "could not create Tx CMB DMA tag.\n"); 1117 goto fail; 1118 } 1119 1120 /* Create DMA tag for Rx coalescing message block. */ 1121 for (i = 0; i < ALE_RX_PAGES; i++) { 1122 error = bus_dma_tag_create( 1123 sc->ale_cdata.ale_parent_tag, /* parent */ 1124 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1125 BUS_SPACE_MAXADDR, /* lowaddr */ 1126 BUS_SPACE_MAXADDR, /* highaddr */ 1127 NULL, NULL, /* filter, filterarg */ 1128 ALE_RX_CMB_SZ, /* maxsize */ 1129 1, /* nsegments */ 1130 ALE_RX_CMB_SZ, /* maxsegsize */ 1131 0, /* flags */ 1132 NULL, NULL, /* lockfunc, lockarg */ 1133 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1134 if (error != 0) { 1135 device_printf(sc->ale_dev, 1136 "could not create Rx page %d CMB DMA tag.\n", i); 1137 goto fail; 1138 } 1139 } 1140 1141 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1142 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1143 (void **)&sc->ale_cdata.ale_tx_ring, 1144 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1145 &sc->ale_cdata.ale_tx_ring_map); 1146 if (error != 0) { 1147 device_printf(sc->ale_dev, 1148 "could not allocate DMA'able memory for Tx ring.\n"); 1149 goto fail; 1150 } 1151 ctx.ale_busaddr = 0; 1152 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1153 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1154 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1155 if (error != 0 || ctx.ale_busaddr == 0) { 1156 device_printf(sc->ale_dev, 1157 "could not load DMA'able memory for Tx ring.\n"); 1158 goto fail; 1159 } 1160 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1161 1162 /* Rx pages. */ 1163 for (i = 0; i < ALE_RX_PAGES; i++) { 1164 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1165 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1166 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1167 &sc->ale_cdata.ale_rx_page[i].page_map); 1168 if (error != 0) { 1169 device_printf(sc->ale_dev, 1170 "could not allocate DMA'able memory for " 1171 "Rx page %d.\n", i); 1172 goto fail; 1173 } 1174 ctx.ale_busaddr = 0; 1175 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1176 sc->ale_cdata.ale_rx_page[i].page_map, 1177 sc->ale_cdata.ale_rx_page[i].page_addr, 1178 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1179 if (error != 0 || ctx.ale_busaddr == 0) { 1180 device_printf(sc->ale_dev, 1181 "could not load DMA'able memory for " 1182 "Rx page %d.\n", i); 1183 goto fail; 1184 } 1185 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1186 } 1187 1188 /* Tx CMB. */ 1189 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1190 (void **)&sc->ale_cdata.ale_tx_cmb, 1191 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1192 &sc->ale_cdata.ale_tx_cmb_map); 1193 if (error != 0) { 1194 device_printf(sc->ale_dev, 1195 "could not allocate DMA'able memory for Tx CMB.\n"); 1196 goto fail; 1197 } 1198 ctx.ale_busaddr = 0; 1199 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1200 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1201 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1202 if (error != 0 || ctx.ale_busaddr == 0) { 1203 device_printf(sc->ale_dev, 1204 "could not load DMA'able memory for Tx CMB.\n"); 1205 goto fail; 1206 } 1207 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1208 1209 /* Rx CMB. */ 1210 for (i = 0; i < ALE_RX_PAGES; i++) { 1211 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1212 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1213 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1214 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1215 if (error != 0) { 1216 device_printf(sc->ale_dev, "could not allocate " 1217 "DMA'able memory for Rx page %d CMB.\n", i); 1218 goto fail; 1219 } 1220 ctx.ale_busaddr = 0; 1221 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1222 sc->ale_cdata.ale_rx_page[i].cmb_map, 1223 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1224 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1225 if (error != 0 || ctx.ale_busaddr == 0) { 1226 device_printf(sc->ale_dev, "could not load DMA'able " 1227 "memory for Rx page %d CMB.\n", i); 1228 goto fail; 1229 } 1230 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1231 } 1232 1233 /* 1234 * Tx descriptors/RXF0/CMB DMA blocks share the same 1235 * high address region of 64bit DMA address space. 1236 */ 1237 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1238 (error = ale_check_boundary(sc)) != 0) { 1239 device_printf(sc->ale_dev, "4GB boundary crossed, " 1240 "switching to 32bit DMA addressing mode.\n"); 1241 ale_dma_free(sc); 1242 /* 1243 * Limit max allowable DMA address space to 32bit 1244 * and try again. 1245 */ 1246 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1247 goto again; 1248 } 1249 1250 /* 1251 * Create Tx buffer parent tag. 1252 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1253 * needs separate parent DMA tag as parent DMA address space 1254 * could be restricted to be within 32bit address space by 1255 * 4GB boundary crossing. 1256 */ 1257 error = bus_dma_tag_create( 1258 bus_get_dma_tag(sc->ale_dev), /* parent */ 1259 1, 0, /* alignment, boundary */ 1260 BUS_SPACE_MAXADDR, /* lowaddr */ 1261 BUS_SPACE_MAXADDR, /* highaddr */ 1262 NULL, NULL, /* filter, filterarg */ 1263 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1264 0, /* nsegments */ 1265 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1266 0, /* flags */ 1267 NULL, NULL, /* lockfunc, lockarg */ 1268 &sc->ale_cdata.ale_buffer_tag); 1269 if (error != 0) { 1270 device_printf(sc->ale_dev, 1271 "could not create parent buffer DMA tag.\n"); 1272 goto fail; 1273 } 1274 1275 /* Create DMA tag for Tx buffers. */ 1276 error = bus_dma_tag_create( 1277 sc->ale_cdata.ale_buffer_tag, /* parent */ 1278 1, 0, /* alignment, boundary */ 1279 BUS_SPACE_MAXADDR, /* lowaddr */ 1280 BUS_SPACE_MAXADDR, /* highaddr */ 1281 NULL, NULL, /* filter, filterarg */ 1282 ALE_TSO_MAXSIZE, /* maxsize */ 1283 ALE_MAXTXSEGS, /* nsegments */ 1284 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1285 0, /* flags */ 1286 NULL, NULL, /* lockfunc, lockarg */ 1287 &sc->ale_cdata.ale_tx_tag); 1288 if (error != 0) { 1289 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1290 goto fail; 1291 } 1292 1293 /* Create DMA maps for Tx buffers. */ 1294 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1295 txd = &sc->ale_cdata.ale_txdesc[i]; 1296 txd->tx_m = NULL; 1297 txd->tx_dmamap = NULL; 1298 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1299 &txd->tx_dmamap); 1300 if (error != 0) { 1301 device_printf(sc->ale_dev, 1302 "could not create Tx dmamap.\n"); 1303 goto fail; 1304 } 1305 } 1306 1307fail: 1308 return (error); 1309} 1310 1311static void 1312ale_dma_free(struct ale_softc *sc) 1313{ 1314 struct ale_txdesc *txd; 1315 int i; 1316 1317 /* Tx buffers. */ 1318 if (sc->ale_cdata.ale_tx_tag != NULL) { 1319 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1320 txd = &sc->ale_cdata.ale_txdesc[i]; 1321 if (txd->tx_dmamap != NULL) { 1322 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1323 txd->tx_dmamap); 1324 txd->tx_dmamap = NULL; 1325 } 1326 } 1327 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1328 sc->ale_cdata.ale_tx_tag = NULL; 1329 } 1330 /* Tx descriptor ring. */ 1331 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1332 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1333 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1334 sc->ale_cdata.ale_tx_ring_map); 1335 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1336 sc->ale_cdata.ale_tx_ring != NULL) 1337 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1338 sc->ale_cdata.ale_tx_ring, 1339 sc->ale_cdata.ale_tx_ring_map); 1340 sc->ale_cdata.ale_tx_ring = NULL; 1341 sc->ale_cdata.ale_tx_ring_map = NULL; 1342 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1343 sc->ale_cdata.ale_tx_ring_tag = NULL; 1344 } 1345 /* Rx page block. */ 1346 for (i = 0; i < ALE_RX_PAGES; i++) { 1347 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1348 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1349 bus_dmamap_unload( 1350 sc->ale_cdata.ale_rx_page[i].page_tag, 1351 sc->ale_cdata.ale_rx_page[i].page_map); 1352 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1353 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1354 bus_dmamem_free( 1355 sc->ale_cdata.ale_rx_page[i].page_tag, 1356 sc->ale_cdata.ale_rx_page[i].page_addr, 1357 sc->ale_cdata.ale_rx_page[i].page_map); 1358 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1359 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1360 bus_dma_tag_destroy( 1361 sc->ale_cdata.ale_rx_page[i].page_tag); 1362 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1363 } 1364 } 1365 /* Rx CMB. */ 1366 for (i = 0; i < ALE_RX_PAGES; i++) { 1367 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1368 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1369 bus_dmamap_unload( 1370 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1371 sc->ale_cdata.ale_rx_page[i].cmb_map); 1372 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1373 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1374 bus_dmamem_free( 1375 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1376 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1377 sc->ale_cdata.ale_rx_page[i].cmb_map); 1378 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1379 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1380 bus_dma_tag_destroy( 1381 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1382 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1383 } 1384 } 1385 /* Tx CMB. */ 1386 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1387 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1388 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1389 sc->ale_cdata.ale_tx_cmb_map); 1390 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1391 sc->ale_cdata.ale_tx_cmb != NULL) 1392 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1393 sc->ale_cdata.ale_tx_cmb, 1394 sc->ale_cdata.ale_tx_cmb_map); 1395 sc->ale_cdata.ale_tx_cmb = NULL; 1396 sc->ale_cdata.ale_tx_cmb_map = NULL; 1397 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1398 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1399 } 1400 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1401 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1402 sc->ale_cdata.ale_buffer_tag = NULL; 1403 } 1404 if (sc->ale_cdata.ale_parent_tag != NULL) { 1405 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1406 sc->ale_cdata.ale_parent_tag = NULL; 1407 } 1408} 1409 1410static int 1411ale_shutdown(device_t dev) 1412{ 1413 1414 return (ale_suspend(dev)); 1415} 1416 1417/* 1418 * Note, this driver resets the link speed to 10/100Mbps by 1419 * restarting auto-negotiation in suspend/shutdown phase but we 1420 * don't know whether that auto-negotiation would succeed or not 1421 * as driver has no control after powering off/suspend operation. 1422 * If the renegotiation fail WOL may not work. Running at 1Gbps 1423 * will draw more power than 375mA at 3.3V which is specified in 1424 * PCI specification and that would result in complete 1425 * shutdowning power to ethernet controller. 1426 * 1427 * TODO 1428 * Save current negotiated media speed/duplex/flow-control to 1429 * softc and restore the same link again after resuming. PHY 1430 * handling such as power down/resetting to 100Mbps may be better 1431 * handled in suspend method in phy driver. 1432 */ 1433static void 1434ale_setlinkspeed(struct ale_softc *sc) 1435{ 1436 struct mii_data *mii; 1437 int aneg, i; 1438 1439 mii = device_get_softc(sc->ale_miibus); 1440 mii_pollstat(mii); 1441 aneg = 0; 1442 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1443 (IFM_ACTIVE | IFM_AVALID)) { 1444 switch IFM_SUBTYPE(mii->mii_media_active) { 1445 case IFM_10_T: 1446 case IFM_100_TX: 1447 return; 1448 case IFM_1000_T: 1449 aneg++; 1450 break; 1451 default: 1452 break; 1453 } 1454 } 1455 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1456 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1457 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1458 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1459 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1460 DELAY(1000); 1461 if (aneg != 0) { 1462 /* 1463 * Poll link state until ale(4) get a 10/100Mbps link. 1464 */ 1465 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1466 mii_pollstat(mii); 1467 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1468 == (IFM_ACTIVE | IFM_AVALID)) { 1469 switch (IFM_SUBTYPE( 1470 mii->mii_media_active)) { 1471 case IFM_10_T: 1472 case IFM_100_TX: 1473 ale_mac_config(sc); 1474 return; 1475 default: 1476 break; 1477 } 1478 } 1479 ALE_UNLOCK(sc); 1480 pause("alelnk", hz); 1481 ALE_LOCK(sc); 1482 } 1483 if (i == MII_ANEGTICKS_GIGE) 1484 device_printf(sc->ale_dev, 1485 "establishing a link failed, WOL may not work!"); 1486 } 1487 /* 1488 * No link, force MAC to have 100Mbps, full-duplex link. 1489 * This is the last resort and may/may not work. 1490 */ 1491 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1492 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1493 ale_mac_config(sc); 1494} 1495 1496static void 1497ale_setwol(struct ale_softc *sc) 1498{ 1499 struct ifnet *ifp; 1500 uint32_t reg, pmcs; 1501 uint16_t pmstat; 1502 int pmc; 1503 1504 ALE_LOCK_ASSERT(sc); 1505 1506 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1507 /* Disable WOL. */ 1508 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1509 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1510 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1511 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1512 /* Force PHY power down. */ 1513 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1514 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1515 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1516 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1517 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1518 return; 1519 } 1520 1521 ifp = sc->ale_ifp; 1522 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1523 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1524 ale_setlinkspeed(sc); 1525 } 1526 1527 pmcs = 0; 1528 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1529 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1530 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1531 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1532 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1533 MAC_CFG_BCAST); 1534 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1535 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1536 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1537 reg |= MAC_CFG_RX_ENB; 1538 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1539 1540 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1541 /* WOL disabled, PHY power down. */ 1542 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1543 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1544 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1545 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1546 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1547 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1548 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1549 GPHY_CTRL_PWDOWN_HW); 1550 } 1551 /* Request PME. */ 1552 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1553 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1554 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1555 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1556 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1557} 1558 1559static int 1560ale_suspend(device_t dev) 1561{ 1562 struct ale_softc *sc; 1563 1564 sc = device_get_softc(dev); 1565 1566 ALE_LOCK(sc); 1567 ale_stop(sc); 1568 ale_setwol(sc); 1569 ALE_UNLOCK(sc); 1570 1571 return (0); 1572} 1573 1574static int 1575ale_resume(device_t dev) 1576{ 1577 struct ale_softc *sc; 1578 struct ifnet *ifp; 1579 int pmc; 1580 uint16_t pmstat; 1581 1582 sc = device_get_softc(dev); 1583 1584 ALE_LOCK(sc); 1585 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1586 /* Disable PME and clear PME status. */ 1587 pmstat = pci_read_config(sc->ale_dev, 1588 pmc + PCIR_POWER_STATUS, 2); 1589 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1590 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1591 pci_write_config(sc->ale_dev, 1592 pmc + PCIR_POWER_STATUS, pmstat, 2); 1593 } 1594 } 1595 /* Reset PHY. */ 1596 ale_phy_reset(sc); 1597 ifp = sc->ale_ifp; 1598 if ((ifp->if_flags & IFF_UP) != 0) { 1599 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1600 ale_init_locked(sc); 1601 } 1602 ALE_UNLOCK(sc); 1603 1604 return (0); 1605} 1606 1607static int 1608ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1609{ 1610 struct ale_txdesc *txd, *txd_last; 1611 struct tx_desc *desc; 1612 struct mbuf *m; 1613 struct ip *ip; 1614 struct tcphdr *tcp; 1615 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1616 bus_dmamap_t map; 1617 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1618 int error, i, nsegs, prod, si; 1619 1620 ALE_LOCK_ASSERT(sc); 1621 1622 M_ASSERTPKTHDR((*m_head)); 1623 1624 m = *m_head; 1625 ip = NULL; 1626 tcp = NULL; 1627 cflags = vtag = 0; 1628 ip_off = poff = 0; 1629 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1630 /* 1631 * AR81xx requires offset of TCP/UDP payload in its Tx 1632 * descriptor to perform hardware Tx checksum offload. 1633 * Additionally, TSO requires IP/TCP header size and 1634 * modification of IP/TCP header in order to make TSO 1635 * engine work. This kind of operation takes many CPU 1636 * cycles on FreeBSD so fast host CPU is required to 1637 * get smooth TSO performance. 1638 */ 1639 struct ether_header *eh; 1640 1641 if (M_WRITABLE(m) == 0) { 1642 /* Get a writable copy. */ 1643 m = m_dup(*m_head, M_NOWAIT); 1644 /* Release original mbufs. */ 1645 m_freem(*m_head); 1646 if (m == NULL) { 1647 *m_head = NULL; 1648 return (ENOBUFS); 1649 } 1650 *m_head = m; 1651 } 1652 1653 /* 1654 * Buggy-controller requires 4 byte aligned Tx buffer 1655 * to make custom checksum offload work. 1656 */ 1657 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1658 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1659 (mtod(m, intptr_t) & 3) != 0) { 1660 m = m_defrag(*m_head, M_NOWAIT); 1661 if (m == NULL) { 1662 m_freem(*m_head); 1663 *m_head = NULL; 1664 return (ENOBUFS); 1665 } 1666 *m_head = m; 1667 } 1668 1669 ip_off = sizeof(struct ether_header); 1670 m = m_pullup(m, ip_off); 1671 if (m == NULL) { 1672 *m_head = NULL; 1673 return (ENOBUFS); 1674 } 1675 eh = mtod(m, struct ether_header *); 1676 /* 1677 * Check if hardware VLAN insertion is off. 1678 * Additional check for LLC/SNAP frame? 1679 */ 1680 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1681 ip_off = sizeof(struct ether_vlan_header); 1682 m = m_pullup(m, ip_off); 1683 if (m == NULL) { 1684 *m_head = NULL; 1685 return (ENOBUFS); 1686 } 1687 } 1688 m = m_pullup(m, ip_off + sizeof(struct ip)); 1689 if (m == NULL) { 1690 *m_head = NULL; 1691 return (ENOBUFS); 1692 } 1693 ip = (struct ip *)(mtod(m, char *) + ip_off); 1694 poff = ip_off + (ip->ip_hl << 2); 1695 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1696 /* 1697 * XXX 1698 * AR81xx requires the first descriptor should 1699 * not include any TCP playload for TSO case. 1700 * (i.e. ethernet header + IP + TCP header only) 1701 * m_pullup(9) above will ensure this too. 1702 * However it's not correct if the first mbuf 1703 * of the chain does not use cluster. 1704 */ 1705 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1706 if (m == NULL) { 1707 *m_head = NULL; 1708 return (ENOBUFS); 1709 } 1710 ip = (struct ip *)(mtod(m, char *) + ip_off); 1711 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1712 m = m_pullup(m, poff + (tcp->th_off << 2)); 1713 if (m == NULL) { 1714 *m_head = NULL; 1715 return (ENOBUFS); 1716 } 1717 /* 1718 * AR81xx requires IP/TCP header size and offset as 1719 * well as TCP pseudo checksum which complicates 1720 * TSO configuration. I guess this comes from the 1721 * adherence to Microsoft NDIS Large Send 1722 * specification which requires insertion of 1723 * pseudo checksum by upper stack. The pseudo 1724 * checksum that NDIS refers to doesn't include 1725 * TCP payload length so ale(4) should recompute 1726 * the pseudo checksum here. Hopefully this wouldn't 1727 * be much burden on modern CPUs. 1728 * Reset IP checksum and recompute TCP pseudo 1729 * checksum as NDIS specification said. 1730 */ 1731 ip->ip_sum = 0; 1732 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1733 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1734 } 1735 *m_head = m; 1736 } 1737 1738 si = prod = sc->ale_cdata.ale_tx_prod; 1739 txd = &sc->ale_cdata.ale_txdesc[prod]; 1740 txd_last = txd; 1741 map = txd->tx_dmamap; 1742 1743 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1744 *m_head, txsegs, &nsegs, 0); 1745 if (error == EFBIG) { 1746 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1747 if (m == NULL) { 1748 m_freem(*m_head); 1749 *m_head = NULL; 1750 return (ENOMEM); 1751 } 1752 *m_head = m; 1753 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1754 *m_head, txsegs, &nsegs, 0); 1755 if (error != 0) { 1756 m_freem(*m_head); 1757 *m_head = NULL; 1758 return (error); 1759 } 1760 } else if (error != 0) 1761 return (error); 1762 if (nsegs == 0) { 1763 m_freem(*m_head); 1764 *m_head = NULL; 1765 return (EIO); 1766 } 1767 1768 /* Check descriptor overrun. */ 1769 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1770 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1771 return (ENOBUFS); 1772 } 1773 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1774 1775 m = *m_head; 1776 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1777 /* Request TSO and set MSS. */ 1778 cflags |= ALE_TD_TSO; 1779 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1780 /* Set IP/TCP header size. */ 1781 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1782 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1783 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1784 /* 1785 * AR81xx supports Tx custom checksum offload feature 1786 * that offloads single 16bit checksum computation. 1787 * So you can choose one among IP, TCP and UDP. 1788 * Normally driver sets checksum start/insertion 1789 * position from the information of TCP/UDP frame as 1790 * TCP/UDP checksum takes more time than that of IP. 1791 * However it seems that custom checksum offload 1792 * requires 4 bytes aligned Tx buffers due to hardware 1793 * bug. 1794 * AR81xx also supports explicit Tx checksum computation 1795 * if it is told that the size of IP header and TCP 1796 * header(for UDP, the header size does not matter 1797 * because it's fixed length). However with this scheme 1798 * TSO does not work so you have to choose one either 1799 * TSO or explicit Tx checksum offload. I chosen TSO 1800 * plus custom checksum offload with work-around which 1801 * will cover most common usage for this consumer 1802 * ethernet controller. The work-around takes a lot of 1803 * CPU cycles if Tx buffer is not aligned on 4 bytes 1804 * boundary, though. 1805 */ 1806 cflags |= ALE_TD_CXSUM; 1807 /* Set checksum start offset. */ 1808 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1809 /* Set checksum insertion position of TCP/UDP. */ 1810 cflags |= ((poff + m->m_pkthdr.csum_data) << 1811 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1812 } 1813 1814 /* Configure VLAN hardware tag insertion. */ 1815 if ((m->m_flags & M_VLANTAG) != 0) { 1816 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1817 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1818 cflags |= ALE_TD_INSERT_VLAN_TAG; 1819 } 1820 1821 i = 0; 1822 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1823 /* 1824 * Make sure the first fragment contains 1825 * only ethernet and IP/TCP header with options. 1826 */ 1827 hdrlen = poff + (tcp->th_off << 2); 1828 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1829 desc->addr = htole64(txsegs[i].ds_addr); 1830 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1831 desc->flags = htole32(cflags); 1832 sc->ale_cdata.ale_tx_cnt++; 1833 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1834 if (m->m_len - hdrlen > 0) { 1835 /* Handle remaining payload of the first fragment. */ 1836 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1837 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1838 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1839 vtag); 1840 desc->flags = htole32(cflags); 1841 sc->ale_cdata.ale_tx_cnt++; 1842 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1843 } 1844 i = 1; 1845 } 1846 for (; i < nsegs; i++) { 1847 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1848 desc->addr = htole64(txsegs[i].ds_addr); 1849 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1850 desc->flags = htole32(cflags); 1851 sc->ale_cdata.ale_tx_cnt++; 1852 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1853 } 1854 /* Update producer index. */ 1855 sc->ale_cdata.ale_tx_prod = prod; 1856 /* Set TSO header on the first descriptor. */ 1857 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1858 desc = &sc->ale_cdata.ale_tx_ring[si]; 1859 desc->flags |= htole32(ALE_TD_TSO_HDR); 1860 } 1861 1862 /* Finally set EOP on the last descriptor. */ 1863 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1864 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1865 desc->flags |= htole32(ALE_TD_EOP); 1866 1867 /* Swap dmamap of the first and the last. */ 1868 txd = &sc->ale_cdata.ale_txdesc[prod]; 1869 map = txd_last->tx_dmamap; 1870 txd_last->tx_dmamap = txd->tx_dmamap; 1871 txd->tx_dmamap = map; 1872 txd->tx_m = m; 1873 1874 /* Sync descriptors. */ 1875 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1876 sc->ale_cdata.ale_tx_ring_map, 1877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878 1879 return (0); 1880} 1881 1882static void 1883ale_start(struct ifnet *ifp) 1884{ 1885 struct ale_softc *sc; 1886 1887 sc = ifp->if_softc; 1888 ALE_LOCK(sc); 1889 ale_start_locked(ifp); 1890 ALE_UNLOCK(sc); 1891} 1892 1893static void 1894ale_start_locked(struct ifnet *ifp) 1895{ 1896 struct ale_softc *sc; 1897 struct mbuf *m_head; 1898 int enq; 1899 1900 sc = ifp->if_softc; 1901 1902 ALE_LOCK_ASSERT(sc); 1903 1904 /* Reclaim transmitted frames. */ 1905 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1906 ale_txeof(sc); 1907 1908 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1909 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1910 return; 1911 1912 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1913 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1914 if (m_head == NULL) 1915 break; 1916 /* 1917 * Pack the data into the transmit ring. If we 1918 * don't have room, set the OACTIVE flag and wait 1919 * for the NIC to drain the ring. 1920 */ 1921 if (ale_encap(sc, &m_head)) { 1922 if (m_head == NULL) 1923 break; 1924 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1925 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1926 break; 1927 } 1928 1929 enq++; 1930 /* 1931 * If there's a BPF listener, bounce a copy of this frame 1932 * to him. 1933 */ 1934 ETHER_BPF_MTAP(ifp, m_head); 1935 } 1936 1937 if (enq > 0) { 1938 /* Kick. */ 1939 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1940 sc->ale_cdata.ale_tx_prod); 1941 /* Set a timeout in case the chip goes out to lunch. */ 1942 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1943 } 1944} 1945 1946static void 1947ale_watchdog(struct ale_softc *sc) 1948{ 1949 struct ifnet *ifp; 1950 1951 ALE_LOCK_ASSERT(sc); 1952 1953 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1954 return; 1955 1956 ifp = sc->ale_ifp; 1957 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1958 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1959 ifp->if_oerrors++; 1960 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1961 ale_init_locked(sc); 1962 return; 1963 } 1964 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1965 ifp->if_oerrors++; 1966 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1967 ale_init_locked(sc); 1968 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1969 ale_start_locked(ifp); 1970} 1971 1972static int 1973ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1974{ 1975 struct ale_softc *sc; 1976 struct ifreq *ifr; 1977 struct mii_data *mii; 1978 int error, mask; 1979 1980 sc = ifp->if_softc; 1981 ifr = (struct ifreq *)data; 1982 error = 0; 1983 switch (cmd) { 1984 case SIOCSIFMTU: 1985 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1986 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1987 ifr->ifr_mtu > ETHERMTU)) 1988 error = EINVAL; 1989 else if (ifp->if_mtu != ifr->ifr_mtu) { 1990 ALE_LOCK(sc); 1991 ifp->if_mtu = ifr->ifr_mtu; 1992 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1993 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1994 ale_init_locked(sc); 1995 } 1996 ALE_UNLOCK(sc); 1997 } 1998 break; 1999 case SIOCSIFFLAGS: 2000 ALE_LOCK(sc); 2001 if ((ifp->if_flags & IFF_UP) != 0) { 2002 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2003 if (((ifp->if_flags ^ sc->ale_if_flags) 2004 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2005 ale_rxfilter(sc); 2006 } else { 2007 ale_init_locked(sc); 2008 } 2009 } else { 2010 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2011 ale_stop(sc); 2012 } 2013 sc->ale_if_flags = ifp->if_flags; 2014 ALE_UNLOCK(sc); 2015 break; 2016 case SIOCADDMULTI: 2017 case SIOCDELMULTI: 2018 ALE_LOCK(sc); 2019 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2020 ale_rxfilter(sc); 2021 ALE_UNLOCK(sc); 2022 break; 2023 case SIOCSIFMEDIA: 2024 case SIOCGIFMEDIA: 2025 mii = device_get_softc(sc->ale_miibus); 2026 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2027 break; 2028 case SIOCSIFCAP: 2029 ALE_LOCK(sc); 2030 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2031 if ((mask & IFCAP_TXCSUM) != 0 && 2032 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2033 ifp->if_capenable ^= IFCAP_TXCSUM; 2034 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2035 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2036 else 2037 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2038 } 2039 if ((mask & IFCAP_RXCSUM) != 0 && 2040 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2041 ifp->if_capenable ^= IFCAP_RXCSUM; 2042 if ((mask & IFCAP_TSO4) != 0 && 2043 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2044 ifp->if_capenable ^= IFCAP_TSO4; 2045 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2046 ifp->if_hwassist |= CSUM_TSO; 2047 else 2048 ifp->if_hwassist &= ~CSUM_TSO; 2049 } 2050 2051 if ((mask & IFCAP_WOL_MCAST) != 0 && 2052 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2053 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2054 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2055 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2056 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2057 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2058 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2059 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2060 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2061 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2062 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2063 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2064 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2065 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2066 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2067 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2068 ale_rxvlan(sc); 2069 } 2070 ALE_UNLOCK(sc); 2071 VLAN_CAPABILITIES(ifp); 2072 break; 2073 default: 2074 error = ether_ioctl(ifp, cmd, data); 2075 break; 2076 } 2077 2078 return (error); 2079} 2080 2081static void 2082ale_mac_config(struct ale_softc *sc) 2083{ 2084 struct mii_data *mii; 2085 uint32_t reg; 2086 2087 ALE_LOCK_ASSERT(sc); 2088 2089 mii = device_get_softc(sc->ale_miibus); 2090 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2091 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2092 MAC_CFG_SPEED_MASK); 2093 /* Reprogram MAC with resolved speed/duplex. */ 2094 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2095 case IFM_10_T: 2096 case IFM_100_TX: 2097 reg |= MAC_CFG_SPEED_10_100; 2098 break; 2099 case IFM_1000_T: 2100 reg |= MAC_CFG_SPEED_1000; 2101 break; 2102 } 2103 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2104 reg |= MAC_CFG_FULL_DUPLEX; 2105 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2106 reg |= MAC_CFG_TX_FC; 2107 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2108 reg |= MAC_CFG_RX_FC; 2109 } 2110 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2111} 2112 2113static void 2114ale_stats_clear(struct ale_softc *sc) 2115{ 2116 struct smb sb; 2117 uint32_t *reg; 2118 int i; 2119 2120 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2121 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2122 i += sizeof(uint32_t); 2123 } 2124 /* Read Tx statistics. */ 2125 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2126 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2127 i += sizeof(uint32_t); 2128 } 2129} 2130 2131static void 2132ale_stats_update(struct ale_softc *sc) 2133{ 2134 struct ale_hw_stats *stat; 2135 struct smb sb, *smb; 2136 struct ifnet *ifp; 2137 uint32_t *reg; 2138 int i; 2139 2140 ALE_LOCK_ASSERT(sc); 2141 2142 ifp = sc->ale_ifp; 2143 stat = &sc->ale_stats; 2144 smb = &sb; 2145 2146 /* Read Rx statistics. */ 2147 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2148 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2149 i += sizeof(uint32_t); 2150 } 2151 /* Read Tx statistics. */ 2152 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2153 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2154 i += sizeof(uint32_t); 2155 } 2156 2157 /* Rx stats. */ 2158 stat->rx_frames += smb->rx_frames; 2159 stat->rx_bcast_frames += smb->rx_bcast_frames; 2160 stat->rx_mcast_frames += smb->rx_mcast_frames; 2161 stat->rx_pause_frames += smb->rx_pause_frames; 2162 stat->rx_control_frames += smb->rx_control_frames; 2163 stat->rx_crcerrs += smb->rx_crcerrs; 2164 stat->rx_lenerrs += smb->rx_lenerrs; 2165 stat->rx_bytes += smb->rx_bytes; 2166 stat->rx_runts += smb->rx_runts; 2167 stat->rx_fragments += smb->rx_fragments; 2168 stat->rx_pkts_64 += smb->rx_pkts_64; 2169 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2170 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2171 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2172 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2173 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2174 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2175 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2176 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2177 stat->rx_rrs_errs += smb->rx_rrs_errs; 2178 stat->rx_alignerrs += smb->rx_alignerrs; 2179 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2180 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2181 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2182 2183 /* Tx stats. */ 2184 stat->tx_frames += smb->tx_frames; 2185 stat->tx_bcast_frames += smb->tx_bcast_frames; 2186 stat->tx_mcast_frames += smb->tx_mcast_frames; 2187 stat->tx_pause_frames += smb->tx_pause_frames; 2188 stat->tx_excess_defer += smb->tx_excess_defer; 2189 stat->tx_control_frames += smb->tx_control_frames; 2190 stat->tx_deferred += smb->tx_deferred; 2191 stat->tx_bytes += smb->tx_bytes; 2192 stat->tx_pkts_64 += smb->tx_pkts_64; 2193 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2194 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2195 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2196 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2197 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2198 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2199 stat->tx_single_colls += smb->tx_single_colls; 2200 stat->tx_multi_colls += smb->tx_multi_colls; 2201 stat->tx_late_colls += smb->tx_late_colls; 2202 stat->tx_excess_colls += smb->tx_excess_colls; 2203 stat->tx_abort += smb->tx_abort; 2204 stat->tx_underrun += smb->tx_underrun; 2205 stat->tx_desc_underrun += smb->tx_desc_underrun; 2206 stat->tx_lenerrs += smb->tx_lenerrs; 2207 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2208 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2209 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2210 2211 /* Update counters in ifnet. */ 2212 ifp->if_opackets += smb->tx_frames; 2213 2214 ifp->if_collisions += smb->tx_single_colls + 2215 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2216 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2217 2218 /* 2219 * XXX 2220 * tx_pkts_truncated counter looks suspicious. It constantly 2221 * increments with no sign of Tx errors. This may indicate 2222 * the counter name is not correct one so I've removed the 2223 * counter in output errors. 2224 */ 2225 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2226 smb->tx_underrun; 2227 2228 ifp->if_ipackets += smb->rx_frames; 2229 2230 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2231 smb->rx_runts + smb->rx_pkts_truncated + 2232 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2233 smb->rx_alignerrs; 2234} 2235 2236static int 2237ale_intr(void *arg) 2238{ 2239 struct ale_softc *sc; 2240 uint32_t status; 2241 2242 sc = (struct ale_softc *)arg; 2243 2244 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2245 if ((status & ALE_INTRS) == 0) 2246 return (FILTER_STRAY); 2247 /* Disable interrupts. */ 2248 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2249 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2250 2251 return (FILTER_HANDLED); 2252} 2253 2254static void 2255ale_int_task(void *arg, int pending) 2256{ 2257 struct ale_softc *sc; 2258 struct ifnet *ifp; 2259 uint32_t status; 2260 int more; 2261 2262 sc = (struct ale_softc *)arg; 2263 2264 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2265 ALE_LOCK(sc); 2266 if (sc->ale_morework != 0) 2267 status |= INTR_RX_PKT; 2268 if ((status & ALE_INTRS) == 0) 2269 goto done; 2270 2271 /* Acknowledge interrupts but still disable interrupts. */ 2272 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2273 2274 ifp = sc->ale_ifp; 2275 more = 0; 2276 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2277 more = ale_rxeof(sc, sc->ale_process_limit); 2278 if (more == EAGAIN) 2279 sc->ale_morework = 1; 2280 else if (more == EIO) { 2281 sc->ale_stats.reset_brk_seq++; 2282 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2283 ale_init_locked(sc); 2284 ALE_UNLOCK(sc); 2285 return; 2286 } 2287 2288 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2289 if ((status & INTR_DMA_RD_TO_RST) != 0) 2290 device_printf(sc->ale_dev, 2291 "DMA read error! -- resetting\n"); 2292 if ((status & INTR_DMA_WR_TO_RST) != 0) 2293 device_printf(sc->ale_dev, 2294 "DMA write error! -- resetting\n"); 2295 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2296 ale_init_locked(sc); 2297 ALE_UNLOCK(sc); 2298 return; 2299 } 2300 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2301 ale_start_locked(ifp); 2302 } 2303 2304 if (more == EAGAIN || 2305 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2306 ALE_UNLOCK(sc); 2307 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2308 return; 2309 } 2310 2311done: 2312 ALE_UNLOCK(sc); 2313 2314 /* Re-enable interrupts. */ 2315 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2316} 2317 2318static void 2319ale_txeof(struct ale_softc *sc) 2320{ 2321 struct ifnet *ifp; 2322 struct ale_txdesc *txd; 2323 uint32_t cons, prod; 2324 int prog; 2325 2326 ALE_LOCK_ASSERT(sc); 2327 2328 ifp = sc->ale_ifp; 2329 2330 if (sc->ale_cdata.ale_tx_cnt == 0) 2331 return; 2332 2333 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2334 sc->ale_cdata.ale_tx_ring_map, 2335 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2336 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2337 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2338 sc->ale_cdata.ale_tx_cmb_map, 2339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2340 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2341 } else 2342 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2343 cons = sc->ale_cdata.ale_tx_cons; 2344 /* 2345 * Go through our Tx list and free mbufs for those 2346 * frames which have been transmitted. 2347 */ 2348 for (prog = 0; cons != prod; prog++, 2349 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2350 if (sc->ale_cdata.ale_tx_cnt <= 0) 2351 break; 2352 prog++; 2353 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2354 sc->ale_cdata.ale_tx_cnt--; 2355 txd = &sc->ale_cdata.ale_txdesc[cons]; 2356 if (txd->tx_m != NULL) { 2357 /* Reclaim transmitted mbufs. */ 2358 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2359 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2360 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2361 txd->tx_dmamap); 2362 m_freem(txd->tx_m); 2363 txd->tx_m = NULL; 2364 } 2365 } 2366 2367 if (prog > 0) { 2368 sc->ale_cdata.ale_tx_cons = cons; 2369 /* 2370 * Unarm watchdog timer only when there is no pending 2371 * Tx descriptors in queue. 2372 */ 2373 if (sc->ale_cdata.ale_tx_cnt == 0) 2374 sc->ale_watchdog_timer = 0; 2375 } 2376} 2377 2378static void 2379ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2380 uint32_t length, uint32_t *prod) 2381{ 2382 struct ale_rx_page *rx_page; 2383 2384 rx_page = *page; 2385 /* Update consumer position. */ 2386 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2387 ALE_RX_PAGE_ALIGN); 2388 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2389 /* 2390 * End of Rx page reached, let hardware reuse 2391 * this page. 2392 */ 2393 rx_page->cons = 0; 2394 *rx_page->cmb_addr = 0; 2395 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2397 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2398 RXF_VALID); 2399 /* Switch to alternate Rx page. */ 2400 sc->ale_cdata.ale_rx_curp ^= 1; 2401 rx_page = *page = 2402 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2403 /* Page flipped, sync CMB and Rx page. */ 2404 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2405 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2406 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2407 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2408 /* Sync completed, cache updated producer index. */ 2409 *prod = *rx_page->cmb_addr; 2410 } 2411} 2412 2413 2414/* 2415 * It seems that AR81xx controller can compute partial checksum. 2416 * The partial checksum value can be used to accelerate checksum 2417 * computation for fragmented TCP/UDP packets. Upper network stack 2418 * already takes advantage of the partial checksum value in IP 2419 * reassembly stage. But I'm not sure the correctness of the 2420 * partial hardware checksum assistance due to lack of data sheet. 2421 * In addition, the Rx feature of controller that requires copying 2422 * for every frames effectively nullifies one of most nice offload 2423 * capability of controller. 2424 */ 2425static void 2426ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2427{ 2428 struct ifnet *ifp; 2429 struct ip *ip; 2430 char *p; 2431 2432 ifp = sc->ale_ifp; 2433 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2434 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2435 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2436 2437 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2438 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2439 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2440 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2441 m->m_pkthdr.csum_flags |= 2442 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2443 m->m_pkthdr.csum_data = 0xffff; 2444 } 2445 } else { 2446 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2447 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2448 p = mtod(m, char *); 2449 p += ETHER_HDR_LEN; 2450 if ((status & ALE_RD_802_3) != 0) 2451 p += LLC_SNAPFRAMELEN; 2452 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2453 (status & ALE_RD_VLAN) != 0) 2454 p += ETHER_VLAN_ENCAP_LEN; 2455 ip = (struct ip *)p; 2456 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2457 return; 2458 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2459 CSUM_PSEUDO_HDR; 2460 m->m_pkthdr.csum_data = 0xffff; 2461 } 2462 } 2463 /* 2464 * Don't mark bad checksum for TCP/UDP frames 2465 * as fragmented frames may always have set 2466 * bad checksummed bit of frame status. 2467 */ 2468} 2469 2470/* Process received frames. */ 2471static int 2472ale_rxeof(struct ale_softc *sc, int count) 2473{ 2474 struct ale_rx_page *rx_page; 2475 struct rx_rs *rs; 2476 struct ifnet *ifp; 2477 struct mbuf *m; 2478 uint32_t length, prod, seqno, status, vtags; 2479 int prog; 2480 2481 ifp = sc->ale_ifp; 2482 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2483 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2484 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2485 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2487 /* 2488 * Don't directly access producer index as hardware may 2489 * update it while Rx handler is in progress. It would 2490 * be even better if there is a way to let hardware 2491 * know how far driver processed its received frames. 2492 * Alternatively, hardware could provide a way to disable 2493 * CMB updates until driver acknowledges the end of CMB 2494 * access. 2495 */ 2496 prod = *rx_page->cmb_addr; 2497 for (prog = 0; prog < count; prog++) { 2498 if (rx_page->cons >= prod) 2499 break; 2500 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2501 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2502 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2503 /* 2504 * Normally I believe this should not happen unless 2505 * severe driver bug or corrupted memory. However 2506 * it seems to happen under certain conditions which 2507 * is triggered by abrupt Rx events such as initiation 2508 * of bulk transfer of remote host. It's not easy to 2509 * reproduce this and I doubt it could be related 2510 * with FIFO overflow of hardware or activity of Tx 2511 * CMB updates. I also remember similar behaviour 2512 * seen on RealTek 8139 which uses resembling Rx 2513 * scheme. 2514 */ 2515 if (bootverbose) 2516 device_printf(sc->ale_dev, 2517 "garbled seq: %u, expected: %u -- " 2518 "resetting!\n", seqno, 2519 sc->ale_cdata.ale_rx_seqno); 2520 return (EIO); 2521 } 2522 /* Frame received. */ 2523 sc->ale_cdata.ale_rx_seqno++; 2524 length = ALE_RX_BYTES(le32toh(rs->length)); 2525 status = le32toh(rs->flags); 2526 if ((status & ALE_RD_ERROR) != 0) { 2527 /* 2528 * We want to pass the following frames to upper 2529 * layer regardless of error status of Rx return 2530 * status. 2531 * 2532 * o IP/TCP/UDP checksum is bad. 2533 * o frame length and protocol specific length 2534 * does not match. 2535 */ 2536 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2537 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2538 ALE_RD_TRUNC)) != 0) { 2539 ale_rx_update_page(sc, &rx_page, length, &prod); 2540 continue; 2541 } 2542 } 2543 /* 2544 * m_devget(9) is major bottle-neck of ale(4)(It comes 2545 * from hardware limitation). For jumbo frames we could 2546 * get a slightly better performance if driver use 2547 * m_getjcl(9) with proper buffer size argument. However 2548 * that would make code more complicated and I don't 2549 * think users would expect good Rx performance numbers 2550 * on these low-end consumer ethernet controller. 2551 */ 2552 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2553 ETHER_ALIGN, ifp, NULL); 2554 if (m == NULL) { 2555 ifp->if_iqdrops++; 2556 ale_rx_update_page(sc, &rx_page, length, &prod); 2557 continue; 2558 } 2559 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2560 (status & ALE_RD_IPV4) != 0) 2561 ale_rxcsum(sc, m, status); 2562 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2563 (status & ALE_RD_VLAN) != 0) { 2564 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2565 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2566 m->m_flags |= M_VLANTAG; 2567 } 2568 2569 /* Pass it to upper layer. */ 2570 ALE_UNLOCK(sc); 2571 (*ifp->if_input)(ifp, m); 2572 ALE_LOCK(sc); 2573 2574 ale_rx_update_page(sc, &rx_page, length, &prod); 2575 } 2576 2577 return (count > 0 ? 0 : EAGAIN); 2578} 2579 2580static void 2581ale_tick(void *arg) 2582{ 2583 struct ale_softc *sc; 2584 struct mii_data *mii; 2585 2586 sc = (struct ale_softc *)arg; 2587 2588 ALE_LOCK_ASSERT(sc); 2589 2590 mii = device_get_softc(sc->ale_miibus); 2591 mii_tick(mii); 2592 ale_stats_update(sc); 2593 /* 2594 * Reclaim Tx buffers that have been transferred. It's not 2595 * needed here but it would release allocated mbuf chains 2596 * faster and limit the maximum delay to a hz. 2597 */ 2598 ale_txeof(sc); 2599 ale_watchdog(sc); 2600 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2601} 2602 2603static void 2604ale_reset(struct ale_softc *sc) 2605{ 2606 uint32_t reg; 2607 int i; 2608 2609 /* Initialize PCIe module. From Linux. */ 2610 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2611 2612 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2613 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2614 DELAY(10); 2615 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2616 break; 2617 } 2618 if (i == 0) 2619 device_printf(sc->ale_dev, "master reset timeout!\n"); 2620 2621 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2622 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2623 break; 2624 DELAY(10); 2625 } 2626 2627 if (i == 0) 2628 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2629} 2630 2631static void 2632ale_init(void *xsc) 2633{ 2634 struct ale_softc *sc; 2635 2636 sc = (struct ale_softc *)xsc; 2637 ALE_LOCK(sc); 2638 ale_init_locked(sc); 2639 ALE_UNLOCK(sc); 2640} 2641 2642static void 2643ale_init_locked(struct ale_softc *sc) 2644{ 2645 struct ifnet *ifp; 2646 struct mii_data *mii; 2647 uint8_t eaddr[ETHER_ADDR_LEN]; 2648 bus_addr_t paddr; 2649 uint32_t reg, rxf_hi, rxf_lo; 2650 2651 ALE_LOCK_ASSERT(sc); 2652 2653 ifp = sc->ale_ifp; 2654 mii = device_get_softc(sc->ale_miibus); 2655 2656 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2657 return; 2658 /* 2659 * Cancel any pending I/O. 2660 */ 2661 ale_stop(sc); 2662 /* 2663 * Reset the chip to a known state. 2664 */ 2665 ale_reset(sc); 2666 /* Initialize Tx descriptors, DMA memory blocks. */ 2667 ale_init_rx_pages(sc); 2668 ale_init_tx_ring(sc); 2669 2670 /* Reprogram the station address. */ 2671 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2672 CSR_WRITE_4(sc, ALE_PAR0, 2673 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2674 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2675 /* 2676 * Clear WOL status and disable all WOL feature as WOL 2677 * would interfere Rx operation under normal environments. 2678 */ 2679 CSR_READ_4(sc, ALE_WOL_CFG); 2680 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2681 /* 2682 * Set Tx descriptor/RXF0/CMB base addresses. They share 2683 * the same high address part of DMAable region. 2684 */ 2685 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2686 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2687 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2688 CSR_WRITE_4(sc, ALE_TPD_CNT, 2689 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2690 /* Set Rx page base address, note we use single queue. */ 2691 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2692 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2693 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2694 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2695 /* Set Tx/Rx CMB addresses. */ 2696 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2697 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2698 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2699 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2700 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2701 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2702 /* Mark RXF0 is valid. */ 2703 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2704 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2705 /* 2706 * No need to initialize RFX1/RXF2/RXF3. We don't use 2707 * multi-queue yet. 2708 */ 2709 2710 /* Set Rx page size, excluding guard frame size. */ 2711 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2712 /* Tell hardware that we're ready to load DMA blocks. */ 2713 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2714 2715 /* Set Rx/Tx interrupt trigger threshold. */ 2716 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2717 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2718 /* 2719 * XXX 2720 * Set interrupt trigger timer, its purpose and relation 2721 * with interrupt moderation mechanism is not clear yet. 2722 */ 2723 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2724 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2725 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2726 2727 /* Configure interrupt moderation timer. */ 2728 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2729 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2730 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2731 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2732 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2733 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2734 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2735 reg |= MASTER_IM_RX_TIMER_ENB; 2736 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2737 reg |= MASTER_IM_TX_TIMER_ENB; 2738 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2739 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2740 2741 /* Set Maximum frame size of controller. */ 2742 if (ifp->if_mtu < ETHERMTU) 2743 sc->ale_max_frame_size = ETHERMTU; 2744 else 2745 sc->ale_max_frame_size = ifp->if_mtu; 2746 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2747 ETHER_CRC_LEN; 2748 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2749 /* Configure IPG/IFG parameters. */ 2750 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2751 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2752 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2753 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2754 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2755 /* Set parameters for half-duplex media. */ 2756 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2757 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2758 HDPX_CFG_LCOL_MASK) | 2759 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2760 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2761 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2762 HDPX_CFG_ABEBT_MASK) | 2763 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2764 HDPX_CFG_JAMIPG_MASK)); 2765 2766 /* Configure Tx jumbo frame parameters. */ 2767 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2768 if (ifp->if_mtu < ETHERMTU) 2769 reg = sc->ale_max_frame_size; 2770 else if (ifp->if_mtu < 6 * 1024) 2771 reg = (sc->ale_max_frame_size * 2) / 3; 2772 else 2773 reg = sc->ale_max_frame_size / 2; 2774 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2775 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2776 TX_JUMBO_THRESH_UNIT_SHIFT); 2777 } 2778 /* Configure TxQ. */ 2779 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2780 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2781 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2782 TXQ_CFG_TPD_BURST_MASK; 2783 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2784 2785 /* Configure Rx jumbo frame & flow control parameters. */ 2786 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2787 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2788 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2789 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2790 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2791 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2792 RX_JUMBO_LKAH_MASK)); 2793 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2794 rxf_hi = (reg * 7) / 10; 2795 rxf_lo = (reg * 3)/ 10; 2796 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2797 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2798 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2799 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2800 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2801 } 2802 2803 /* Disable RSS. */ 2804 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2805 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2806 2807 /* Configure RxQ. */ 2808 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2809 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2810 2811 /* Configure DMA parameters. */ 2812 reg = 0; 2813 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2814 reg |= DMA_CFG_TXCMB_ENB; 2815 CSR_WRITE_4(sc, ALE_DMA_CFG, 2816 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2817 sc->ale_dma_rd_burst | reg | 2818 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2819 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2820 DMA_CFG_RD_DELAY_CNT_MASK) | 2821 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2822 DMA_CFG_WR_DELAY_CNT_MASK)); 2823 2824 /* 2825 * Hardware can be configured to issue SMB interrupt based 2826 * on programmed interval. Since there is a callout that is 2827 * invoked for every hz in driver we use that instead of 2828 * relying on periodic SMB interrupt. 2829 */ 2830 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2831 /* Clear MAC statistics. */ 2832 ale_stats_clear(sc); 2833 2834 /* 2835 * Configure Tx/Rx MACs. 2836 * - Auto-padding for short frames. 2837 * - Enable CRC generation. 2838 * Actual reconfiguration of MAC for resolved speed/duplex 2839 * is followed after detection of link establishment. 2840 * AR81xx always does checksum computation regardless of 2841 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2842 * cause Rx handling issue for fragmented IP datagrams due 2843 * to silicon bug. 2844 */ 2845 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2846 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2847 MAC_CFG_PREAMBLE_MASK); 2848 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2849 reg |= MAC_CFG_SPEED_10_100; 2850 else 2851 reg |= MAC_CFG_SPEED_1000; 2852 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2853 2854 /* Set up the receive filter. */ 2855 ale_rxfilter(sc); 2856 ale_rxvlan(sc); 2857 2858 /* Acknowledge all pending interrupts and clear it. */ 2859 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2860 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2861 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2862 2863 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2864 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2865 2866 sc->ale_flags &= ~ALE_FLAG_LINK; 2867 /* Switch to the current media. */ 2868 mii_mediachg(mii); 2869 2870 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2871} 2872 2873static void 2874ale_stop(struct ale_softc *sc) 2875{ 2876 struct ifnet *ifp; 2877 struct ale_txdesc *txd; 2878 uint32_t reg; 2879 int i; 2880 2881 ALE_LOCK_ASSERT(sc); 2882 /* 2883 * Mark the interface down and cancel the watchdog timer. 2884 */ 2885 ifp = sc->ale_ifp; 2886 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2887 sc->ale_flags &= ~ALE_FLAG_LINK; 2888 callout_stop(&sc->ale_tick_ch); 2889 sc->ale_watchdog_timer = 0; 2890 ale_stats_update(sc); 2891 /* Disable interrupts. */ 2892 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2893 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2894 /* Disable queue processing and DMA. */ 2895 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2896 reg &= ~TXQ_CFG_ENB; 2897 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2898 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2899 reg &= ~RXQ_CFG_ENB; 2900 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2901 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2902 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2903 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2904 DELAY(1000); 2905 /* Stop Rx/Tx MACs. */ 2906 ale_stop_mac(sc); 2907 /* Disable interrupts which might be touched in taskq handler. */ 2908 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2909 2910 /* 2911 * Free TX mbufs still in the queues. 2912 */ 2913 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2914 txd = &sc->ale_cdata.ale_txdesc[i]; 2915 if (txd->tx_m != NULL) { 2916 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2917 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2918 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2919 txd->tx_dmamap); 2920 m_freem(txd->tx_m); 2921 txd->tx_m = NULL; 2922 } 2923 } 2924} 2925 2926static void 2927ale_stop_mac(struct ale_softc *sc) 2928{ 2929 uint32_t reg; 2930 int i; 2931 2932 ALE_LOCK_ASSERT(sc); 2933 2934 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2935 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2936 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2937 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2938 } 2939 2940 for (i = ALE_TIMEOUT; i > 0; i--) { 2941 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2942 if (reg == 0) 2943 break; 2944 DELAY(10); 2945 } 2946 if (i == 0) 2947 device_printf(sc->ale_dev, 2948 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2949} 2950 2951static void 2952ale_init_tx_ring(struct ale_softc *sc) 2953{ 2954 struct ale_txdesc *txd; 2955 int i; 2956 2957 ALE_LOCK_ASSERT(sc); 2958 2959 sc->ale_cdata.ale_tx_prod = 0; 2960 sc->ale_cdata.ale_tx_cons = 0; 2961 sc->ale_cdata.ale_tx_cnt = 0; 2962 2963 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2964 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2965 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2966 txd = &sc->ale_cdata.ale_txdesc[i]; 2967 txd->tx_m = NULL; 2968 } 2969 *sc->ale_cdata.ale_tx_cmb = 0; 2970 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2971 sc->ale_cdata.ale_tx_cmb_map, 2972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2973 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2974 sc->ale_cdata.ale_tx_ring_map, 2975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2976} 2977 2978static void 2979ale_init_rx_pages(struct ale_softc *sc) 2980{ 2981 struct ale_rx_page *rx_page; 2982 int i; 2983 2984 ALE_LOCK_ASSERT(sc); 2985 2986 sc->ale_morework = 0; 2987 sc->ale_cdata.ale_rx_seqno = 0; 2988 sc->ale_cdata.ale_rx_curp = 0; 2989 2990 for (i = 0; i < ALE_RX_PAGES; i++) { 2991 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2992 bzero(rx_page->page_addr, sc->ale_pagesize); 2993 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2994 rx_page->cons = 0; 2995 *rx_page->cmb_addr = 0; 2996 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2998 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3000 } 3001} 3002 3003static void 3004ale_rxvlan(struct ale_softc *sc) 3005{ 3006 struct ifnet *ifp; 3007 uint32_t reg; 3008 3009 ALE_LOCK_ASSERT(sc); 3010 3011 ifp = sc->ale_ifp; 3012 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3013 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3014 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3015 reg |= MAC_CFG_VLAN_TAG_STRIP; 3016 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3017} 3018 3019static void 3020ale_rxfilter(struct ale_softc *sc) 3021{ 3022 struct ifnet *ifp; 3023 struct ifmultiaddr *ifma; 3024 uint32_t crc; 3025 uint32_t mchash[2]; 3026 uint32_t rxcfg; 3027 3028 ALE_LOCK_ASSERT(sc); 3029 3030 ifp = sc->ale_ifp; 3031 3032 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3033 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3034 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3035 rxcfg |= MAC_CFG_BCAST; 3036 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3037 if ((ifp->if_flags & IFF_PROMISC) != 0) 3038 rxcfg |= MAC_CFG_PROMISC; 3039 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3040 rxcfg |= MAC_CFG_ALLMULTI; 3041 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3042 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3043 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3044 return; 3045 } 3046 3047 /* Program new filter. */ 3048 bzero(mchash, sizeof(mchash)); 3049 3050 if_maddr_rlock(ifp); 3051 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3052 if (ifma->ifma_addr->sa_family != AF_LINK) 3053 continue; 3054 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3055 ifma->ifma_addr), ETHER_ADDR_LEN); 3056 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3057 } 3058 if_maddr_runlock(ifp); 3059 3060 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3061 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3062 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3063} 3064 3065static int 3066sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3067{ 3068 int error, value; 3069 3070 if (arg1 == NULL) 3071 return (EINVAL); 3072 value = *(int *)arg1; 3073 error = sysctl_handle_int(oidp, &value, 0, req); 3074 if (error || req->newptr == NULL) 3075 return (error); 3076 if (value < low || value > high) 3077 return (EINVAL); 3078 *(int *)arg1 = value; 3079 3080 return (0); 3081} 3082 3083static int 3084sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3085{ 3086 return (sysctl_int_range(oidp, arg1, arg2, req, 3087 ALE_PROC_MIN, ALE_PROC_MAX)); 3088} 3089 3090static int 3091sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3092{ 3093 3094 return (sysctl_int_range(oidp, arg1, arg2, req, 3095 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3096} 3097