1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30/* 31 * Clocks and power control driver for Freescale i.MX6 family of SoCs. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/kernel.h> 37#include <sys/module.h> 38#include <sys/bus.h> 39#include <sys/rman.h> 40 41#include <dev/ofw/ofw_bus.h> 42#include <dev/ofw/ofw_bus_subr.h> 43 44#include <machine/bus.h> 45 46#include <arm/freescale/imx/imx6_anatopreg.h> 47#include <arm/freescale/imx/imx6_anatopvar.h> 48#include <arm/freescale/imx/imx6_ccmreg.h> 49#include <arm/freescale/imx/imx_machdep.h> 50#include <arm/freescale/imx/imx_ccmvar.h> 51 52#ifndef CCGR_CLK_MODE_ALWAYS 53#define CCGR_CLK_MODE_OFF 0 54#define CCGR_CLK_MODE_RUNMODE 1 55#define CCGR_CLK_MODE_ALWAYS 3 56#endif 57 58struct ccm_softc { 59 device_t dev; 60 struct resource *mem_res; 61}; 62 63static struct ccm_softc *ccm_sc; 64 65static inline uint32_t 66RD4(struct ccm_softc *sc, bus_size_t off) 67{ 68 69 return (bus_read_4(sc->mem_res, off)); 70} 71 72static inline void 73WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) 74{ 75 76 bus_write_4(sc->mem_res, off, val); 77} 78 79static int 80ccm_detach(device_t dev) 81{ 82 struct ccm_softc *sc; 83 84 sc = device_get_softc(dev); 85 86 if (sc->mem_res != NULL) 87 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 88 89 return (0); 90} 91 92static int 93ccm_attach(device_t dev) 94{ 95 struct ccm_softc *sc; 96 int err, rid; 97 uint32_t reg; 98 99 sc = device_get_softc(dev); 100 err = 0; 101 102 /* Allocate bus_space resources. */ 103 rid = 0; 104 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 105 RF_ACTIVE); 106 if (sc->mem_res == NULL) { 107 device_printf(dev, "Cannot allocate memory resources\n"); 108 err = ENXIO; 109 goto out; 110 } 111 112 ccm_sc = sc; 113 114 /* 115 * Configure the Low Power Mode setting to leave the ARM core power on 116 * when a WFI instruction is executed. This lets the MPCore timers and 117 * GIC continue to run, which is helpful when the only thing that can 118 * wake you up is an MPCore Private Timer interrupt delivered via GIC. 119 * 120 * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be 121 * required when the LPM bits are set to LPM_RUN. But experimentally 122 * I've experienced a fairly rare lockup when not setting it. I was 123 * unable to prove conclusively that the lockup was related to power 124 * management or that this definitively fixes it. Revisit this. 125 */ 126 reg = RD4(sc, CCM_CGPR); 127 reg |= CCM_CGPR_INT_MEM_CLK_LPM; 128 WR4(sc, CCM_CGPR, reg); 129 reg = RD4(sc, CCM_CLPCR); 130 reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; 131 WR4(sc, CCM_CLPCR, reg); 132 133 err = 0; 134 135out: 136 137 if (err != 0) 138 ccm_detach(dev); 139 140 return (err); 141} 142 143static int 144ccm_probe(device_t dev) 145{ 146 147 if (!ofw_bus_status_okay(dev)) 148 return (ENXIO); 149 150 if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) 151 return (ENXIO); 152 153 device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); 154 155 return (BUS_PROBE_DEFAULT); 156} 157 158void 159imx_ccm_usb_enable(device_t _usbdev) 160{ 161 162 /* 163 * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for 164 * shifting and masking here, just set the low-order two bits to ALWAYS. 165 */ 166 WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); 167} 168 169void 170imx_ccm_usbphy_enable(device_t _phydev) 171{ 172 /* 173 * XXX Which unit? 174 * Right now it's not clear how to figure from fdt data which phy unit 175 * we're supposed to operate on. Until this is worked out, just enable 176 * both PHYs. 177 */ 178#if 0 179 int phy_num, regoff; 180 181 phy_num = 0; /* XXX */ 182 183 switch (phy_num) { 184 case 0: 185 regoff = 0; 186 break; 187 case 1: 188 regoff = 0x10; 189 break; 190 default: 191 device_printf(ccm_sc->dev, "Bad PHY number %u,\n", 192 phy_num); 193 return; 194 } 195 196 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, 197 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 198 IMX6_ANALOG_CCM_PLL_USB_POWER | 199 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 200#else 201 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, 202 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 203 IMX6_ANALOG_CCM_PLL_USB_POWER | 204 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 205 206 imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, 207 IMX6_ANALOG_CCM_PLL_USB_ENABLE | 208 IMX6_ANALOG_CCM_PLL_USB_POWER | 209 IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); 210#endif 211} 212 213uint32_t 214imx_ccm_ipg_hz(void) 215{ 216 217 return (66000000); 218} 219 220uint32_t 221imx_ccm_perclk_hz(void) 222{ 223 224 return (66000000); 225} 226 227uint32_t 228imx_ccm_sdhci_hz(void) 229{ 230 231 return (200000000); 232} 233 234uint32_t 235imx_ccm_uart_hz(void) 236{ 237 238 return (80000000); 239} 240 241static device_method_t ccm_methods[] = { 242 /* Device interface */ 243 DEVMETHOD(device_probe, ccm_probe), 244 DEVMETHOD(device_attach, ccm_attach), 245 DEVMETHOD(device_detach, ccm_detach), 246 247 DEVMETHOD_END 248}; 249 250static driver_t ccm_driver = { 251 "ccm", 252 ccm_methods, 253 sizeof(struct ccm_softc) 254}; 255 256static devclass_t ccm_devclass; 257 258DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0); 259 260