1/*-
2 * Copyright (c) 2001 Tsubai Masanari.
3 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
4 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD$");
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/lock.h>
36#include <sys/module.h>
37#include <sys/mutex.h>
38#include <sys/bus.h>
39#include <machine/resource.h>
40#include <machine/bus.h>
41#include <sys/rman.h>
42#include <sys/sysctl.h>
43
44#include <dev/iicbus/iicbus.h>
45#include <dev/iicbus/iiconf.h>
46#include <dev/ofw/ofw_bus.h>
47#include <dev/ofw/ofw_bus_subr.h>
48
49#include <arm/broadcom/bcm2835/bcm2835_gpio.h>
50#include <arm/broadcom/bcm2835/bcm2835_bscreg.h>
51#include <arm/broadcom/bcm2835/bcm2835_bscvar.h>
52
53#include "iicbus_if.h"
54
55static void bcm_bsc_intr(void *);
56
57static void
58bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask,
59	uint32_t value)
60{
61	uint32_t reg;
62
63	mtx_assert(&sc->sc_mtx, MA_OWNED);
64	reg = BCM_BSC_READ(sc, off);
65	reg &= ~mask;
66	reg |= value;
67	BCM_BSC_WRITE(sc, off, reg);
68}
69
70static int
71bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS)
72{
73	struct bcm_bsc_softc *sc;
74	uint32_t clk;
75	int error;
76
77	sc = (struct bcm_bsc_softc *)arg1;
78
79	BCM_BSC_LOCK(sc);
80	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
81	BCM_BSC_UNLOCK(sc);
82	clk &= 0xffff;
83	if (clk == 0)
84		clk = 32768;
85	clk = BCM_BSC_CORE_CLK / clk;
86	error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
87	if (error != 0 || req->newptr == NULL)
88		return (error);
89
90	clk = BCM_BSC_CORE_CLK / clk;
91	if (clk % 2)
92		clk--;
93	if (clk > 0xffff)
94		clk = 0xffff;
95	BCM_BSC_LOCK(sc);
96	BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, clk);
97	BCM_BSC_UNLOCK(sc);
98
99	return (0);
100}
101
102static int
103bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS)
104{
105	struct bcm_bsc_softc *sc;
106	uint32_t clkt;
107	int error;
108
109	sc = (struct bcm_bsc_softc *)arg1;
110
111	BCM_BSC_LOCK(sc);
112	clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT);
113	BCM_BSC_UNLOCK(sc);
114	clkt &= 0xffff;
115	error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req);
116	if (error != 0 || req->newptr == NULL)
117		return (error);
118
119	BCM_BSC_LOCK(sc);
120	BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff);
121	BCM_BSC_UNLOCK(sc);
122
123	return (0);
124}
125
126static int
127bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS)
128{
129	struct bcm_bsc_softc *sc;
130	uint32_t clk, reg;
131	int error;
132
133	sc = (struct bcm_bsc_softc *)arg1;
134
135	BCM_BSC_LOCK(sc);
136	reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
137	BCM_BSC_UNLOCK(sc);
138	reg >>= 16;
139	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
140	if (error != 0 || req->newptr == NULL)
141		return (error);
142
143	BCM_BSC_LOCK(sc);
144	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
145	clk = BCM_BSC_CORE_CLK / clk;
146	if (reg > clk / 2)
147		reg = clk / 2 - 1;
148	bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16);
149	BCM_BSC_UNLOCK(sc);
150
151	return (0);
152}
153
154static int
155bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS)
156{
157	struct bcm_bsc_softc *sc;
158	uint32_t clk, reg;
159	int error;
160
161	sc = (struct bcm_bsc_softc *)arg1;
162
163	BCM_BSC_LOCK(sc);
164	reg = BCM_BSC_READ(sc, BCM_BSC_DELAY);
165	BCM_BSC_UNLOCK(sc);
166	reg &= 0xffff;
167	error = sysctl_handle_int(oidp, &reg, sizeof(reg), req);
168	if (error != 0 || req->newptr == NULL)
169		return (error);
170
171	BCM_BSC_LOCK(sc);
172	clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK);
173	clk = BCM_BSC_CORE_CLK / clk;
174	if (reg > clk / 2)
175		reg = clk / 2 - 1;
176	bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg);
177	BCM_BSC_UNLOCK(sc);
178
179	return (0);
180}
181
182static void
183bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc)
184{
185	struct sysctl_ctx_list *ctx;
186	struct sysctl_oid *tree_node;
187	struct sysctl_oid_list *tree;
188
189	/*
190	 * Add system sysctl tree/handlers.
191	 */
192	ctx = device_get_sysctl_ctx(sc->sc_dev);
193	tree_node = device_get_sysctl_tree(sc->sc_dev);
194	tree = SYSCTL_CHILDREN(tree_node);
195	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
196	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
197	    bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency");
198	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch",
199	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
200	    bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout");
201	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay",
202	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
203	    bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay");
204	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay",
205	    CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
206	    bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay");
207}
208
209static void
210bcm_bsc_reset(struct bcm_bsc_softc *sc)
211{
212
213	/* Clear pending interrupts. */
214	BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT |
215	    BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE);
216	/* Clear the FIFO. */
217	bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0,
218	    BCM_BSC_CTRL_CLEAR0);
219}
220
221static int
222bcm_bsc_probe(device_t dev)
223{
224
225	if (!ofw_bus_status_okay(dev))
226		return (ENXIO);
227
228	if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-bsc"))
229		return (ENXIO);
230
231	device_set_desc(dev, "BCM2708/2835 BSC controller");
232
233	return (BUS_PROBE_DEFAULT);
234}
235
236static int
237bcm_bsc_attach(device_t dev)
238{
239	struct bcm_bsc_softc *sc;
240	unsigned long start;
241	device_t gpio;
242	int i, rid;
243
244	sc = device_get_softc(dev);
245	sc->sc_dev = dev;
246
247	rid = 0;
248	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
249	    RF_ACTIVE);
250	if (!sc->sc_mem_res) {
251		device_printf(dev, "cannot allocate memory window\n");
252		return (ENXIO);
253	}
254
255	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
256	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
257
258	/* Check the unit we are attaching by its base address. */
259	start = rman_get_start(sc->sc_mem_res);
260	for (i = 0; i < nitems(bcm_bsc_pins); i++) {
261		if (bcm_bsc_pins[i].start == start)
262			break;
263	}
264	if (i == nitems(bcm_bsc_pins)) {
265		device_printf(dev, "only bsc0 and bsc1 are supported\n");
266		return (ENXIO);
267	}
268
269	/*
270	 * Configure the GPIO pins to ALT0 function to enable BSC control
271	 * over the pins.
272	 */
273	gpio = devclass_get_device(devclass_find("gpio"), 0);
274	if (!gpio) {
275		device_printf(dev, "cannot find gpio0\n");
276		return (ENXIO);
277	}
278	bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0);
279	bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0);
280
281	rid = 0;
282	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
283	    RF_ACTIVE | RF_SHAREABLE);
284	if (!sc->sc_irq_res) {
285		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
286		device_printf(dev, "cannot allocate interrupt\n");
287		return (ENXIO);
288	}
289
290	/* Hook up our interrupt handler. */
291	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
292	    NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) {
293		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
294		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
295		device_printf(dev, "cannot setup the interrupt handler\n");
296		return (ENXIO);
297	}
298
299	mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF);
300
301	bcm_bsc_sysctl_init(sc);
302
303	/* Enable the BSC controller.  Flush the FIFO. */
304	BCM_BSC_LOCK(sc);
305	BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
306	bcm_bsc_reset(sc);
307	BCM_BSC_UNLOCK(sc);
308
309	device_add_child(dev, "iicbus", -1);
310
311	return (bus_generic_attach(dev));
312}
313
314static int
315bcm_bsc_detach(device_t dev)
316{
317	struct bcm_bsc_softc *sc;
318
319	bus_generic_detach(dev);
320
321	sc = device_get_softc(dev);
322	mtx_destroy(&sc->sc_mtx);
323	if (sc->sc_intrhand)
324		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
325	if (sc->sc_irq_res)
326		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
327	if (sc->sc_mem_res)
328		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
329
330	return (0);
331}
332
333static void
334bcm_bsc_intr(void *arg)
335{
336	struct bcm_bsc_softc *sc;
337	uint32_t status;
338
339	sc = (struct bcm_bsc_softc *)arg;
340
341	BCM_BSC_LOCK(sc);
342
343	/* The I2C interrupt is shared among all the BSC controllers. */
344	if ((sc->sc_flags & BCM_I2C_BUSY) == 0) {
345		BCM_BSC_UNLOCK(sc);
346		return;
347	}
348
349	status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
350
351	/* Check for errors. */
352	if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) {
353		/* Disable interrupts. */
354		BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
355		sc->sc_flags |= BCM_I2C_ERROR;
356		bcm_bsc_reset(sc);
357		wakeup(sc->sc_dev);
358		BCM_BSC_UNLOCK(sc);
359		return;
360	}
361
362	if (sc->sc_flags & BCM_I2C_READ) {
363		while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) {
364			*sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA);
365			sc->sc_resid--;
366			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
367		}
368	} else {
369		while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) {
370			BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++);
371			sc->sc_resid--;
372			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
373		}
374	}
375
376	if (status & BCM_BSC_STATUS_DONE) {
377		/* Disable interrupts. */
378		BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN);
379		bcm_bsc_reset(sc);
380		wakeup(sc->sc_dev);
381	}
382
383	BCM_BSC_UNLOCK(sc);
384}
385
386static int
387bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
388{
389	struct bcm_bsc_softc *sc;
390	uint32_t intr, read, status;
391	int i, err;
392
393	sc = device_get_softc(dev);
394	BCM_BSC_LOCK(sc);
395
396	/* If the controller is busy wait until it is available. */
397	while (sc->sc_flags & BCM_I2C_BUSY)
398		mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_bsc", 0);
399
400	/* Now we have control over the BSC controller. */
401	sc->sc_flags = BCM_I2C_BUSY;
402
403	/* Clear the FIFO and the pending interrupts. */
404	bcm_bsc_reset(sc);
405
406	err = 0;
407	for (i = 0; i < nmsgs; i++) {
408
409		/* Write the slave address. */
410		BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1);
411
412		/* Write the data length. */
413		BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len);
414
415		sc->sc_data = msgs[i].buf;
416		sc->sc_resid = msgs[i].len;
417		if ((msgs[i].flags & IIC_M_RD) == 0) {
418			/* Fill up the TX FIFO. */
419			status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
420			while (sc->sc_resid > 0 &&
421			    (status & BCM_BSC_STATUS_TXD)) {
422				BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data);
423				sc->sc_data++;
424				sc->sc_resid--;
425				status = BCM_BSC_READ(sc, BCM_BSC_STATUS);
426			}
427			read = 0;
428			intr = BCM_BSC_CTRL_INTT;
429			sc->sc_flags &= ~BCM_I2C_READ;
430		} else {
431			sc->sc_flags |= BCM_I2C_READ;
432			read = BCM_BSC_CTRL_READ;
433			intr = BCM_BSC_CTRL_INTR;
434		}
435		intr |= BCM_BSC_CTRL_INTD;
436
437		/* Start the transfer. */
438		BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN |
439		    BCM_BSC_CTRL_ST | read | intr);
440
441		/* Wait for the transaction to complete. */
442		err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_bsc", hz);
443
444		/* Check if we have a timeout or an I2C error. */
445		if ((sc->sc_flags & BCM_I2C_ERROR) || err == EWOULDBLOCK) {
446			device_printf(sc->sc_dev, "I2C error\n");
447			err = EIO;
448			break;
449		}
450	}
451
452	/* Clean the controller flags. */
453	sc->sc_flags = 0;
454
455	BCM_BSC_UNLOCK(sc);
456
457	return (err);
458}
459
460static phandle_t
461bcm_bsc_get_node(device_t bus, device_t dev)
462{
463
464	/* We only have one child, the I2C bus, which needs our own node. */
465	return (ofw_bus_get_node(bus));
466}
467
468static device_method_t bcm_bsc_methods[] = {
469	/* Device interface */
470	DEVMETHOD(device_probe,		bcm_bsc_probe),
471	DEVMETHOD(device_attach,	bcm_bsc_attach),
472	DEVMETHOD(device_detach,	bcm_bsc_detach),
473
474	/* iicbus interface */
475	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
476	DEVMETHOD(iicbus_transfer,	bcm_bsc_transfer),
477
478	/* ofw_bus interface */
479	DEVMETHOD(ofw_bus_get_node,	bcm_bsc_get_node),
480
481	DEVMETHOD_END
482};
483
484static devclass_t bcm_bsc_devclass;
485
486static driver_t bcm_bsc_driver = {
487	"iichb",
488	bcm_bsc_methods,
489	sizeof(struct bcm_bsc_softc),
490};
491
492DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0);
493DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0);
494