at91_smc.h revision 260884
1260884Simp/*- 2260884Simp * Copyright (c) 2014 M. Warner Losh. All rights reserved. 3260884Simp * 4260884Simp * Redistribution and use in source and binary forms, with or without 5260884Simp * modification, are permitted provided that the following conditions 6260884Simp * are met: 7260884Simp * 1. Redistributions of source code must retain the above copyright 8260884Simp * notice, this list of conditions and the following disclaimer. 9260884Simp * 2. Redistributions in binary form must reproduce the above copyright 10260884Simp * notice, this list of conditions and the following disclaimer in the 11260884Simp * documentation and/or other materials provided with the distribution. 12260884Simp * 13260884Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14260884Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15260884Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16260884Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17260884Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18260884Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19260884Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20260884Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21260884Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22260884Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23260884Simp * SUCH DAMAGE. 24260884Simp */ 25260884Simp 26260884Simp/* $FreeBSD: head/sys/arm/at91/at91_smc.h 260884 2014-01-19 17:45:13Z imp $ */ 27260884Simp 28260884Simp#ifndef ARM_AT91_AT91_SMC_H 29260884Simp#define ARM_AT91_AT91_SMC_H 30260884Simp 31260884Simp/* Registers */ 32260884Simp#define SMC_SETUP 0x00 33260884Simp#define SMC_PULSE 0x04 34260884Simp#define SMC_CYCLE 0x08 35260884Simp#define SMC_MODE 0x0C 36260884Simp 37260884Simp#define SMC_CS_OFF(cs) (0x10 * (cs)) 38260884Simp 39260884Simp/* Setup */ 40260884Simp#define SMC_SETUP_NCS_RD_SETUP(x) ((x) << 24) 41260884Simp#define SMC_SETUP_NRD_SETUP(x) ((x) << 16) 42260884Simp#define SMC_SETUP_NCS_WR_SETUP(x) ((x) << 8) 43260884Simp#define SMC_SETUP_NWE_SETUP(x) (x) 44260884Simp 45260884Simp/* Pulse */ 46260884Simp#define SMC_PULSE_NCS_RD_PULSE(x) ((x) << 24) 47260884Simp#define SMC_PULSE_NRD_PULSE(x) ((x) << 16) 48260884Simp#define SMC_PULSE_NCS_WR_PULSE(x) ((x) << 8) 49260884Simp#define SMC_PULSE_NWE_PULSE(x) (x) 50260884Simp 51260884Simp/* Cycle */ 52260884Simp#define SMC_CYCLE_NRD_CYCLE(x) ((x) << 16) 53260884Simp#define SMC_CYCLE_NWE_CYCLE(x) (x) 54260884Simp 55260884Simp/* Mode */ 56260884Simp#define SMC_MODE_READ (1 << 0) 57260884Simp#define SMC_MODE_WRITE (1 << 1) 58260884Simp#define SMC_MODE_EXNW_DISABLED (0 << 4) 59260884Simp#define SMC_MODE_EXNW_FROZEN_MODE (2 << 4) 60260884Simp#define SMC_MODE_EXNW_READY_MODE (3 << 4) 61260884Simp#define SMC_MODE_BAT (1 << 8) 62260884Simp#define SMC_MODE_DBW_8BIT (0 << 12) 63260884Simp#define SMC_MODE_DBW_16BIT (1 << 12) 64260884Simp#define SMC_MODE_DBW_32_BIT (2 << 12) 65260884Simp#define SMC_MODE_TDF_CYCLES(x) ((x) << 16) 66260884Simp#define SMC_MODE_TDF_MODE (1 << 20) 67260884Simp#define SMC_MODE_PMEN (1 << 24) 68260884Simp#define SMC_PS_4BYTE (0 << 28) 69260884Simp#define SMC_PS_8BYTE (1 << 28) 70260884Simp#define SMC_PS_16BYTE (2 << 28) 71260884Simp#define SMC_PS_32BYTE (3 << 28) 72260884Simp 73260884Simp/* 74260884Simp * structure to ease init. See the SMC chapter in the datasheet for 75260884Simp * the appropriate SoC you are using for details. 76260884Simp */ 77260884Simpstruct at91_smc_init 78260884Simp{ 79260884Simp /* Setup register */ 80260884Simp uint8_t ncs_rd_setup; 81260884Simp uint8_t nrd_setup; 82260884Simp uint8_t ncs_wr_setup; 83260884Simp uint8_t nwe_setup; 84260884Simp 85260884Simp /* Pulse register */ 86260884Simp uint8_t ncs_rd_pulse; 87260884Simp uint8_t nrd_pulse; 88260884Simp uint8_t ncs_wr_pulse; 89260884Simp uint8_t nwe_pulse; 90260884Simp 91260884Simp /* Cycle register */ 92260884Simp uint16_t nrd_cycle; 93260884Simp uint16_t nwe_cycle; 94260884Simp 95260884Simp /* Mode register */ 96260884Simp uint8_t mode; /* Combo of READ/WRITE/EXNW fields */ 97260884Simp uint8_t bat; 98260884Simp uint8_t dwb; 99260884Simp uint8_t tdf_cycles; 100260884Simp uint8_t tdf_mode; 101260884Simp uint8_t pmen; 102260884Simp uint8_t ps; 103260884Simp}; 104260884Simp 105260884Simp/* 106260884Simp * Convenience routine to fill in SMC registers for a given chip select. 107260884Simp */ 108260884Simpvoid at91_smc_setup(int id, int cs, const struct at91_smc_init *smc); 109260884Simp 110260884Simp/* 111260884Simp * Disable/Enable different External Bus Interfaces (EBI) 112260884Simp */ 113260884Simpvoid at91_ebi_enable(int cs); 114260884Simpvoid at91_ebi_disable(int cs); 115260884Simp 116260884Simp#endif /* ARM_AT91_AT91_SMC_H */ 117