PPCRegisterInfo.td revision 249423
1234353Sdim//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// 2234353Sdim// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7234353Sdim// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// 11193323Sed//===----------------------------------------------------------------------===// 12193323Sed 13208599Srdivackylet Namespace = "PPC" in { 14208599Srdivackydef sub_lt : SubRegIndex; 15208599Srdivackydef sub_gt : SubRegIndex; 16208599Srdivackydef sub_eq : SubRegIndex; 17208599Srdivackydef sub_un : SubRegIndex; 18208599Srdivackydef sub_32 : SubRegIndex; 19208599Srdivacky} 20208599Srdivacky 21208599Srdivacky 22193323Sedclass PPCReg<string n> : Register<n> { 23193323Sed let Namespace = "PPC"; 24193323Sed} 25193323Sed 26193323Sed// We identify all our registers with a 5-bit ID, for consistency's sake. 27193323Sed 28193323Sed// GPR - One of the 32 32-bit general-purpose registers 29193323Sedclass GPR<bits<5> num, string n> : PPCReg<n> { 30249423Sdim let HWEncoding{4-0} = num; 31193323Sed} 32193323Sed 33193323Sed// GP8 - One of the 32 64-bit general-purpose registers 34193323Sedclass GP8<GPR SubReg, string n> : PPCReg<n> { 35249423Sdim let HWEncoding = SubReg.HWEncoding; 36193323Sed let SubRegs = [SubReg]; 37208599Srdivacky let SubRegIndices = [sub_32]; 38193323Sed} 39193323Sed 40193323Sed// SPR - One of the 32-bit special-purpose registers 41193323Sedclass SPR<bits<10> num, string n> : PPCReg<n> { 42249423Sdim let HWEncoding{9-0} = num; 43193323Sed} 44193323Sed 45193323Sed// FPR - One of the 32 64-bit floating-point registers 46193323Sedclass FPR<bits<5> num, string n> : PPCReg<n> { 47249423Sdim let HWEncoding{4-0} = num; 48193323Sed} 49193323Sed 50193323Sed// VR - One of the 32 128-bit vector registers 51193323Sedclass VR<bits<5> num, string n> : PPCReg<n> { 52249423Sdim let HWEncoding{4-0} = num; 53193323Sed} 54193323Sed 55193323Sed// CR - One of the 8 4-bit condition registers 56195340Sedclass CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> { 57249423Sdim let HWEncoding{2-0} = num; 58195340Sed let SubRegs = subregs; 59193323Sed} 60193323Sed 61193323Sed// CRBIT - One of the 32 1-bit condition register fields 62193323Sedclass CRBIT<bits<5> num, string n> : PPCReg<n> { 63249423Sdim let HWEncoding{4-0} = num; 64193323Sed} 65193323Sed 66193323Sed// General-purpose registers 67249423Sdimforeach Index = 0-31 in { 68249423Sdim def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>; 69249423Sdim} 70193323Sed 71193323Sed// 64-bit General-purpose registers 72249423Sdimforeach Index = 0-31 in { 73249423Sdim def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>, 74249423Sdim DwarfRegNum<[Index, -2]>; 75249423Sdim} 76193323Sed 77193323Sed// Floating-point registers 78249423Sdimforeach Index = 0-31 in { 79249423Sdim def F#Index : FPR<Index, "f"#Index>, 80249423Sdim DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>; 81249423Sdim} 82193323Sed 83193323Sed// Vector registers 84249423Sdimforeach Index = 0-31 in { 85249423Sdim def V#Index : VR<Index, "v"#Index>, 86249423Sdim DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>; 87249423Sdim} 88193323Sed 89249423Sdim// The reprsentation of r0 when treated as the constant 0. 90249423Sdimdef ZERO : GPR<0, "0">; 91249423Sdimdef ZERO8 : GP8<ZERO, "0">; 92249423Sdim 93249423Sdim// Representations of the frame pointer used by ISD::FRAMEADDR. 94249423Sdimdef FP : GPR<0 /* arbitrary */, "**FRAME POINTER**">; 95249423Sdimdef FP8 : GP8<FP, "**FRAME POINTER**">; 96249423Sdim 97193323Sed// Condition register bits 98223017Sdimdef CR0LT : CRBIT< 0, "0">; 99223017Sdimdef CR0GT : CRBIT< 1, "1">; 100223017Sdimdef CR0EQ : CRBIT< 2, "2">; 101223017Sdimdef CR0UN : CRBIT< 3, "3">; 102223017Sdimdef CR1LT : CRBIT< 4, "4">; 103223017Sdimdef CR1GT : CRBIT< 5, "5">; 104223017Sdimdef CR1EQ : CRBIT< 6, "6">; 105223017Sdimdef CR1UN : CRBIT< 7, "7">; 106223017Sdimdef CR2LT : CRBIT< 8, "8">; 107223017Sdimdef CR2GT : CRBIT< 9, "9">; 108223017Sdimdef CR2EQ : CRBIT<10, "10">; 109223017Sdimdef CR2UN : CRBIT<11, "11">; 110223017Sdimdef CR3LT : CRBIT<12, "12">; 111223017Sdimdef CR3GT : CRBIT<13, "13">; 112223017Sdimdef CR3EQ : CRBIT<14, "14">; 113223017Sdimdef CR3UN : CRBIT<15, "15">; 114223017Sdimdef CR4LT : CRBIT<16, "16">; 115223017Sdimdef CR4GT : CRBIT<17, "17">; 116223017Sdimdef CR4EQ : CRBIT<18, "18">; 117223017Sdimdef CR4UN : CRBIT<19, "19">; 118223017Sdimdef CR5LT : CRBIT<20, "20">; 119223017Sdimdef CR5GT : CRBIT<21, "21">; 120223017Sdimdef CR5EQ : CRBIT<22, "22">; 121223017Sdimdef CR5UN : CRBIT<23, "23">; 122223017Sdimdef CR6LT : CRBIT<24, "24">; 123223017Sdimdef CR6GT : CRBIT<25, "25">; 124223017Sdimdef CR6EQ : CRBIT<26, "26">; 125223017Sdimdef CR6UN : CRBIT<27, "27">; 126223017Sdimdef CR7LT : CRBIT<28, "28">; 127223017Sdimdef CR7GT : CRBIT<29, "29">; 128223017Sdimdef CR7EQ : CRBIT<30, "30">; 129223017Sdimdef CR7UN : CRBIT<31, "31">; 130193323Sed 131195340Sed// Condition registers 132208599Srdivackylet SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { 133223017Sdimdef CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; 134223017Sdimdef CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; 135223017Sdimdef CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; 136223017Sdimdef CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; 137223017Sdimdef CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; 138223017Sdimdef CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; 139223017Sdimdef CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; 140223017Sdimdef CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; 141208599Srdivacky} 142195340Sed 143193323Sed// Link register 144223017Sdimdef LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; 145193323Sed//let Aliases = [LR] in 146223017Sdimdef LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; 147193323Sed 148193323Sed// Count register 149223017Sdimdef CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; 150223017Sdimdef CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; 151193323Sed 152193323Sed// VRsave register 153223017Sdimdef VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>; 154193323Sed 155198090Srdivacky// Carry bit. In the architecture this is really bit 0 of the XER register 156198090Srdivacky// (which really is SPR register 1); this is the only bit interesting to a 157198090Srdivacky// compiler. 158223017Sdimdef CARRY: SPR<1, "ca">; 159198090Srdivacky 160193323Sed// FP rounding mode: bits 30 and 31 of the FP status and control register 161193323Sed// This is not allocated as a normal register; it appears only in 162193323Sed// Uses and Defs. The ABI says it needs to be preserved by a function, 163193323Sed// but this is not achieved by saving and restoring it as with 164193323Sed// most registers, it has to be done in code; to make this work all the 165193323Sed// return and call instructions are described as Uses of RM, so instructions 166193323Sed// that do nothing but change RM will not get deleted. 167193323Sed// Also, in the architecture it is not really a SPR; 512 is arbitrary. 168223017Sdimdef RM: SPR<512, "**ROUNDING MODE**">; 169193323Sed 170193323Sed/// Register classes 171193323Sed// Allocate volatiles first 172193323Sed// then nonvolatiles in reverse order since stmw/lmw save from rN to r31 173224145Sdimdef GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), 174224145Sdim (sequence "R%u", 30, 13), 175249423Sdim R31, R0, R1, FP)>; 176223017Sdim 177224145Sdimdef G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), 178224145Sdim (sequence "X%u", 30, 14), 179249423Sdim X31, X13, X0, X1, FP8)>; 180193323Sed 181249423Sdim// For some instructions r0 is special (representing the value 0 instead of 182249423Sdim// the value in the r0 register), and we use these register subclasses to 183249423Sdim// prevent r0 from being allocated for use by those instructions. 184249423Sdimdef GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)>; 185249423Sdimdef G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)>; 186249423Sdim 187195340Sed// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4 188195340Sed// ABI the size of the Floating-point register save area is determined by the 189195340Sed// allocated non-volatile register with the lowest register number, as FP 190195340Sed// register N is spilled to offset 8 * (32 - N) below the back chain word of the 191195340Sed// previous stack frame. By allocating non-volatiles in reverse order we make 192195340Sed// sure that the Floating-point register save area is always as small as 193195340Sed// possible because there aren't any unused spill slots. 194224145Sdimdef F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13), 195224145Sdim (sequence "F%u", 31, 14))>; 196224145Sdimdef F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>; 197193323Sed 198193323Seddef VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128, 199224145Sdim (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11, 200224145Sdim V12, V13, V14, V15, V16, V17, V18, V19, V31, V30, 201224145Sdim V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>; 202193323Sed 203193323Seddef CRBITRC : RegisterClass<"PPC", [i32], 32, 204224145Sdim (add CR0LT, CR0GT, CR0EQ, CR0UN, 205224145Sdim CR1LT, CR1GT, CR1EQ, CR1UN, 206224145Sdim CR2LT, CR2GT, CR2EQ, CR2UN, 207224145Sdim CR3LT, CR3GT, CR3EQ, CR3UN, 208224145Sdim CR4LT, CR4GT, CR4EQ, CR4UN, 209224145Sdim CR5LT, CR5GT, CR5EQ, CR5UN, 210224145Sdim CR6LT, CR6GT, CR6EQ, CR6UN, 211224145Sdim CR7LT, CR7GT, CR7EQ, CR7UN)> 212193323Sed{ 213193323Sed let CopyCost = -1; 214193323Sed} 215193323Sed 216224145Sdimdef CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6, 217239462Sdim CR7, CR2, CR3, CR4)>; 218239462Sdim 219239462Sdim// The CTR registers are not allocatable because they're used by the 220239462Sdim// decrement-and-branch instructions, and thus need to stay live across 221239462Sdim// multiple basic blocks. 222239462Sdimdef CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> { 223239462Sdim let isAllocatable = 0; 224195340Sed} 225239462Sdimdef CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> { 226239462Sdim let isAllocatable = 0; 227239462Sdim} 228193323Sed 229224145Sdimdef VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; 230224145Sdimdef CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { 231198090Srdivacky let CopyCost = -1; 232198090Srdivacky} 233