1//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMBASEREGISTERINFO_H 15#define ARMBASEREGISTERINFO_H 16 17#include "ARM.h" 18#include "llvm/Target/TargetRegisterInfo.h" 19 20#define GET_REGINFO_HEADER 21#include "ARMGenRegisterInfo.inc" 22 23namespace llvm { 24 class ARMSubtarget; 25 class ARMBaseInstrInfo; 26 class Type; 27 28/// Register allocation hints. 29namespace ARMRI { 30 enum { 31 RegPairOdd = 1, 32 RegPairEven = 2 33 }; 34} 35 36/// isARMArea1Register - Returns true if the register is a low register (r0-r7) 37/// or a stack/pc register that we should push/pop. 38static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { 39 using namespace ARM; 40 switch (Reg) { 41 case R0: case R1: case R2: case R3: 42 case R4: case R5: case R6: case R7: 43 case LR: case SP: case PC: 44 return true; 45 case R8: case R9: case R10: case R11: 46 // For iOS we want r7 and lr to be next to each other. 47 return !isIOS; 48 default: 49 return false; 50 } 51} 52 53static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { 54 using namespace ARM; 55 switch (Reg) { 56 case R8: case R9: case R10: case R11: 57 // iOS has this second area. 58 return isIOS; 59 default: 60 return false; 61 } 62} 63 64static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { 65 using namespace ARM; 66 switch (Reg) { 67 case D15: case D14: case D13: case D12: 68 case D11: case D10: case D9: case D8: 69 return true; 70 default: 71 return false; 72 } 73} 74 75static inline bool isCalleeSavedRegister(unsigned Reg, 76 const MCPhysReg *CSRegs) { 77 for (unsigned i = 0; CSRegs[i]; ++i) 78 if (Reg == CSRegs[i]) 79 return true; 80 return false; 81} 82 83class ARMBaseRegisterInfo : public ARMGenRegisterInfo { 84protected: 85 const ARMSubtarget &STI; 86 87 /// FramePtr - ARM physical register used as frame ptr. 88 unsigned FramePtr; 89 90 /// BasePtr - ARM physical register used as a base ptr in complex stack 91 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 92 /// variable size stack objects. 93 unsigned BasePtr; 94 95 // Can be only subclassed. 96 explicit ARMBaseRegisterInfo(const ARMSubtarget &STI); 97 98 // Return the opcode that implements 'Op', or 0 if no opcode 99 unsigned getOpcode(int Op) const; 100 101public: 102 /// Code Generation virtual methods... 103 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; 104 const uint32_t *getCallPreservedMask(CallingConv::ID) const; 105 const uint32_t *getNoPreservedMask() const; 106 107 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the 108 /// case that 'returned' is on an i32 first argument if the calling convention 109 /// is one that can (partially) model this attribute with a preserved mask 110 /// (i.e. it is a calling convention that uses the same register for the first 111 /// i32 argument and an i32 return value) 112 /// 113 /// Should return NULL in the case that the calling convention does not have 114 /// this property 115 const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const; 116 117 BitVector getReservedRegs(const MachineFunction &MF) const; 118 119 const TargetRegisterClass* 120 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const; 121 const TargetRegisterClass* 122 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 123 124 const TargetRegisterClass* 125 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 126 127 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 128 MachineFunction &MF) const; 129 130 void getRegAllocationHints(unsigned VirtReg, 131 ArrayRef<MCPhysReg> Order, 132 SmallVectorImpl<MCPhysReg> &Hints, 133 const MachineFunction &MF, 134 const VirtRegMap *VRM) const; 135 136 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 137 MachineFunction &MF) const; 138 139 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const; 140 141 bool hasBasePointer(const MachineFunction &MF) const; 142 143 bool canRealignStack(const MachineFunction &MF) const; 144 bool needsStackRealignment(const MachineFunction &MF) const; 145 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const; 146 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const; 147 void materializeFrameBaseRegister(MachineBasicBlock *MBB, 148 unsigned BaseReg, int FrameIdx, 149 int64_t Offset) const; 150 void resolveFrameIndex(MachineBasicBlock::iterator I, 151 unsigned BaseReg, int64_t Offset) const; 152 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const; 153 154 bool cannotEliminateFrame(const MachineFunction &MF) const; 155 156 // Debug information queries. 157 unsigned getFrameRegister(const MachineFunction &MF) const; 158 unsigned getBaseRegister() const { return BasePtr; } 159 160 bool isLowRegister(unsigned Reg) const; 161 162 163 /// emitLoadConstPool - Emits a load from constpool to materialize the 164 /// specified immediate. 165 virtual void emitLoadConstPool(MachineBasicBlock &MBB, 166 MachineBasicBlock::iterator &MBBI, 167 DebugLoc dl, 168 unsigned DestReg, unsigned SubIdx, 169 int Val, 170 ARMCC::CondCodes Pred = ARMCC::AL, 171 unsigned PredReg = 0, 172 unsigned MIFlags = MachineInstr::NoFlags)const; 173 174 /// Code Generation virtual methods... 175 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const; 176 177 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; 178 179 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const; 180 181 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const; 182 183 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II, 184 int SPAdj, unsigned FIOperandNum, 185 RegScavenger *RS = NULL) const; 186}; 187 188} // end namespace llvm 189 190#endif 191