1/* Target-dependent code for the IA-64 for GDB, the GNU debugger. 2 3 Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software 4 Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23#include "defs.h" 24#include "inferior.h" 25#include "gdbcore.h" 26#include "arch-utils.h" 27#include "floatformat.h" 28#include "regcache.h" 29#include "reggroups.h" 30#include "frame.h" 31#include "frame-base.h" 32#include "frame-unwind.h" 33#include "doublest.h" 34#include "value.h" 35#include "gdb_assert.h" 36#include "objfiles.h" 37#include "elf/common.h" /* for DT_PLTGOT value */ 38#include "elf-bfd.h" 39#include "elf.h" /* for PT_IA64_UNWIND value */ 40#include "dis-asm.h" 41#include "ia64-tdep.h" 42 43#ifdef HAVE_LIBUNWIND_IA64_H 44#include "libunwind-frame.h" 45#include "libunwind-ia64.h" 46#endif 47 48/* An enumeration of the different IA-64 instruction types. */ 49 50typedef enum instruction_type 51{ 52 A, /* Integer ALU ; I-unit or M-unit */ 53 I, /* Non-ALU integer; I-unit */ 54 M, /* Memory ; M-unit */ 55 F, /* Floating-point ; F-unit */ 56 B, /* Branch ; B-unit */ 57 L, /* Extended (L+X) ; I-unit */ 58 X, /* Extended (L+X) ; I-unit */ 59 undefined /* undefined or reserved */ 60} instruction_type; 61 62/* We represent IA-64 PC addresses as the value of the instruction 63 pointer or'd with some bit combination in the low nibble which 64 represents the slot number in the bundle addressed by the 65 instruction pointer. The problem is that the Linux kernel 66 multiplies its slot numbers (for exceptions) by one while the 67 disassembler multiplies its slot numbers by 6. In addition, I've 68 heard it said that the simulator uses 1 as the multiplier. 69 70 I've fixed the disassembler so that the bytes_per_line field will 71 be the slot multiplier. If bytes_per_line comes in as zero, it 72 is set to six (which is how it was set up initially). -- objdump 73 displays pretty disassembly dumps with this value. For our purposes, 74 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we 75 never want to also display the raw bytes the way objdump does. */ 76 77#define SLOT_MULTIPLIER 1 78 79/* Length in bytes of an instruction bundle */ 80 81#define BUNDLE_LEN 16 82 83static gdbarch_init_ftype ia64_gdbarch_init; 84 85static gdbarch_register_name_ftype ia64_register_name; 86static gdbarch_register_type_ftype ia64_register_type; 87static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc; 88static gdbarch_skip_prologue_ftype ia64_skip_prologue; 89static gdbarch_extract_return_value_ftype ia64_extract_return_value; 90static gdbarch_use_struct_convention_ftype ia64_use_struct_convention; 91static struct type *is_float_or_hfa_type (struct type *t); 92 93static struct type *builtin_type_ia64_ext; 94 95#define NUM_IA64_RAW_REGS 462 96 97static int sp_regnum = IA64_GR12_REGNUM; 98static int fp_regnum = IA64_VFP_REGNUM; 99static int lr_regnum = IA64_VRAP_REGNUM; 100 101/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because 102 they may not be accessible via the ptrace register get/set interfaces. */ 103enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM, 104 V127_REGNUM = V32_REGNUM + 95, 105 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM }; 106 107/* Array of register names; There should be ia64_num_regs strings in 108 the initializer. */ 109 110static char *ia64_register_names[] = 111{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 112 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 113 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 114 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 115 "", "", "", "", "", "", "", "", 116 "", "", "", "", "", "", "", "", 117 "", "", "", "", "", "", "", "", 118 "", "", "", "", "", "", "", "", 119 "", "", "", "", "", "", "", "", 120 "", "", "", "", "", "", "", "", 121 "", "", "", "", "", "", "", "", 122 "", "", "", "", "", "", "", "", 123 "", "", "", "", "", "", "", "", 124 "", "", "", "", "", "", "", "", 125 "", "", "", "", "", "", "", "", 126 "", "", "", "", "", "", "", "", 127 128 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 129 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 130 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 131 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 132 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", 133 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", 134 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", 135 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", 136 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71", 137 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", 138 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", 139 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95", 140 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103", 141 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111", 142 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119", 143 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127", 144 145 "", "", "", "", "", "", "", "", 146 "", "", "", "", "", "", "", "", 147 "", "", "", "", "", "", "", "", 148 "", "", "", "", "", "", "", "", 149 "", "", "", "", "", "", "", "", 150 "", "", "", "", "", "", "", "", 151 "", "", "", "", "", "", "", "", 152 "", "", "", "", "", "", "", "", 153 154 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 155 156 "vfp", "vrap", 157 158 "pr", "ip", "psr", "cfm", 159 160 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7", 161 "", "", "", "", "", "", "", "", 162 "rsc", "bsp", "bspstore", "rnat", 163 "", "fcr", "", "", 164 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "", 165 "ccv", "", "", "", "unat", "", "", "", 166 "fpsr", "", "", "", "itc", 167 "", "", "", "", "", "", "", "", "", "", 168 "", "", "", "", "", "", "", "", "", 169 "pfs", "lc", "ec", 170 "", "", "", "", "", "", "", "", "", "", 171 "", "", "", "", "", "", "", "", "", "", 172 "", "", "", "", "", "", "", "", "", "", 173 "", "", "", "", "", "", "", "", "", "", 174 "", "", "", "", "", "", "", "", "", "", 175 "", "", "", "", "", "", "", "", "", "", 176 "", 177 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7", 178 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15", 179 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23", 180 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31", 181 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39", 182 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47", 183 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55", 184 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63", 185 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71", 186 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79", 187 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87", 188 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95", 189 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103", 190 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111", 191 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119", 192 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127", 193 194 "bof", 195 196 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", 197 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", 198 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", 199 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", 200 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71", 201 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79", 202 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87", 203 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95", 204 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103", 205 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111", 206 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119", 207 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127", 208 209 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", 210 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15", 211 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23", 212 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31", 213 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", 214 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", 215 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55", 216 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63", 217}; 218 219struct ia64_frame_cache 220{ 221 CORE_ADDR base; /* frame pointer base for frame */ 222 CORE_ADDR pc; /* function start pc for frame */ 223 CORE_ADDR saved_sp; /* stack pointer for frame */ 224 CORE_ADDR bsp; /* points at r32 for the current frame */ 225 CORE_ADDR cfm; /* cfm value for current frame */ 226 CORE_ADDR prev_cfm; /* cfm value for previous frame */ 227 int frameless; 228 int sof; /* Size of frame (decoded from cfm value) */ 229 int sol; /* Size of locals (decoded from cfm value) */ 230 int sor; /* Number of rotating registers. (decoded from cfm value) */ 231 CORE_ADDR after_prologue; 232 /* Address of first instruction after the last 233 prologue instruction; Note that there may 234 be instructions from the function's body 235 intermingled with the prologue. */ 236 int mem_stack_frame_size; 237 /* Size of the memory stack frame (may be zero), 238 or -1 if it has not been determined yet. */ 239 int fp_reg; /* Register number (if any) used a frame pointer 240 for this frame. 0 if no register is being used 241 as the frame pointer. */ 242 243 /* Saved registers. */ 244 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS]; 245 246}; 247 248int 249ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 250 struct reggroup *group) 251{ 252 int vector_p; 253 int float_p; 254 int raw_p; 255 if (group == all_reggroup) 256 return 1; 257 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); 258 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; 259 raw_p = regnum < NUM_IA64_RAW_REGS; 260 if (group == float_reggroup) 261 return float_p; 262 if (group == vector_reggroup) 263 return vector_p; 264 if (group == general_reggroup) 265 return (!vector_p && !float_p); 266 if (group == save_reggroup || group == restore_reggroup) 267 return raw_p; 268 return 0; 269} 270 271static const char * 272ia64_register_name (int reg) 273{ 274 return ia64_register_names[reg]; 275} 276 277struct type * 278ia64_register_type (struct gdbarch *arch, int reg) 279{ 280 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM) 281 return builtin_type_ia64_ext; 282 else 283 return builtin_type_long; 284} 285 286static int 287ia64_dwarf_reg_to_regnum (int reg) 288{ 289 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM) 290 return V32_REGNUM + (reg - IA64_GR32_REGNUM); 291 return reg; 292} 293 294static int 295floatformat_valid (const struct floatformat *fmt, const char *from) 296{ 297 return 1; 298} 299 300const struct floatformat floatformat_ia64_ext = 301{ 302 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64, 303 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid 304}; 305 306 307/* Extract ``len'' bits from an instruction bundle starting at 308 bit ``from''. */ 309 310static long long 311extract_bit_field (char *bundle, int from, int len) 312{ 313 long long result = 0LL; 314 int to = from + len; 315 int from_byte = from / 8; 316 int to_byte = to / 8; 317 unsigned char *b = (unsigned char *) bundle; 318 unsigned char c; 319 int lshift; 320 int i; 321 322 c = b[from_byte]; 323 if (from_byte == to_byte) 324 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8); 325 result = c >> (from % 8); 326 lshift = 8 - (from % 8); 327 328 for (i = from_byte+1; i < to_byte; i++) 329 { 330 result |= ((long long) b[i]) << lshift; 331 lshift += 8; 332 } 333 334 if (from_byte < to_byte && (to % 8 != 0)) 335 { 336 c = b[to_byte]; 337 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8); 338 result |= ((long long) c) << lshift; 339 } 340 341 return result; 342} 343 344/* Replace the specified bits in an instruction bundle */ 345 346static void 347replace_bit_field (char *bundle, long long val, int from, int len) 348{ 349 int to = from + len; 350 int from_byte = from / 8; 351 int to_byte = to / 8; 352 unsigned char *b = (unsigned char *) bundle; 353 unsigned char c; 354 355 if (from_byte == to_byte) 356 { 357 unsigned char left, right; 358 c = b[from_byte]; 359 left = (c >> (to % 8)) << (to % 8); 360 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8); 361 c = (unsigned char) (val & 0xff); 362 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8); 363 c |= right | left; 364 b[from_byte] = c; 365 } 366 else 367 { 368 int i; 369 c = b[from_byte]; 370 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8); 371 c = c | (val << (from % 8)); 372 b[from_byte] = c; 373 val >>= 8 - from % 8; 374 375 for (i = from_byte+1; i < to_byte; i++) 376 { 377 c = val & 0xff; 378 val >>= 8; 379 b[i] = c; 380 } 381 382 if (to % 8 != 0) 383 { 384 unsigned char cv = (unsigned char) val; 385 c = b[to_byte]; 386 c = c >> (to % 8) << (to % 8); 387 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8); 388 b[to_byte] = c; 389 } 390 } 391} 392 393/* Return the contents of slot N (for N = 0, 1, or 2) in 394 and instruction bundle */ 395 396static long long 397slotN_contents (char *bundle, int slotnum) 398{ 399 return extract_bit_field (bundle, 5+41*slotnum, 41); 400} 401 402/* Store an instruction in an instruction bundle */ 403 404static void 405replace_slotN_contents (char *bundle, long long instr, int slotnum) 406{ 407 replace_bit_field (bundle, instr, 5+41*slotnum, 41); 408} 409 410static enum instruction_type template_encoding_table[32][3] = 411{ 412 { M, I, I }, /* 00 */ 413 { M, I, I }, /* 01 */ 414 { M, I, I }, /* 02 */ 415 { M, I, I }, /* 03 */ 416 { M, L, X }, /* 04 */ 417 { M, L, X }, /* 05 */ 418 { undefined, undefined, undefined }, /* 06 */ 419 { undefined, undefined, undefined }, /* 07 */ 420 { M, M, I }, /* 08 */ 421 { M, M, I }, /* 09 */ 422 { M, M, I }, /* 0A */ 423 { M, M, I }, /* 0B */ 424 { M, F, I }, /* 0C */ 425 { M, F, I }, /* 0D */ 426 { M, M, F }, /* 0E */ 427 { M, M, F }, /* 0F */ 428 { M, I, B }, /* 10 */ 429 { M, I, B }, /* 11 */ 430 { M, B, B }, /* 12 */ 431 { M, B, B }, /* 13 */ 432 { undefined, undefined, undefined }, /* 14 */ 433 { undefined, undefined, undefined }, /* 15 */ 434 { B, B, B }, /* 16 */ 435 { B, B, B }, /* 17 */ 436 { M, M, B }, /* 18 */ 437 { M, M, B }, /* 19 */ 438 { undefined, undefined, undefined }, /* 1A */ 439 { undefined, undefined, undefined }, /* 1B */ 440 { M, F, B }, /* 1C */ 441 { M, F, B }, /* 1D */ 442 { undefined, undefined, undefined }, /* 1E */ 443 { undefined, undefined, undefined }, /* 1F */ 444}; 445 446/* Fetch and (partially) decode an instruction at ADDR and return the 447 address of the next instruction to fetch. */ 448 449static CORE_ADDR 450fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr) 451{ 452 char bundle[BUNDLE_LEN]; 453 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER; 454 long long template; 455 int val; 456 457 /* Warn about slot numbers greater than 2. We used to generate 458 an error here on the assumption that the user entered an invalid 459 address. But, sometimes GDB itself requests an invalid address. 460 This can (easily) happen when execution stops in a function for 461 which there are no symbols. The prologue scanner will attempt to 462 find the beginning of the function - if the nearest symbol 463 happens to not be aligned on a bundle boundary (16 bytes), the 464 resulting starting address will cause GDB to think that the slot 465 number is too large. 466 467 So we warn about it and set the slot number to zero. It is 468 not necessarily a fatal condition, particularly if debugging 469 at the assembly language level. */ 470 if (slotnum > 2) 471 { 472 warning ("Can't fetch instructions for slot numbers greater than 2.\n" 473 "Using slot 0 instead"); 474 slotnum = 0; 475 } 476 477 addr &= ~0x0f; 478 479 val = target_read_memory (addr, bundle, BUNDLE_LEN); 480 481 if (val != 0) 482 return 0; 483 484 *instr = slotN_contents (bundle, slotnum); 485 template = extract_bit_field (bundle, 0, 5); 486 *it = template_encoding_table[(int)template][slotnum]; 487 488 if (slotnum == 2 || (slotnum == 1 && *it == L)) 489 addr += 16; 490 else 491 addr += (slotnum + 1) * SLOT_MULTIPLIER; 492 493 return addr; 494} 495 496/* There are 5 different break instructions (break.i, break.b, 497 break.m, break.f, and break.x), but they all have the same 498 encoding. (The five bit template in the low five bits of the 499 instruction bundle distinguishes one from another.) 500 501 The runtime architecture manual specifies that break instructions 502 used for debugging purposes must have the upper two bits of the 21 503 bit immediate set to a 0 and a 1 respectively. A breakpoint 504 instruction encodes the most significant bit of its 21 bit 505 immediate at bit 36 of the 41 bit instruction. The penultimate msb 506 is at bit 25 which leads to the pattern below. 507 508 Originally, I had this set up to do, e.g, a "break.i 0x80000" But 509 it turns out that 0x80000 was used as the syscall break in the early 510 simulators. So I changed the pattern slightly to do "break.i 0x080001" 511 instead. But that didn't work either (I later found out that this 512 pattern was used by the simulator that I was using.) So I ended up 513 using the pattern seen below. */ 514 515#if 0 516#define IA64_BREAKPOINT 0x00002000040LL 517#endif 518#define IA64_BREAKPOINT 0x00003333300LL 519 520static int 521ia64_memory_insert_breakpoint (CORE_ADDR addr, char *contents_cache) 522{ 523 char bundle[BUNDLE_LEN]; 524 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER; 525 long long instr; 526 int val; 527 int template; 528 529 if (slotnum > 2) 530 error("Can't insert breakpoint for slot numbers greater than 2."); 531 532 addr &= ~0x0f; 533 534 val = target_read_memory (addr, bundle, BUNDLE_LEN); 535 536 /* Check for L type instruction in 2nd slot, if present then 537 bump up the slot number to the 3rd slot */ 538 template = extract_bit_field (bundle, 0, 5); 539 if (slotnum == 1 && template_encoding_table[template][1] == L) 540 { 541 slotnum = 2; 542 } 543 544 instr = slotN_contents (bundle, slotnum); 545 memcpy(contents_cache, &instr, sizeof(instr)); 546 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum); 547 if (val == 0) 548 target_write_memory (addr, bundle, BUNDLE_LEN); 549 550 return val; 551} 552 553static int 554ia64_memory_remove_breakpoint (CORE_ADDR addr, char *contents_cache) 555{ 556 char bundle[BUNDLE_LEN]; 557 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER; 558 long long instr; 559 int val; 560 int template; 561 562 addr &= ~0x0f; 563 564 val = target_read_memory (addr, bundle, BUNDLE_LEN); 565 566 /* Check for L type instruction in 2nd slot, if present then 567 bump up the slot number to the 3rd slot */ 568 template = extract_bit_field (bundle, 0, 5); 569 if (slotnum == 1 && template_encoding_table[template][1] == L) 570 { 571 slotnum = 2; 572 } 573 574 memcpy (&instr, contents_cache, sizeof instr); 575 replace_slotN_contents (bundle, instr, slotnum); 576 if (val == 0) 577 target_write_memory (addr, bundle, BUNDLE_LEN); 578 579 return val; 580} 581 582/* We don't really want to use this, but remote.c needs to call it in order 583 to figure out if Z-packets are supported or not. Oh, well. */ 584const unsigned char * 585ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 586{ 587 static unsigned char breakpoint[] = 588 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; 589 *lenptr = sizeof (breakpoint); 590#if 0 591 *pcptr &= ~0x0f; 592#endif 593 return breakpoint; 594} 595 596static CORE_ADDR 597ia64_read_pc (ptid_t ptid) 598{ 599 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid); 600 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid); 601 int slot_num = (psr_value >> 41) & 3; 602 603 return pc_value | (slot_num * SLOT_MULTIPLIER); 604} 605 606void 607ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid) 608{ 609 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER; 610 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid); 611 psr_value &= ~(3LL << 41); 612 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41; 613 614 new_pc &= ~0xfLL; 615 616 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid); 617 write_register_pid (IA64_IP_REGNUM, new_pc, ptid); 618} 619 620#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f) 621 622/* Returns the address of the slot that's NSLOTS slots away from 623 the address ADDR. NSLOTS may be positive or negative. */ 624static CORE_ADDR 625rse_address_add(CORE_ADDR addr, int nslots) 626{ 627 CORE_ADDR new_addr; 628 int mandatory_nat_slots = nslots / 63; 629 int direction = nslots < 0 ? -1 : 1; 630 631 new_addr = addr + 8 * (nslots + mandatory_nat_slots); 632 633 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9)) 634 new_addr += 8 * direction; 635 636 if (IS_NaT_COLLECTION_ADDR(new_addr)) 637 new_addr += 8 * direction; 638 639 return new_addr; 640} 641 642static void 643ia64_read_reg (CORE_ADDR addr, void *buf, int len) 644{ 645 ULONGEST bspstore; 646 regcache_cooked_read_unsigned (current_regcache, IA64_BSPSTORE_REGNUM, 647 &bspstore); 648 if (addr >= bspstore) 649 { 650 ULONGEST bsp; 651 regcache_cooked_read_unsigned (current_regcache, IA64_BSP_REGNUM, 652 &bsp); 653 if (addr < bsp) 654 { 655 target_read_partial (¤t_target, TARGET_OBJECT_DIRTY, 656 (void*)&bspstore, buf, addr - bspstore, len); 657 return; 658 } 659 } 660 read_memory (addr, buf, len); 661} 662 663static void 664ia64_write_reg (CORE_ADDR addr, void *buf, int len) 665{ 666 ULONGEST bspstore; 667 regcache_cooked_read_unsigned (current_regcache, IA64_BSPSTORE_REGNUM, 668 &bspstore); 669 if (addr >= bspstore) 670 { 671 ULONGEST bsp; 672 regcache_cooked_read_unsigned (current_regcache, IA64_BSP_REGNUM, 673 &bsp); 674 if (addr < bsp) 675 { 676 target_write_partial (¤t_target, TARGET_OBJECT_DIRTY, 677 (void*)&bspstore, buf, addr - bspstore, len); 678 return; 679 } 680 } 681 write_memory (addr, buf, len); 682} 683 684static void 685ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 686 int regnum, void *buf) 687{ 688 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM) 689 { 690 ULONGEST bsp; 691 ULONGEST cfm; 692 CORE_ADDR reg; 693 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); 694 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 695 696 /* The bsp points at the end of the register frame so we 697 subtract the size of frame from it to get start of register frame. */ 698 bsp = rse_address_add (bsp, -(cfm & 0x7f)); 699 700 if ((cfm & 0x7f) > regnum - V32_REGNUM) 701 { 702 ULONGEST addr = rse_address_add (bsp, (regnum - V32_REGNUM)); 703 ia64_read_reg (addr, buf, register_size (current_gdbarch, regnum)); 704 } 705 else 706 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0); 707 } 708 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM) 709 { 710 ULONGEST unatN_val; 711 ULONGEST unat; 712 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat); 713 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0; 714 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val); 715 } 716 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) 717 { 718 ULONGEST natN_val = 0; 719 ULONGEST bsp; 720 ULONGEST cfm; 721 CORE_ADDR gr_addr = 0; 722 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); 723 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 724 725 /* The bsp points at the end of the register frame so we 726 subtract the size of frame from it to get start of register frame. */ 727 bsp = rse_address_add (bsp, -(cfm & 0x7f)); 728 729 if ((cfm & 0x7f) > regnum - V32_REGNUM) 730 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM)); 731 732 if (gr_addr != 0) 733 { 734 /* Compute address of nat collection bits. */ 735 CORE_ADDR nat_addr = gr_addr | 0x1f8; 736 CORE_ADDR nat_collection; 737 int nat_bit; 738 /* If our nat collection address is bigger than bsp, we have to get 739 the nat collection from rnat. Otherwise, we fetch the nat 740 collection from the computed address. */ 741 if (nat_addr >= bsp) 742 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection); 743 else 744 { 745 uint64_t tmp; 746 ia64_read_reg (nat_addr, &tmp, sizeof(tmp)); 747 nat_collection = tmp; 748 } 749 nat_bit = (gr_addr >> 3) & 0x3f; 750 natN_val = (nat_collection >> nat_bit) & 1; 751 } 752 753 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val); 754 } 755 else if (regnum == VBOF_REGNUM) 756 { 757 /* A virtual register frame start is provided for user convenience. 758 It can be calculated as the bsp - sof (sizeof frame). */ 759 ULONGEST bsp, vbsp; 760 ULONGEST cfm; 761 CORE_ADDR reg; 762 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); 763 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 764 765 /* The bsp points at the end of the register frame so we 766 subtract the size of frame from it to get beginning of frame. */ 767 vbsp = rse_address_add (bsp, -(cfm & 0x7f)); 768 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp); 769 } 770 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) 771 { 772 ULONGEST pr; 773 ULONGEST cfm; 774 ULONGEST prN_val; 775 CORE_ADDR reg; 776 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr); 777 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 778 779 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) 780 { 781 /* Fetch predicate register rename base from current frame 782 marker for this frame. */ 783 int rrb_pr = (cfm >> 32) & 0x3f; 784 785 /* Adjust the register number to account for register rotation. */ 786 regnum = VP16_REGNUM 787 + ((regnum - VP16_REGNUM) + rrb_pr) % 48; 788 } 789 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0; 790 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val); 791 } 792 else 793 memset (buf, 0, register_size (current_gdbarch, regnum)); 794} 795 796static void 797ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 798 int regnum, const void *buf) 799{ 800 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM) 801 { 802 ULONGEST bsp; 803 ULONGEST cfm; 804 CORE_ADDR reg; 805 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); 806 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 807 808 bsp = rse_address_add (bsp, -(cfm & 0x7f)); 809 810 if ((cfm & 0x7f) > regnum - V32_REGNUM) 811 { 812 ULONGEST addr = rse_address_add (bsp, (regnum - V32_REGNUM)); 813 ia64_write_reg (addr, (void *)buf, 8); 814 } 815 } 816 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM) 817 { 818 ULONGEST unatN_val, unat, unatN_mask; 819 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat); 820 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum)); 821 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM)); 822 if (unatN_val == 0) 823 unat &= ~unatN_mask; 824 else if (unatN_val == 1) 825 unat |= unatN_mask; 826 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat); 827 } 828 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) 829 { 830 ULONGEST natN_val; 831 ULONGEST bsp; 832 ULONGEST cfm; 833 CORE_ADDR gr_addr = 0; 834 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp); 835 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 836 837 /* The bsp points at the end of the register frame so we 838 subtract the size of frame from it to get start of register frame. */ 839 bsp = rse_address_add (bsp, -(cfm & 0x7f)); 840 841 if ((cfm & 0x7f) > regnum - V32_REGNUM) 842 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM)); 843 844 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum)); 845 846 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1)) 847 { 848 /* Compute address of nat collection bits. */ 849 CORE_ADDR nat_addr = gr_addr | 0x1f8; 850 CORE_ADDR nat_collection; 851 int natN_bit = (gr_addr >> 3) & 0x3f; 852 ULONGEST natN_mask = (1LL << natN_bit); 853 /* If our nat collection address is bigger than bsp, we have to get 854 the nat collection from rnat. Otherwise, we fetch the nat 855 collection from the computed address. */ 856 if (nat_addr >= bsp) 857 { 858 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection); 859 if (natN_val) 860 nat_collection |= natN_mask; 861 else 862 nat_collection &= ~natN_mask; 863 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection); 864 } 865 else 866 { 867 uint64_t tmp; 868 ia64_read_reg (nat_addr, &tmp, sizeof(tmp)); 869 nat_collection = tmp; 870 if (natN_val) 871 nat_collection |= natN_mask; 872 else 873 nat_collection &= ~natN_mask; 874 tmp = nat_collection; 875 ia64_write_reg (nat_addr, &tmp, sizeof(tmp)); 876 } 877 } 878 } 879 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) 880 { 881 ULONGEST pr; 882 ULONGEST cfm; 883 ULONGEST prN_val; 884 ULONGEST prN_mask; 885 886 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr); 887 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm); 888 889 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) 890 { 891 /* Fetch predicate register rename base from current frame 892 marker for this frame. */ 893 int rrb_pr = (cfm >> 32) & 0x3f; 894 895 /* Adjust the register number to account for register rotation. */ 896 regnum = VP16_REGNUM 897 + ((regnum - VP16_REGNUM) + rrb_pr) % 48; 898 } 899 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum)); 900 prN_mask = (1LL << (regnum - VP0_REGNUM)); 901 if (prN_val == 0) 902 pr &= ~prN_mask; 903 else if (prN_val == 1) 904 pr |= prN_mask; 905 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr); 906 } 907} 908 909/* The ia64 needs to convert between various ieee floating-point formats 910 and the special ia64 floating point register format. */ 911 912static int 913ia64_convert_register_p (int regno, struct type *type) 914{ 915 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM); 916} 917 918static void 919ia64_register_to_value (struct frame_info *frame, int regnum, 920 struct type *valtype, void *out) 921{ 922 char in[MAX_REGISTER_SIZE]; 923 frame_register_read (frame, regnum, in); 924 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype); 925} 926 927static void 928ia64_value_to_register (struct frame_info *frame, int regnum, 929 struct type *valtype, const void *in) 930{ 931 char out[MAX_REGISTER_SIZE]; 932 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext); 933 put_frame_register (frame, regnum, out); 934} 935 936 937/* Limit the number of skipped non-prologue instructions since examining 938 of the prologue is expensive. */ 939static int max_skip_non_prologue_insns = 40; 940 941/* Given PC representing the starting address of a function, and 942 LIM_PC which is the (sloppy) limit to which to scan when looking 943 for a prologue, attempt to further refine this limit by using 944 the line data in the symbol table. If successful, a better guess 945 on where the prologue ends is returned, otherwise the previous 946 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag 947 which will be set to indicate whether the returned limit may be 948 used with no further scanning in the event that the function is 949 frameless. */ 950 951/* FIXME: cagney/2004-02-14: This function and logic have largely been 952 superseded by skip_prologue_using_sal. */ 953 954static CORE_ADDR 955refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit) 956{ 957 struct symtab_and_line prologue_sal; 958 CORE_ADDR start_pc = pc; 959 960 /* Start off not trusting the limit. */ 961 *trust_limit = 0; 962 963 prologue_sal = find_pc_line (pc, 0); 964 if (prologue_sal.line != 0) 965 { 966 int i; 967 CORE_ADDR addr = prologue_sal.end; 968 969 /* Handle the case in which compiler's optimizer/scheduler 970 has moved instructions into the prologue. We scan ahead 971 in the function looking for address ranges whose corresponding 972 line number is less than or equal to the first one that we 973 found for the function. (It can be less than when the 974 scheduler puts a body instruction before the first prologue 975 instruction.) */ 976 for (i = 2 * max_skip_non_prologue_insns; 977 i > 0 && (lim_pc == 0 || addr < lim_pc); 978 i--) 979 { 980 struct symtab_and_line sal; 981 982 sal = find_pc_line (addr, 0); 983 if (sal.line == 0) 984 break; 985 if (sal.line <= prologue_sal.line 986 && sal.symtab == prologue_sal.symtab) 987 { 988 prologue_sal = sal; 989 } 990 addr = sal.end; 991 } 992 993 if (lim_pc == 0 || prologue_sal.end < lim_pc) 994 { 995 lim_pc = prologue_sal.end; 996 if (start_pc == get_pc_function_start (lim_pc)) 997 *trust_limit = 1; 998 } 999 } 1000 return lim_pc; 1001} 1002 1003#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \ 1004 || (8 <= (_regnum_) && (_regnum_) <= 11) \ 1005 || (14 <= (_regnum_) && (_regnum_) <= 31)) 1006#define imm9(_instr_) \ 1007 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \ 1008 | (((_instr_) & 0x00008000000LL) >> 20) \ 1009 | (((_instr_) & 0x00000001fc0LL) >> 6)) 1010 1011/* Allocate and initialize a frame cache. */ 1012 1013static struct ia64_frame_cache * 1014ia64_alloc_frame_cache (void) 1015{ 1016 struct ia64_frame_cache *cache; 1017 int i; 1018 1019 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache); 1020 1021 /* Base address. */ 1022 cache->base = 0; 1023 cache->pc = 0; 1024 cache->cfm = 0; 1025 cache->prev_cfm = 0; 1026 cache->sof = 0; 1027 cache->sol = 0; 1028 cache->sor = 0; 1029 cache->bsp = 0; 1030 cache->fp_reg = 0; 1031 cache->frameless = 1; 1032 1033 for (i = 0; i < NUM_IA64_RAW_REGS; i++) 1034 cache->saved_regs[i] = 0; 1035 1036 return cache; 1037} 1038 1039static CORE_ADDR 1040examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache) 1041{ 1042 CORE_ADDR next_pc; 1043 CORE_ADDR last_prologue_pc = pc; 1044 instruction_type it; 1045 long long instr; 1046 int cfm_reg = 0; 1047 int ret_reg = 0; 1048 int fp_reg = 0; 1049 int unat_save_reg = 0; 1050 int pr_save_reg = 0; 1051 int mem_stack_frame_size = 0; 1052 int spill_reg = 0; 1053 CORE_ADDR spill_addr = 0; 1054 char instores[8]; 1055 char infpstores[8]; 1056 char reg_contents[256]; 1057 int trust_limit; 1058 int frameless = 1; 1059 int i; 1060 CORE_ADDR addr; 1061 char buf[8]; 1062 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr; 1063 1064 memset (instores, 0, sizeof instores); 1065 memset (infpstores, 0, sizeof infpstores); 1066 memset (reg_contents, 0, sizeof reg_contents); 1067 1068 if (cache->after_prologue != 0 1069 && cache->after_prologue <= lim_pc) 1070 return cache->after_prologue; 1071 1072 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit); 1073 next_pc = fetch_instruction (pc, &it, &instr); 1074 1075 /* We want to check if we have a recognizable function start before we 1076 look ahead for a prologue. */ 1077 if (pc < lim_pc && next_pc 1078 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL)) 1079 { 1080 /* alloc - start of a regular function. */ 1081 int sor = (int) ((instr & 0x00078000000LL) >> 27); 1082 int sol = (int) ((instr & 0x00007f00000LL) >> 20); 1083 int sof = (int) ((instr & 0x000000fe000LL) >> 13); 1084 int rN = (int) ((instr & 0x00000001fc0LL) >> 6); 1085 1086 /* Verify that the current cfm matches what we think is the 1087 function start. If we have somehow jumped within a function, 1088 we do not want to interpret the prologue and calculate the 1089 addresses of various registers such as the return address. 1090 We will instead treat the frame as frameless. */ 1091 if (!next_frame || 1092 (sof == (cache->cfm & 0x7f) && 1093 sol == ((cache->cfm >> 7) & 0x7f))) 1094 frameless = 0; 1095 1096 cfm_reg = rN; 1097 last_prologue_pc = next_pc; 1098 pc = next_pc; 1099 } 1100 else 1101 { 1102 /* Look for a leaf routine. */ 1103 if (pc < lim_pc && next_pc 1104 && (it == I || it == M) 1105 && ((instr & 0x1ee00000000LL) == 0x10800000000LL)) 1106 { 1107 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */ 1108 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13) 1109 | ((instr & 0x001f8000000LL) >> 20) 1110 | ((instr & 0x000000fe000LL) >> 13)); 1111 int rM = (int) ((instr & 0x00007f00000LL) >> 20); 1112 int rN = (int) ((instr & 0x00000001fc0LL) >> 6); 1113 int qp = (int) (instr & 0x0000000003fLL); 1114 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0) 1115 { 1116 /* mov r2, r12 - beginning of leaf routine */ 1117 fp_reg = rN; 1118 last_prologue_pc = next_pc; 1119 } 1120 } 1121 1122 /* If we don't recognize a regular function or leaf routine, we are 1123 done. */ 1124 if (!fp_reg) 1125 { 1126 pc = lim_pc; 1127 if (trust_limit) 1128 last_prologue_pc = lim_pc; 1129 } 1130 } 1131 1132 /* Loop, looking for prologue instructions, keeping track of 1133 where preserved registers were spilled. */ 1134 while (pc < lim_pc) 1135 { 1136 next_pc = fetch_instruction (pc, &it, &instr); 1137 if (next_pc == 0) 1138 break; 1139 1140 if (it == B && ((instr & 0x1e1f800003f) != 0x04000000000)) 1141 { 1142 /* Exit loop upon hitting a non-nop branch instruction. */ 1143 if (trust_limit) 1144 lim_pc = pc; 1145 break; 1146 } 1147 else if (((instr & 0x3fLL) != 0LL) && 1148 (frameless || ret_reg != 0)) 1149 { 1150 /* Exit loop upon hitting a predicated instruction if 1151 we already have the return register or if we are frameless. */ 1152 if (trust_limit) 1153 lim_pc = pc; 1154 break; 1155 } 1156 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL)) 1157 { 1158 /* Move from BR */ 1159 int b2 = (int) ((instr & 0x0000000e000LL) >> 13); 1160 int rN = (int) ((instr & 0x00000001fc0LL) >> 6); 1161 int qp = (int) (instr & 0x0000000003f); 1162 1163 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0) 1164 { 1165 ret_reg = rN; 1166 last_prologue_pc = next_pc; 1167 } 1168 } 1169 else if ((it == I || it == M) 1170 && ((instr & 0x1ee00000000LL) == 0x10800000000LL)) 1171 { 1172 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */ 1173 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13) 1174 | ((instr & 0x001f8000000LL) >> 20) 1175 | ((instr & 0x000000fe000LL) >> 13)); 1176 int rM = (int) ((instr & 0x00007f00000LL) >> 20); 1177 int rN = (int) ((instr & 0x00000001fc0LL) >> 6); 1178 int qp = (int) (instr & 0x0000000003fLL); 1179 1180 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0) 1181 { 1182 /* mov rN, r12 */ 1183 fp_reg = rN; 1184 last_prologue_pc = next_pc; 1185 } 1186 else if (qp == 0 && rN == 12 && rM == 12) 1187 { 1188 /* adds r12, -mem_stack_frame_size, r12 */ 1189 mem_stack_frame_size -= imm; 1190 last_prologue_pc = next_pc; 1191 } 1192 else if (qp == 0 && rN == 2 1193 && ((rM == fp_reg && fp_reg != 0) || rM == 12)) 1194 { 1195 char buf[MAX_REGISTER_SIZE]; 1196 CORE_ADDR saved_sp = 0; 1197 /* adds r2, spilloffset, rFramePointer 1198 or 1199 adds r2, spilloffset, r12 1200 1201 Get ready for stf.spill or st8.spill instructions. 1202 The address to start spilling at is loaded into r2. 1203 FIXME: Why r2? That's what gcc currently uses; it 1204 could well be different for other compilers. */ 1205 1206 /* Hmm... whether or not this will work will depend on 1207 where the pc is. If it's still early in the prologue 1208 this'll be wrong. FIXME */ 1209 if (next_frame) 1210 { 1211 frame_unwind_register (next_frame, sp_regnum, buf); 1212 saved_sp = extract_unsigned_integer (buf, 8); 1213 } 1214 spill_addr = saved_sp 1215 + (rM == 12 ? 0 : mem_stack_frame_size) 1216 + imm; 1217 spill_reg = rN; 1218 last_prologue_pc = next_pc; 1219 } 1220 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] && 1221 rN < 256 && imm == 0) 1222 { 1223 /* mov rN, rM where rM is an input register */ 1224 reg_contents[rN] = rM; 1225 last_prologue_pc = next_pc; 1226 } 1227 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 && 1228 rM == 2) 1229 { 1230 /* mov r12, r2 */ 1231 last_prologue_pc = next_pc; 1232 break; 1233 } 1234 } 1235 else if (it == M 1236 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL) 1237 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) )) 1238 { 1239 /* stf.spill [rN] = fM, imm9 1240 or 1241 stf.spill [rN] = fM */ 1242 1243 int imm = imm9(instr); 1244 int rN = (int) ((instr & 0x00007f00000LL) >> 20); 1245 int fM = (int) ((instr & 0x000000fe000LL) >> 13); 1246 int qp = (int) (instr & 0x0000000003fLL); 1247 if (qp == 0 && rN == spill_reg && spill_addr != 0 1248 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31))) 1249 { 1250 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr; 1251 1252 if ((instr & 0x1efc0000000) == 0x0eec0000000) 1253 spill_addr += imm; 1254 else 1255 spill_addr = 0; /* last one; must be done */ 1256 last_prologue_pc = next_pc; 1257 } 1258 } 1259 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL)) 1260 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) ) 1261 { 1262 /* mov.m rN = arM 1263 or 1264 mov.i rN = arM */ 1265 1266 int arM = (int) ((instr & 0x00007f00000LL) >> 20); 1267 int rN = (int) ((instr & 0x00000001fc0LL) >> 6); 1268 int qp = (int) (instr & 0x0000000003fLL); 1269 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */) 1270 { 1271 /* We have something like "mov.m r3 = ar.unat". Remember the 1272 r3 (or whatever) and watch for a store of this register... */ 1273 unat_save_reg = rN; 1274 last_prologue_pc = next_pc; 1275 } 1276 } 1277 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL)) 1278 { 1279 /* mov rN = pr */ 1280 int rN = (int) ((instr & 0x00000001fc0LL) >> 6); 1281 int qp = (int) (instr & 0x0000000003fLL); 1282 if (qp == 0 && isScratch (rN)) 1283 { 1284 pr_save_reg = rN; 1285 last_prologue_pc = next_pc; 1286 } 1287 } 1288 else if (it == M 1289 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL) 1290 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL))) 1291 { 1292 /* st8 [rN] = rM 1293 or 1294 st8 [rN] = rM, imm9 */ 1295 int rN = (int) ((instr & 0x00007f00000LL) >> 20); 1296 int rM = (int) ((instr & 0x000000fe000LL) >> 13); 1297 int qp = (int) (instr & 0x0000000003fLL); 1298 int indirect = rM < 256 ? reg_contents[rM] : 0; 1299 if (qp == 0 && rN == spill_reg && spill_addr != 0 1300 && (rM == unat_save_reg || rM == pr_save_reg)) 1301 { 1302 /* We've found a spill of either the UNAT register or the PR 1303 register. (Well, not exactly; what we've actually found is 1304 a spill of the register that UNAT or PR was moved to). 1305 Record that fact and move on... */ 1306 if (rM == unat_save_reg) 1307 { 1308 /* Track UNAT register */ 1309 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr; 1310 unat_save_reg = 0; 1311 } 1312 else 1313 { 1314 /* Track PR register */ 1315 cache->saved_regs[IA64_PR_REGNUM] = spill_addr; 1316 pr_save_reg = 0; 1317 } 1318 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL) 1319 /* st8 [rN] = rM, imm9 */ 1320 spill_addr += imm9(instr); 1321 else 1322 spill_addr = 0; /* must be done spilling */ 1323 last_prologue_pc = next_pc; 1324 } 1325 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32]) 1326 { 1327 /* Allow up to one store of each input register. */ 1328 instores[rM-32] = 1; 1329 last_prologue_pc = next_pc; 1330 } 1331 else if (qp == 0 && 32 <= indirect && indirect < 40 && 1332 !instores[indirect-32]) 1333 { 1334 /* Allow an indirect store of an input register. */ 1335 instores[indirect-32] = 1; 1336 last_prologue_pc = next_pc; 1337 } 1338 } 1339 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL)) 1340 { 1341 /* One of 1342 st1 [rN] = rM 1343 st2 [rN] = rM 1344 st4 [rN] = rM 1345 st8 [rN] = rM 1346 Note that the st8 case is handled in the clause above. 1347 1348 Advance over stores of input registers. One store per input 1349 register is permitted. */ 1350 int rM = (int) ((instr & 0x000000fe000LL) >> 13); 1351 int qp = (int) (instr & 0x0000000003fLL); 1352 int indirect = rM < 256 ? reg_contents[rM] : 0; 1353 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32]) 1354 { 1355 instores[rM-32] = 1; 1356 last_prologue_pc = next_pc; 1357 } 1358 else if (qp == 0 && 32 <= indirect && indirect < 40 && 1359 !instores[indirect-32]) 1360 { 1361 /* Allow an indirect store of an input register. */ 1362 instores[indirect-32] = 1; 1363 last_prologue_pc = next_pc; 1364 } 1365 } 1366 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL)) 1367 { 1368 /* Either 1369 stfs [rN] = fM 1370 or 1371 stfd [rN] = fM 1372 1373 Advance over stores of floating point input registers. Again 1374 one store per register is permitted */ 1375 int fM = (int) ((instr & 0x000000fe000LL) >> 13); 1376 int qp = (int) (instr & 0x0000000003fLL); 1377 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8]) 1378 { 1379 infpstores[fM-8] = 1; 1380 last_prologue_pc = next_pc; 1381 } 1382 } 1383 else if (it == M 1384 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL) 1385 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL))) 1386 { 1387 /* st8.spill [rN] = rM 1388 or 1389 st8.spill [rN] = rM, imm9 */ 1390 int rN = (int) ((instr & 0x00007f00000LL) >> 20); 1391 int rM = (int) ((instr & 0x000000fe000LL) >> 13); 1392 int qp = (int) (instr & 0x0000000003fLL); 1393 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7) 1394 { 1395 /* We've found a spill of one of the preserved general purpose 1396 regs. Record the spill address and advance the spill 1397 register if appropriate. */ 1398 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr; 1399 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL) 1400 /* st8.spill [rN] = rM, imm9 */ 1401 spill_addr += imm9(instr); 1402 else 1403 spill_addr = 0; /* Done spilling */ 1404 last_prologue_pc = next_pc; 1405 } 1406 } 1407 1408 pc = next_pc; 1409 } 1410 1411 /* If not frameless and we aren't called by skip_prologue, then we need to calculate 1412 registers for the previous frame which will be needed later. */ 1413 1414 if (!frameless && next_frame) 1415 { 1416 /* Extract the size of the rotating portion of the stack 1417 frame and the register rename base from the current 1418 frame marker. */ 1419 cfm = cache->cfm; 1420 sor = cache->sor; 1421 sof = cache->sof; 1422 sol = cache->sol; 1423 rrb_gr = (cfm >> 18) & 0x7f; 1424 1425 /* Find the bof (beginning of frame). */ 1426 bof = rse_address_add (cache->bsp, -sof); 1427 1428 for (i = 0, addr = bof; 1429 i < sof; 1430 i++, addr += 8) 1431 { 1432 if (IS_NaT_COLLECTION_ADDR (addr)) 1433 { 1434 addr += 8; 1435 } 1436 if (i+32 == cfm_reg) 1437 cache->saved_regs[IA64_CFM_REGNUM] = addr; 1438 if (i+32 == ret_reg) 1439 cache->saved_regs[IA64_VRAP_REGNUM] = addr; 1440 if (i+32 == fp_reg) 1441 cache->saved_regs[IA64_VFP_REGNUM] = addr; 1442 } 1443 1444 /* For the previous argument registers we require the previous bof. 1445 If we can't find the previous cfm, then we can do nothing. */ 1446 cfm = 0; 1447 if (cache->saved_regs[IA64_CFM_REGNUM] != 0) 1448 { 1449 uint64_t tmp; 1450 ia64_read_reg (cache->saved_regs[IA64_CFM_REGNUM], &tmp, sizeof(tmp)); 1451 cfm = tmp; 1452 } 1453 else if (cfm_reg != 0) 1454 { 1455 frame_unwind_register (next_frame, cfm_reg, buf); 1456 cfm = extract_unsigned_integer (buf, 8); 1457 } 1458 cache->prev_cfm = cfm; 1459 1460 if (cfm != 0) 1461 { 1462 sor = ((cfm >> 14) & 0xf) * 8; 1463 sof = (cfm & 0x7f); 1464 sol = (cfm >> 7) & 0x7f; 1465 rrb_gr = (cfm >> 18) & 0x7f; 1466 1467 /* The previous bof only requires subtraction of the sol (size of locals) 1468 due to the overlap between output and input of subsequent frames. */ 1469 bof = rse_address_add (bof, -sol); 1470 1471 for (i = 0, addr = bof; 1472 i < sof; 1473 i++, addr += 8) 1474 { 1475 if (IS_NaT_COLLECTION_ADDR (addr)) 1476 { 1477 addr += 8; 1478 } 1479 if (i < sor) 1480 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)] 1481 = addr; 1482 else 1483 cache->saved_regs[IA64_GR32_REGNUM + i] = addr; 1484 } 1485 1486 } 1487 } 1488 1489 /* Try and trust the lim_pc value whenever possible. */ 1490 if (trust_limit && lim_pc >= last_prologue_pc) 1491 last_prologue_pc = lim_pc; 1492 1493 cache->frameless = frameless; 1494 cache->after_prologue = last_prologue_pc; 1495 cache->mem_stack_frame_size = mem_stack_frame_size; 1496 cache->fp_reg = fp_reg; 1497 1498 return last_prologue_pc; 1499} 1500 1501CORE_ADDR 1502ia64_skip_prologue (CORE_ADDR pc) 1503{ 1504 struct ia64_frame_cache cache; 1505 cache.base = 0; 1506 cache.after_prologue = 0; 1507 cache.cfm = 0; 1508 cache.bsp = 0; 1509 1510 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */ 1511 return examine_prologue (pc, pc+1024, 0, &cache); 1512} 1513 1514 1515/* Normal frames. */ 1516 1517static struct ia64_frame_cache * 1518ia64_frame_cache (struct frame_info *next_frame, void **this_cache) 1519{ 1520 struct ia64_frame_cache *cache; 1521 char buf[8]; 1522 CORE_ADDR cfm, sof, sol, bsp, psr; 1523 int i; 1524 1525 if (*this_cache) 1526 return *this_cache; 1527 1528 cache = ia64_alloc_frame_cache (); 1529 *this_cache = cache; 1530 1531 frame_unwind_register (next_frame, sp_regnum, buf); 1532 cache->saved_sp = extract_unsigned_integer (buf, 8); 1533 1534 /* We always want the bsp to point to the end of frame. 1535 This way, we can always get the beginning of frame (bof) 1536 by subtracting frame size. */ 1537 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 1538 cache->bsp = extract_unsigned_integer (buf, 8); 1539 1540 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf); 1541 psr = extract_unsigned_integer (buf, 8); 1542 1543 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf); 1544 cfm = extract_unsigned_integer (buf, 8); 1545 1546 cache->sof = (cfm & 0x7f); 1547 cache->sol = (cfm >> 7) & 0x7f; 1548 cache->sor = ((cfm >> 14) & 0xf) * 8; 1549 1550 cache->cfm = cfm; 1551 1552 cache->pc = frame_func_unwind (next_frame); 1553 1554 if (cache->pc != 0) 1555 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache); 1556 1557 cache->base = cache->saved_sp + cache->mem_stack_frame_size; 1558 1559 return cache; 1560} 1561 1562static void 1563ia64_frame_this_id (struct frame_info *next_frame, void **this_cache, 1564 struct frame_id *this_id) 1565{ 1566 struct ia64_frame_cache *cache = 1567 ia64_frame_cache (next_frame, this_cache); 1568 1569 /* This marks the outermost frame. */ 1570 if (cache->base == 0) 1571 return; 1572 1573 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp); 1574 if (gdbarch_debug >= 1) 1575 fprintf_unfiltered (gdb_stdlog, 1576 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n", 1577 paddr_nz (this_id->code_addr), 1578 paddr_nz (this_id->stack_addr), 1579 paddr_nz (cache->bsp), next_frame); 1580} 1581 1582static void 1583ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache, 1584 int regnum, int *optimizedp, 1585 enum lval_type *lvalp, CORE_ADDR *addrp, 1586 int *realnump, void *valuep) 1587{ 1588 struct ia64_frame_cache *cache = 1589 ia64_frame_cache (next_frame, this_cache); 1590 char dummy_valp[MAX_REGISTER_SIZE]; 1591 char buf[8]; 1592 1593 gdb_assert (regnum >= 0); 1594 1595 if (!target_has_registers) 1596 error ("No registers."); 1597 1598 *optimizedp = 0; 1599 *addrp = 0; 1600 *lvalp = not_lval; 1601 *realnump = -1; 1602 1603 /* Rather than check each time if valuep is non-null, supply a dummy buffer 1604 when valuep is not supplied. */ 1605 if (!valuep) 1606 valuep = dummy_valp; 1607 1608 memset (valuep, 0, register_size (current_gdbarch, regnum)); 1609 1610 if (regnum == SP_REGNUM) 1611 { 1612 /* Handle SP values for all frames but the topmost. */ 1613 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), 1614 cache->base); 1615 } 1616 else if (regnum == IA64_BSP_REGNUM) 1617 { 1618 char cfm_valuep[MAX_REGISTER_SIZE]; 1619 int cfm_optim; 1620 int cfm_realnum; 1621 enum lval_type cfm_lval; 1622 CORE_ADDR cfm_addr; 1623 CORE_ADDR bsp, prev_cfm, prev_bsp; 1624 1625 /* We want to calculate the previous bsp as the end of the previous register stack frame. 1626 This corresponds to what the hardware bsp register will be if we pop the frame 1627 back which is why we might have been called. We know the beginning of the current 1628 frame is cache->bsp - cache->sof. This value in the previous frame points to 1629 the start of the output registers. We can calculate the end of that frame by adding 1630 the size of output (sof (size of frame) - sol (size of locals)). */ 1631 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM, 1632 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep); 1633 prev_cfm = extract_unsigned_integer (cfm_valuep, 8); 1634 1635 bsp = rse_address_add (cache->bsp, -(cache->sof)); 1636 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f)); 1637 1638 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), 1639 prev_bsp); 1640 } 1641 else if (regnum == IA64_CFM_REGNUM) 1642 { 1643 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM]; 1644 1645 if (addr != 0) 1646 { 1647 *lvalp = lval_memory; 1648 *addrp = addr; 1649 ia64_read_reg (addr, valuep, register_size (current_gdbarch, regnum)); 1650 } 1651 else if (cache->prev_cfm) 1652 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm); 1653 else if (cache->frameless) 1654 { 1655 CORE_ADDR cfm = 0; 1656 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep); 1657 } 1658 } 1659 else if (regnum == IA64_VFP_REGNUM) 1660 { 1661 /* If the function in question uses an automatic register (r32-r127) 1662 for the frame pointer, it'll be found by ia64_find_saved_register() 1663 above. If the function lacks one of these frame pointers, we can 1664 still provide a value since we know the size of the frame. */ 1665 CORE_ADDR vfp = cache->base; 1666 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp); 1667 } 1668 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) 1669 { 1670 char pr_valuep[MAX_REGISTER_SIZE]; 1671 int pr_optim; 1672 int pr_realnum; 1673 enum lval_type pr_lval; 1674 CORE_ADDR pr_addr; 1675 ULONGEST prN_val; 1676 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM, 1677 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep); 1678 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) 1679 { 1680 /* Fetch predicate register rename base from current frame 1681 marker for this frame. */ 1682 int rrb_pr = (cache->cfm >> 32) & 0x3f; 1683 1684 /* Adjust the register number to account for register rotation. */ 1685 regnum = VP16_REGNUM 1686 + ((regnum - VP16_REGNUM) + rrb_pr) % 48; 1687 } 1688 prN_val = extract_bit_field ((unsigned char *) pr_valuep, 1689 regnum - VP0_REGNUM, 1); 1690 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val); 1691 } 1692 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM) 1693 { 1694 char unat_valuep[MAX_REGISTER_SIZE]; 1695 int unat_optim; 1696 int unat_realnum; 1697 enum lval_type unat_lval; 1698 CORE_ADDR unat_addr; 1699 ULONGEST unatN_val; 1700 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM, 1701 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep); 1702 unatN_val = extract_bit_field ((unsigned char *) unat_valuep, 1703 regnum - IA64_NAT0_REGNUM, 1); 1704 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), 1705 unatN_val); 1706 } 1707 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) 1708 { 1709 int natval = 0; 1710 /* Find address of general register corresponding to nat bit we're 1711 interested in. */ 1712 CORE_ADDR gr_addr; 1713 1714 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM 1715 + IA64_GR0_REGNUM]; 1716 if (gr_addr != 0) 1717 { 1718 /* Compute address of nat collection bits. */ 1719 CORE_ADDR nat_addr = gr_addr | 0x1f8; 1720 CORE_ADDR bsp; 1721 CORE_ADDR nat_collection; 1722 int nat_bit; 1723 /* If our nat collection address is bigger than bsp, we have to get 1724 the nat collection from rnat. Otherwise, we fetch the nat 1725 collection from the computed address. */ 1726 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 1727 bsp = extract_unsigned_integer (buf, 8); 1728 if (nat_addr >= bsp) 1729 { 1730 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf); 1731 nat_collection = extract_unsigned_integer (buf, 8); 1732 } 1733 else 1734 { 1735 uint64_t tmp; 1736 ia64_read_reg (nat_addr, &tmp, sizeof(tmp)); 1737 nat_collection = tmp; 1738 } 1739 nat_bit = (gr_addr >> 3) & 0x3f; 1740 natval = (nat_collection >> nat_bit) & 1; 1741 } 1742 1743 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval); 1744 } 1745 else if (regnum == IA64_IP_REGNUM) 1746 { 1747 CORE_ADDR pc = 0; 1748 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM]; 1749 1750 if (addr != 0) 1751 { 1752 *lvalp = lval_memory; 1753 *addrp = addr; 1754 ia64_read_reg (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM)); 1755 pc = extract_unsigned_integer (buf, 8); 1756 } 1757 else if (cache->frameless) 1758 { 1759 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf); 1760 pc = extract_unsigned_integer (buf, 8); 1761 } 1762 pc &= ~0xf; 1763 store_unsigned_integer (valuep, 8, pc); 1764 } 1765 else if (regnum == IA64_PSR_REGNUM) 1766 { 1767 /* We don't know how to get the complete previous PSR, but we need it for 1768 the slot information when we unwind the pc (pc is formed of IP register 1769 plus slot information from PSR). To get the previous slot information, 1770 we mask it off the return address. */ 1771 ULONGEST slot_num = 0; 1772 CORE_ADDR pc= 0; 1773 CORE_ADDR psr = 0; 1774 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM]; 1775 1776 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf); 1777 psr = extract_unsigned_integer (buf, 8); 1778 1779 if (addr != 0) 1780 { 1781 *lvalp = lval_memory; 1782 *addrp = addr; 1783 ia64_read_reg (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM)); 1784 pc = extract_unsigned_integer (buf, 8); 1785 } 1786 else if (cache->frameless) 1787 { 1788 CORE_ADDR pc; 1789 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf); 1790 pc = extract_unsigned_integer (buf, 8); 1791 } 1792 psr &= ~(3LL << 41); 1793 slot_num = pc & 0x3LL; 1794 psr |= (CORE_ADDR)slot_num << 41; 1795 store_unsigned_integer (valuep, 8, psr); 1796 } 1797 else if (regnum == IA64_BR0_REGNUM) 1798 { 1799 CORE_ADDR br0 = 0; 1800 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM]; 1801 if (addr != 0) 1802 { 1803 *lvalp = lval_memory; 1804 *addrp = addr; 1805 ia64_read_reg (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM)); 1806 br0 = extract_unsigned_integer (buf, 8); 1807 } 1808 store_unsigned_integer (valuep, 8, br0); 1809 } 1810 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) || 1811 (regnum >= V32_REGNUM && regnum <= V127_REGNUM)) 1812 { 1813 CORE_ADDR addr = 0; 1814 if (regnum >= V32_REGNUM) 1815 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM); 1816 addr = cache->saved_regs[regnum]; 1817 if (addr != 0) 1818 { 1819 *lvalp = lval_memory; 1820 *addrp = addr; 1821 ia64_read_reg (addr, valuep, register_size (current_gdbarch, regnum)); 1822 } 1823 else if (cache->frameless) 1824 { 1825 char r_valuep[MAX_REGISTER_SIZE]; 1826 int r_optim; 1827 int r_realnum; 1828 enum lval_type r_lval; 1829 CORE_ADDR r_addr; 1830 CORE_ADDR prev_cfm, prev_bsp, prev_bof; 1831 CORE_ADDR addr = 0; 1832 1833 if (regnum >= V32_REGNUM) 1834 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM); 1835 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM, 1836 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep); 1837 prev_cfm = extract_unsigned_integer (r_valuep, 8); 1838 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM, 1839 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep); 1840 prev_bsp = extract_unsigned_integer (r_valuep, 8); 1841 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f)); 1842 1843 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM)); 1844 *lvalp = lval_memory; 1845 *addrp = addr; 1846 ia64_read_reg (addr, valuep, register_size (current_gdbarch, regnum)); 1847 } 1848 } 1849 else 1850 { 1851 CORE_ADDR addr = 0; 1852 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM) 1853 { 1854 /* Fetch floating point register rename base from current 1855 frame marker for this frame. */ 1856 int rrb_fr = (cache->cfm >> 25) & 0x7f; 1857 1858 /* Adjust the floating point register number to account for 1859 register rotation. */ 1860 regnum = IA64_FR32_REGNUM 1861 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96; 1862 } 1863 1864 /* If we have stored a memory address, access the register. */ 1865 addr = cache->saved_regs[regnum]; 1866 if (addr != 0) 1867 { 1868 *lvalp = lval_memory; 1869 *addrp = addr; 1870 ia64_read_reg (addr, valuep, register_size (current_gdbarch, regnum)); 1871 } 1872 /* Otherwise, punt and get the current value of the register. */ 1873 else 1874 frame_unwind_register (next_frame, regnum, valuep); 1875 } 1876 1877 if (gdbarch_debug >= 1) 1878 fprintf_unfiltered (gdb_stdlog, 1879 "regular prev register <%d> <%s> is 0x%s\n", regnum, 1880 (((unsigned) regnum <= IA64_NAT127_REGNUM) 1881 ? ia64_register_names[regnum] : "r??"), 1882 paddr_nz (extract_unsigned_integer (valuep, 8))); 1883} 1884 1885static const struct frame_unwind ia64_frame_unwind = 1886{ 1887 NORMAL_FRAME, 1888 &ia64_frame_this_id, 1889 &ia64_frame_prev_register 1890}; 1891 1892static const struct frame_unwind * 1893ia64_frame_sniffer (struct frame_info *next_frame) 1894{ 1895 return &ia64_frame_unwind; 1896} 1897 1898/* Signal trampolines. */ 1899 1900static void 1901ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache) 1902{ 1903 if (SIGCONTEXT_REGISTER_ADDRESS) 1904 { 1905 int regno; 1906 1907 cache->saved_regs[IA64_VRAP_REGNUM] = 1908 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM); 1909 cache->saved_regs[IA64_CFM_REGNUM] = 1910 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM); 1911 cache->saved_regs[IA64_PSR_REGNUM] = 1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM); 1913 cache->saved_regs[IA64_BSP_REGNUM] = 1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM); 1915 cache->saved_regs[IA64_RNAT_REGNUM] = 1916 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM); 1917 cache->saved_regs[IA64_CCV_REGNUM] = 1918 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM); 1919 cache->saved_regs[IA64_UNAT_REGNUM] = 1920 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM); 1921 cache->saved_regs[IA64_FPSR_REGNUM] = 1922 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM); 1923 cache->saved_regs[IA64_PFS_REGNUM] = 1924 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM); 1925 cache->saved_regs[IA64_LC_REGNUM] = 1926 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM); 1927 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++) 1928 cache->saved_regs[regno] = 1929 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno); 1930 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++) 1931 cache->saved_regs[regno] = 1932 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno); 1933 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++) 1934 cache->saved_regs[regno] = 1935 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno); 1936 } 1937} 1938 1939static struct ia64_frame_cache * 1940ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) 1941{ 1942 struct ia64_frame_cache *cache; 1943 CORE_ADDR addr; 1944 char buf[8]; 1945 int i; 1946 1947 if (*this_cache) 1948 return *this_cache; 1949 1950 cache = ia64_alloc_frame_cache (); 1951 1952 frame_unwind_register (next_frame, sp_regnum, buf); 1953 /* Note that frame size is hard-coded below. We cannot calculate it 1954 via prologue examination. */ 1955 cache->base = extract_unsigned_integer (buf, 8) + 16; 1956 1957 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 1958 cache->bsp = extract_unsigned_integer (buf, 8); 1959 1960 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf); 1961 cache->cfm = extract_unsigned_integer (buf, 8); 1962 cache->sof = cache->cfm & 0x7f; 1963 1964 ia64_sigtramp_frame_init_saved_regs (cache); 1965 1966 *this_cache = cache; 1967 return cache; 1968} 1969 1970static void 1971ia64_sigtramp_frame_this_id (struct frame_info *next_frame, 1972 void **this_cache, struct frame_id *this_id) 1973{ 1974 struct ia64_frame_cache *cache = 1975 ia64_sigtramp_frame_cache (next_frame, this_cache); 1976 1977 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp); 1978 if (gdbarch_debug >= 1) 1979 fprintf_unfiltered (gdb_stdlog, 1980 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n", 1981 paddr_nz (this_id->code_addr), 1982 paddr_nz (this_id->stack_addr), 1983 paddr_nz (cache->bsp), next_frame); 1984} 1985 1986static void 1987ia64_sigtramp_frame_prev_register (struct frame_info *next_frame, 1988 void **this_cache, 1989 int regnum, int *optimizedp, 1990 enum lval_type *lvalp, CORE_ADDR *addrp, 1991 int *realnump, void *valuep) 1992{ 1993 char dummy_valp[MAX_REGISTER_SIZE]; 1994 char buf[MAX_REGISTER_SIZE]; 1995 1996 struct ia64_frame_cache *cache = 1997 ia64_sigtramp_frame_cache (next_frame, this_cache); 1998 1999 gdb_assert (regnum >= 0); 2000 2001 if (!target_has_registers) 2002 error ("No registers."); 2003 2004 *optimizedp = 0; 2005 *addrp = 0; 2006 *lvalp = not_lval; 2007 *realnump = -1; 2008 2009 /* Rather than check each time if valuep is non-null, supply a dummy buffer 2010 when valuep is not supplied. */ 2011 if (!valuep) 2012 valuep = dummy_valp; 2013 2014 memset (valuep, 0, register_size (current_gdbarch, regnum)); 2015 2016 if (regnum == IA64_IP_REGNUM) 2017 { 2018 CORE_ADDR pc = 0; 2019 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM]; 2020 2021 if (addr != 0) 2022 { 2023 *lvalp = lval_memory; 2024 *addrp = addr; 2025 ia64_read_reg (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM)); 2026 pc = extract_unsigned_integer (buf, 8); 2027 } 2028 pc &= ~0xf; 2029 store_unsigned_integer (valuep, 8, pc); 2030 } 2031 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) || 2032 (regnum >= V32_REGNUM && regnum <= V127_REGNUM)) 2033 { 2034 CORE_ADDR addr = 0; 2035 if (regnum >= V32_REGNUM) 2036 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM); 2037 addr = cache->saved_regs[regnum]; 2038 if (addr != 0) 2039 { 2040 *lvalp = lval_memory; 2041 *addrp = addr; 2042 ia64_read_reg (addr, valuep, register_size (current_gdbarch, regnum)); 2043 } 2044 } 2045 else 2046 { 2047 /* All other registers not listed above. */ 2048 CORE_ADDR addr = cache->saved_regs[regnum]; 2049 if (addr != 0) 2050 { 2051 *lvalp = lval_memory; 2052 *addrp = addr; 2053 ia64_read_reg (addr, valuep, register_size (current_gdbarch, regnum)); 2054 } 2055 } 2056 2057 if (gdbarch_debug >= 1) 2058 fprintf_unfiltered (gdb_stdlog, 2059 "sigtramp prev register <%s> is 0x%s\n", 2060 (((unsigned) regnum <= IA64_NAT127_REGNUM) 2061 ? ia64_register_names[regnum] : "r??"), 2062 paddr_nz (extract_unsigned_integer (valuep, 8))); 2063} 2064 2065static const struct frame_unwind ia64_sigtramp_frame_unwind = 2066{ 2067 SIGTRAMP_FRAME, 2068 ia64_sigtramp_frame_this_id, 2069 ia64_sigtramp_frame_prev_register 2070}; 2071 2072static const struct frame_unwind * 2073ia64_sigtramp_frame_sniffer (struct frame_info *next_frame) 2074{ 2075 char *name; 2076 CORE_ADDR pc = frame_pc_unwind (next_frame); 2077 2078 find_pc_partial_function (pc, &name, NULL, NULL); 2079 if (PC_IN_SIGTRAMP (pc, name)) 2080 return &ia64_sigtramp_frame_unwind; 2081 2082 return NULL; 2083} 2084 2085 2086static CORE_ADDR 2087ia64_frame_base_address (struct frame_info *next_frame, void **this_cache) 2088{ 2089 struct ia64_frame_cache *cache = 2090 ia64_frame_cache (next_frame, this_cache); 2091 2092 return cache->base; 2093} 2094 2095static const struct frame_base ia64_frame_base = 2096{ 2097 &ia64_frame_unwind, 2098 ia64_frame_base_address, 2099 ia64_frame_base_address, 2100 ia64_frame_base_address 2101}; 2102 2103#ifdef HAVE_LIBUNWIND_IA64_H 2104 2105struct ia64_unwind_table_entry 2106 { 2107 unw_word_t start_offset; 2108 unw_word_t end_offset; 2109 unw_word_t info_offset; 2110 }; 2111 2112static __inline__ uint64_t 2113ia64_rse_slot_num (uint64_t addr) 2114{ 2115 return (addr >> 3) & 0x3f; 2116} 2117 2118/* Skip over a designated number of registers in the backing 2119 store, remembering every 64th position is for NAT. */ 2120static __inline__ uint64_t 2121ia64_rse_skip_regs (uint64_t addr, long num_regs) 2122{ 2123 long delta = ia64_rse_slot_num(addr) + num_regs; 2124 2125 if (num_regs < 0) 2126 delta -= 0x3e; 2127 return addr + ((num_regs + delta/0x3f) << 3); 2128} 2129 2130/* Gdb libunwind-frame callback function to convert from an ia64 gdb register 2131 number to a libunwind register number. */ 2132static int 2133ia64_gdb2uw_regnum (int regnum) 2134{ 2135 if (regnum == sp_regnum) 2136 return UNW_IA64_SP; 2137 else if (regnum == IA64_BSP_REGNUM) 2138 return UNW_IA64_BSP; 2139 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128) 2140 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM); 2141 else if ((unsigned) (regnum - V32_REGNUM) < 95) 2142 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM); 2143 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128) 2144 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM); 2145 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64) 2146 return -1; 2147 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8) 2148 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM); 2149 else if (regnum == IA64_PR_REGNUM) 2150 return UNW_IA64_PR; 2151 else if (regnum == IA64_IP_REGNUM) 2152 return UNW_REG_IP; 2153 else if (regnum == IA64_CFM_REGNUM) 2154 return UNW_IA64_CFM; 2155 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128) 2156 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM); 2157 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128) 2158 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM); 2159 else 2160 return -1; 2161} 2162 2163/* Gdb libunwind-frame callback function to convert from a libunwind register 2164 number to a ia64 gdb register number. */ 2165static int 2166ia64_uw2gdb_regnum (int uw_regnum) 2167{ 2168 if (uw_regnum == UNW_IA64_SP) 2169 return sp_regnum; 2170 else if (uw_regnum == UNW_IA64_BSP) 2171 return IA64_BSP_REGNUM; 2172 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32) 2173 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR); 2174 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128) 2175 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32)); 2176 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128) 2177 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR); 2178 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8) 2179 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR); 2180 else if (uw_regnum == UNW_IA64_PR) 2181 return IA64_PR_REGNUM; 2182 else if (uw_regnum == UNW_REG_IP) 2183 return IA64_IP_REGNUM; 2184 else if (uw_regnum == UNW_IA64_CFM) 2185 return IA64_CFM_REGNUM; 2186 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128) 2187 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR); 2188 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128) 2189 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT); 2190 else 2191 return -1; 2192} 2193 2194/* Gdb libunwind-frame callback function to reveal if register is a float 2195 register or not. */ 2196static int 2197ia64_is_fpreg (int uw_regnum) 2198{ 2199 return unw_is_fpreg (uw_regnum); 2200} 2201 2202/* Libunwind callback accessor function for general registers. */ 2203static int 2204ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val, 2205 int write, void *arg) 2206{ 2207 int regnum = ia64_uw2gdb_regnum (uw_regnum); 2208 unw_word_t bsp, sof, sol, cfm, psr, ip; 2209 struct frame_info *next_frame = arg; 2210 long new_sof, old_sof; 2211 char buf[MAX_REGISTER_SIZE]; 2212 2213 if (write) 2214 { 2215 if (regnum < 0) 2216 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */ 2217 return 0; 2218 2219 switch (uw_regnum) 2220 { 2221 case UNW_REG_IP: 2222 ia64_write_pc (*val, inferior_ptid); 2223 break; 2224 2225 case UNW_IA64_AR_BSPSTORE: 2226 write_register (IA64_BSP_REGNUM, *val); 2227 break; 2228 2229 case UNW_IA64_AR_BSP: 2230 case UNW_IA64_BSP: 2231 /* Account for the fact that ptrace() expects bsp to point 2232 after the current register frame. */ 2233 cfm = read_register (IA64_CFM_REGNUM); 2234 sof = (cfm & 0x7f); 2235 bsp = ia64_rse_skip_regs (*val, sof); 2236 write_register (IA64_BSP_REGNUM, bsp); 2237 break; 2238 2239 case UNW_IA64_CFM: 2240 /* If we change CFM, we need to adjust ptrace's notion of 2241 bsp accordingly, so that the real bsp remains 2242 unchanged. */ 2243 bsp = read_register (IA64_BSP_REGNUM); 2244 cfm = read_register (IA64_CFM_REGNUM); 2245 old_sof = (cfm & 0x7f); 2246 new_sof = (*val & 0x7f); 2247 if (old_sof != new_sof) 2248 { 2249 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof); 2250 write_register (IA64_BSP_REGNUM, bsp); 2251 } 2252 write_register (IA64_CFM_REGNUM, *val); 2253 break; 2254 2255 default: 2256 write_register (regnum, *val); 2257 break; 2258 } 2259 if (gdbarch_debug >= 1) 2260 fprintf_unfiltered (gdb_stdlog, 2261 " access_reg: to cache: %4s=0x%s\n", 2262 (((unsigned) regnum <= IA64_NAT127_REGNUM) 2263 ? ia64_register_names[regnum] : "r??"), 2264 paddr_nz (*val)); 2265 } 2266 else 2267 { 2268 switch (uw_regnum) 2269 { 2270 case UNW_REG_IP: 2271 /* Libunwind expects to see the pc value which means the slot number 2272 from the psr must be merged with the ip word address. */ 2273 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf); 2274 ip = extract_unsigned_integer (buf, 8); 2275 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf); 2276 psr = extract_unsigned_integer (buf, 8); 2277 *val = ip | ((psr >> 41) & 0x3); 2278 break; 2279 2280 case UNW_IA64_AR_BSP: 2281 /* Libunwind expects to see the beginning of the current register 2282 frame so we must account for the fact that ptrace() will return a value 2283 for bsp that points *after* the current register frame. */ 2284 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 2285 bsp = extract_unsigned_integer (buf, 8); 2286 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf); 2287 cfm = extract_unsigned_integer (buf, 8); 2288 sof = (cfm & 0x7f); 2289 *val = ia64_rse_skip_regs (bsp, -sof); 2290 break; 2291 2292 case UNW_IA64_AR_BSPSTORE: 2293 /* Libunwind wants bspstore to be after the current register frame. 2294 This is what ptrace() and gdb treats as the regular bsp value. */ 2295 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 2296 *val = extract_unsigned_integer (buf, 8); 2297 break; 2298 2299 default: 2300 /* For all other registers, just unwind the value directly. */ 2301 frame_unwind_register (next_frame, regnum, buf); 2302 *val = extract_unsigned_integer (buf, 8); 2303 break; 2304 } 2305 2306 if (gdbarch_debug >= 1) 2307 fprintf_unfiltered (gdb_stdlog, 2308 " access_reg: from cache: %4s=0x%s\n", 2309 (((unsigned) regnum <= IA64_NAT127_REGNUM) 2310 ? ia64_register_names[regnum] : "r??"), 2311 paddr_nz (*val)); 2312 } 2313 return 0; 2314} 2315 2316/* Libunwind callback accessor function for floating-point registers. */ 2317static int 2318ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val, 2319 int write, void *arg) 2320{ 2321 int regnum = ia64_uw2gdb_regnum (uw_regnum); 2322 2323 if (write) 2324 regcache_cooked_write (current_regcache, regnum, (char *) val); 2325 else 2326 regcache_cooked_read (current_regcache, regnum, (char *) val); 2327 return 0; 2328} 2329 2330/* Libunwind callback accessor function for accessing memory. */ 2331static int 2332ia64_access_mem (unw_addr_space_t as, 2333 unw_word_t addr, unw_word_t *val, 2334 int write, void *arg) 2335{ 2336 /* XXX do we need to normalize byte-order here? */ 2337 if (write) 2338 return target_write_memory (addr, (char *) val, sizeof (unw_word_t)); 2339 else 2340 return target_read_memory (addr, (char *) val, sizeof (unw_word_t)); 2341} 2342 2343/* Call low-level function to access the kernel unwind table. */ 2344static int 2345getunwind_table (void *buf, size_t len) 2346{ 2347 LONGEST x; 2348 x = target_read_partial (¤t_target, TARGET_OBJECT_UNWIND_TABLE, NULL, 2349 buf, 0, len); 2350 2351 return (int)x; 2352} 2353 2354/* Get the kernel unwind table. */ 2355static int 2356get_kernel_table (unw_word_t ip, unw_dyn_info_t *di) 2357{ 2358 size_t size; 2359 struct ia64_table_entry 2360 { 2361 uint64_t start_offset; 2362 uint64_t end_offset; 2363 uint64_t info_offset; 2364 }; 2365 static struct ia64_table_entry *ktab = NULL, *etab; 2366 2367 if (!ktab) 2368 { 2369 size = getunwind_table (NULL, 0); 2370 if ((int)size < 0) 2371 return -UNW_ENOINFO; 2372 ktab = xmalloc (size); 2373 getunwind_table (ktab, size); 2374 2375 /* Determine length of kernel's unwind table and relocate 2376 it's entries. */ 2377 for (etab = ktab; etab->start_offset; ++etab) 2378 etab->info_offset += (uint64_t) ktab; 2379 } 2380 2381 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset) 2382 return -UNW_ENOINFO; 2383 2384 di->format = UNW_INFO_FORMAT_TABLE; 2385 di->gp = 0; 2386 di->start_ip = ktab[0].start_offset; 2387 di->end_ip = etab[-1].end_offset; 2388 di->u.ti.name_ptr = (unw_word_t) "<kernel>"; 2389 di->u.ti.segbase = 0; 2390 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t); 2391 di->u.ti.table_data = (unw_word_t *) ktab; 2392 2393 if (gdbarch_debug >= 1) 2394 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': " 2395 "segbase=0x%s, length=%s, gp=0x%s\n", 2396 (char *) di->u.ti.name_ptr, 2397 paddr_nz (di->u.ti.segbase), 2398 paddr_u (di->u.ti.table_len), 2399 paddr_nz (di->gp)); 2400 return 0; 2401} 2402 2403/* Find the unwind table entry for a specified address. */ 2404static int 2405ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip, 2406 unw_dyn_info_t *dip, void **buf) 2407{ 2408 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL; 2409 Elf_Internal_Ehdr *ehdr; 2410 unw_word_t segbase = 0; 2411 CORE_ADDR load_base; 2412 bfd *bfd; 2413 int i; 2414 2415 bfd = objfile->obfd; 2416 2417 ehdr = elf_tdata (bfd)->elf_header; 2418 phdr = elf_tdata (bfd)->phdr; 2419 2420 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile)); 2421 2422 for (i = 0; i < ehdr->e_phnum; ++i) 2423 { 2424 switch (phdr[i].p_type) 2425 { 2426 case PT_LOAD: 2427 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr) 2428 < phdr[i].p_memsz) 2429 p_text = phdr + i; 2430 break; 2431 2432 case PT_IA_64_UNWIND: 2433 p_unwind = phdr + i; 2434 break; 2435 2436 default: 2437 break; 2438 } 2439 } 2440 2441 if (!p_text || !p_unwind 2442 /* Verify that the segment that contains the IP also contains 2443 the static unwind table. If not, we are dealing with 2444 runtime-generated code, for which we have no info here. */ 2445 || (p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz) 2446 return -UNW_ENOINFO; 2447 2448 segbase = p_text->p_vaddr + load_base; 2449 2450 dip->start_ip = segbase; 2451 dip->end_ip = dip->start_ip + p_text->p_memsz; 2452 dip->gp = FIND_GLOBAL_POINTER (ip); 2453 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE; 2454 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd); 2455 dip->u.rti.segbase = segbase; 2456 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t); 2457 dip->u.rti.table_data = p_unwind->p_vaddr + load_base; 2458 2459 return 0; 2460} 2461 2462/* Libunwind callback accessor function to acquire procedure unwind-info. */ 2463static int 2464ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi, 2465 int need_unwind_info, void *arg) 2466{ 2467 struct obj_section *sec = find_pc_section (ip); 2468 unw_dyn_info_t di; 2469 int ret; 2470 void *buf = NULL; 2471 2472 if (!sec) 2473 { 2474 /* XXX This only works if the host and the target architecture are 2475 both ia64 and if the have (more or less) the same kernel 2476 version. */ 2477 if (get_kernel_table (ip, &di) < 0) 2478 return -UNW_ENOINFO; 2479 2480 if (gdbarch_debug >= 1) 2481 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> " 2482 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s," 2483 "length=%s,data=0x%s)\n", 2484 paddr_nz (ip), (char *)di.u.ti.name_ptr, 2485 paddr_nz (di.u.ti.segbase), 2486 paddr_nz (di.start_ip), paddr_nz (di.end_ip), 2487 paddr_nz (di.gp), 2488 paddr_u (di.u.ti.table_len), 2489 paddr_nz ((CORE_ADDR)di.u.ti.table_data)); 2490 } 2491 else 2492 { 2493 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf); 2494 if (ret < 0) 2495 return ret; 2496 2497 if (gdbarch_debug >= 1) 2498 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> " 2499 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s," 2500 "length=%s,data=0x%s)\n", 2501 paddr_nz (ip), (char *)di.u.rti.name_ptr, 2502 paddr_nz (di.u.rti.segbase), 2503 paddr_nz (di.start_ip), paddr_nz (di.end_ip), 2504 paddr_nz (di.gp), 2505 paddr_u (di.u.rti.table_len), 2506 paddr_nz (di.u.rti.table_data)); 2507 } 2508 2509 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info, 2510 arg); 2511 2512 /* We no longer need the dyn info storage so free it. */ 2513 xfree (buf); 2514 2515 return ret; 2516} 2517 2518/* Libunwind callback accessor function for cleanup. */ 2519static void 2520ia64_put_unwind_info (unw_addr_space_t as, 2521 unw_proc_info_t *pip, void *arg) 2522{ 2523 /* Nothing required for now. */ 2524} 2525 2526/* Libunwind callback accessor function to get head of the dynamic 2527 unwind-info registration list. */ 2528static int 2529ia64_get_dyn_info_list (unw_addr_space_t as, 2530 unw_word_t *dilap, void *arg) 2531{ 2532 struct obj_section *text_sec; 2533 struct objfile *objfile; 2534 unw_word_t ip, addr; 2535 unw_dyn_info_t di; 2536 int ret; 2537 2538 if (!libunwind_is_initialized ()) 2539 return -UNW_ENOINFO; 2540 2541 for (objfile = object_files; objfile; objfile = objfile->next) 2542 { 2543 void *buf = NULL; 2544 2545 text_sec = objfile->sections + SECT_OFF_TEXT (objfile); 2546 ip = text_sec->addr; 2547 ret = ia64_find_unwind_table (objfile, ip, &di, &buf); 2548 if (ret >= 0) 2549 { 2550 addr = libunwind_find_dyn_list (as, &di, arg); 2551 /* We no longer need the dyn info storage so free it. */ 2552 xfree (buf); 2553 2554 if (addr) 2555 { 2556 if (gdbarch_debug >= 1) 2557 fprintf_unfiltered (gdb_stdlog, 2558 "dynamic unwind table in objfile %s " 2559 "at 0x%s (gp=0x%s)\n", 2560 bfd_get_filename (objfile->obfd), 2561 paddr_nz (addr), paddr_nz (di.gp)); 2562 *dilap = addr; 2563 return 0; 2564 } 2565 } 2566 } 2567 return -UNW_ENOINFO; 2568} 2569 2570 2571/* Frame interface functions for libunwind. */ 2572 2573static void 2574ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache, 2575 struct frame_id *this_id) 2576{ 2577 char buf[8]; 2578 CORE_ADDR bsp; 2579 struct frame_id id; 2580 2581 libunwind_frame_this_id (next_frame, this_cache, &id); 2582 2583 /* We must add the bsp as the special address for frame comparison purposes. */ 2584 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 2585 bsp = extract_unsigned_integer (buf, 8); 2586 2587 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp); 2588 2589 if (gdbarch_debug >= 1) 2590 fprintf_unfiltered (gdb_stdlog, 2591 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n", 2592 paddr_nz (id.code_addr), paddr_nz (id.stack_addr), 2593 paddr_nz (bsp), next_frame); 2594} 2595 2596static void 2597ia64_libunwind_frame_prev_register (struct frame_info *next_frame, 2598 void **this_cache, 2599 int regnum, int *optimizedp, 2600 enum lval_type *lvalp, CORE_ADDR *addrp, 2601 int *realnump, void *valuep) 2602{ 2603 int reg = regnum; 2604 2605 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) 2606 reg = IA64_PR_REGNUM; 2607 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) 2608 reg = IA64_UNAT_REGNUM; 2609 2610 /* Let libunwind do most of the work. */ 2611 libunwind_frame_prev_register (next_frame, this_cache, reg, 2612 optimizedp, lvalp, addrp, realnump, valuep); 2613 2614 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM) 2615 { 2616 ULONGEST prN_val; 2617 2618 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM) 2619 { 2620 int rrb_pr = 0; 2621 ULONGEST cfm; 2622 unsigned char buf[MAX_REGISTER_SIZE]; 2623 2624 /* Fetch predicate register rename base from current frame 2625 marker for this frame. */ 2626 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf); 2627 cfm = extract_unsigned_integer (buf, 8); 2628 rrb_pr = (cfm >> 32) & 0x3f; 2629 2630 /* Adjust the register number to account for register rotation. */ 2631 regnum = VP16_REGNUM 2632 + ((regnum - VP16_REGNUM) + rrb_pr) % 48; 2633 } 2634 prN_val = extract_bit_field ((unsigned char *) valuep, 2635 regnum - VP0_REGNUM, 1); 2636 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val); 2637 } 2638 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM) 2639 { 2640 ULONGEST unatN_val; 2641 2642 unatN_val = extract_bit_field ((unsigned char *) valuep, 2643 regnum - IA64_NAT0_REGNUM, 1); 2644 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), 2645 unatN_val); 2646 } 2647 else if (regnum == IA64_BSP_REGNUM) 2648 { 2649 char cfm_valuep[MAX_REGISTER_SIZE]; 2650 int cfm_optim; 2651 int cfm_realnum; 2652 enum lval_type cfm_lval; 2653 CORE_ADDR cfm_addr; 2654 CORE_ADDR bsp, prev_cfm, prev_bsp; 2655 2656 /* We want to calculate the previous bsp as the end of the previous register stack frame. 2657 This corresponds to what the hardware bsp register will be if we pop the frame 2658 back which is why we might have been called. We know that libunwind will pass us back 2659 the beginning of the current frame so we should just add sof to it. */ 2660 prev_bsp = extract_unsigned_integer (valuep, 8); 2661 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM, 2662 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep); 2663 prev_cfm = extract_unsigned_integer (cfm_valuep, 8); 2664 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f)); 2665 2666 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), 2667 prev_bsp); 2668 } 2669 2670 if (gdbarch_debug >= 1) 2671 fprintf_unfiltered (gdb_stdlog, 2672 "libunwind prev register <%s> is 0x%s\n", 2673 (((unsigned) regnum <= IA64_NAT127_REGNUM) 2674 ? ia64_register_names[regnum] : "r??"), 2675 paddr_nz (extract_unsigned_integer (valuep, 8))); 2676} 2677 2678static const struct frame_unwind ia64_libunwind_frame_unwind = 2679{ 2680 NORMAL_FRAME, 2681 ia64_libunwind_frame_this_id, 2682 ia64_libunwind_frame_prev_register 2683}; 2684 2685static const struct frame_unwind * 2686ia64_libunwind_frame_sniffer (struct frame_info *next_frame) 2687{ 2688 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame)) 2689 return &ia64_libunwind_frame_unwind; 2690 2691 return NULL; 2692} 2693 2694/* Set of libunwind callback acccessor functions. */ 2695static unw_accessors_t ia64_unw_accessors = 2696{ 2697 ia64_find_proc_info_x, 2698 ia64_put_unwind_info, 2699 ia64_get_dyn_info_list, 2700 ia64_access_mem, 2701 ia64_access_reg, 2702 ia64_access_fpreg, 2703 /* resume */ 2704 /* get_proc_name */ 2705}; 2706 2707/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */ 2708static struct libunwind_descr ia64_libunwind_descr = 2709{ 2710 ia64_gdb2uw_regnum, 2711 ia64_uw2gdb_regnum, 2712 ia64_is_fpreg, 2713 &ia64_unw_accessors, 2714}; 2715 2716#endif /* HAVE_LIBUNWIND_IA64_H */ 2717 2718/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of 2719 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE 2720 is the type (which is known to be struct, union or array). */ 2721int 2722ia64_use_struct_convention (int gcc_p, struct type *type) 2723{ 2724 struct type *float_elt_type; 2725 2726 /* HFAs are structures (or arrays) consisting entirely of floating 2727 point values of the same length. Up to 8 of these are returned 2728 in registers. Don't use the struct convention when this is the 2729 case. */ 2730 float_elt_type = is_float_or_hfa_type (type); 2731 if (float_elt_type != NULL 2732 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8) 2733 return 0; 2734 2735 /* Other structs of length 32 or less are returned in r8-r11. 2736 Don't use the struct convention for those either. */ 2737 return TYPE_LENGTH (type) > 32; 2738} 2739 2740void 2741ia64_extract_return_value (struct type *type, struct regcache *regcache, void *valbuf) 2742{ 2743 struct type *float_elt_type; 2744 2745 float_elt_type = is_float_or_hfa_type (type); 2746 if (float_elt_type != NULL) 2747 { 2748 char from[MAX_REGISTER_SIZE]; 2749 int offset = 0; 2750 int regnum = IA64_FR8_REGNUM; 2751 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type); 2752 2753 while (n-- > 0) 2754 { 2755 regcache_cooked_read (regcache, regnum, from); 2756 convert_typed_floating (from, builtin_type_ia64_ext, 2757 (char *)valbuf + offset, float_elt_type); 2758 offset += TYPE_LENGTH (float_elt_type); 2759 regnum++; 2760 } 2761 } 2762 else 2763 { 2764 ULONGEST val; 2765 int offset = 0; 2766 int regnum = IA64_GR8_REGNUM; 2767 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM)); 2768 int n = TYPE_LENGTH (type) / reglen; 2769 int m = TYPE_LENGTH (type) % reglen; 2770 2771 while (n-- > 0) 2772 { 2773 ULONGEST val; 2774 regcache_cooked_read_unsigned (regcache, regnum, &val); 2775 memcpy ((char *)valbuf + offset, &val, reglen); 2776 offset += reglen; 2777 regnum++; 2778 } 2779 2780 if (m) 2781 { 2782 regcache_cooked_read_unsigned (regcache, regnum, &val); 2783 memcpy ((char *)valbuf + offset, &val, m); 2784 } 2785 } 2786} 2787 2788CORE_ADDR 2789ia64_extract_struct_value_address (struct regcache *regcache) 2790{ 2791 error ("ia64_extract_struct_value_address called and cannot get struct value address"); 2792 return 0; 2793} 2794 2795 2796static int 2797is_float_or_hfa_type_recurse (struct type *t, struct type **etp) 2798{ 2799 switch (TYPE_CODE (t)) 2800 { 2801 case TYPE_CODE_FLT: 2802 if (*etp) 2803 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t); 2804 else 2805 { 2806 *etp = t; 2807 return 1; 2808 } 2809 break; 2810 case TYPE_CODE_ARRAY: 2811 return 2812 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)), 2813 etp); 2814 break; 2815 case TYPE_CODE_STRUCT: 2816 { 2817 int i; 2818 2819 for (i = 0; i < TYPE_NFIELDS (t); i++) 2820 if (!is_float_or_hfa_type_recurse 2821 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp)) 2822 return 0; 2823 return 1; 2824 } 2825 break; 2826 default: 2827 return 0; 2828 break; 2829 } 2830} 2831 2832/* Determine if the given type is one of the floating point types or 2833 and HFA (which is a struct, array, or combination thereof whose 2834 bottom-most elements are all of the same floating point type). */ 2835 2836static struct type * 2837is_float_or_hfa_type (struct type *t) 2838{ 2839 struct type *et = 0; 2840 2841 return is_float_or_hfa_type_recurse (t, &et) ? et : 0; 2842} 2843 2844 2845/* Return 1 if the alignment of T is such that the next even slot 2846 should be used. Return 0, if the next available slot should 2847 be used. (See section 8.5.1 of the IA-64 Software Conventions 2848 and Runtime manual). */ 2849 2850static int 2851slot_alignment_is_next_even (struct type *t) 2852{ 2853 switch (TYPE_CODE (t)) 2854 { 2855 case TYPE_CODE_INT: 2856 case TYPE_CODE_FLT: 2857 if (TYPE_LENGTH (t) > 8) 2858 return 1; 2859 else 2860 return 0; 2861 case TYPE_CODE_ARRAY: 2862 return 2863 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t))); 2864 case TYPE_CODE_STRUCT: 2865 { 2866 int i; 2867 2868 for (i = 0; i < TYPE_NFIELDS (t); i++) 2869 if (slot_alignment_is_next_even 2870 (check_typedef (TYPE_FIELD_TYPE (t, i)))) 2871 return 1; 2872 return 0; 2873 } 2874 default: 2875 return 0; 2876 } 2877} 2878 2879/* Attempt to find (and return) the global pointer for the given 2880 function. 2881 2882 This is a rather nasty bit of code searchs for the .dynamic section 2883 in the objfile corresponding to the pc of the function we're trying 2884 to call. Once it finds the addresses at which the .dynamic section 2885 lives in the child process, it scans the Elf64_Dyn entries for a 2886 DT_PLTGOT tag. If it finds one of these, the corresponding 2887 d_un.d_ptr value is the global pointer. */ 2888 2889CORE_ADDR 2890ia64_generic_find_global_pointer (CORE_ADDR faddr) 2891{ 2892 struct obj_section *faddr_sect; 2893 2894 faddr_sect = find_pc_section (faddr); 2895 if (faddr_sect != NULL) 2896 { 2897 struct obj_section *osect; 2898 2899 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect) 2900 { 2901 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0) 2902 break; 2903 } 2904 2905 if (osect < faddr_sect->objfile->sections_end) 2906 { 2907 CORE_ADDR addr; 2908 2909 addr = osect->addr; 2910 while (addr < osect->endaddr) 2911 { 2912 int status; 2913 LONGEST tag; 2914 char buf[8]; 2915 2916 status = target_read_memory (addr, buf, sizeof (buf)); 2917 if (status != 0) 2918 break; 2919 tag = extract_signed_integer (buf, sizeof (buf)); 2920 2921 if (tag == DT_PLTGOT) 2922 { 2923 CORE_ADDR global_pointer; 2924 2925 status = target_read_memory (addr + 8, buf, sizeof (buf)); 2926 if (status != 0) 2927 break; 2928 global_pointer = extract_unsigned_integer (buf, sizeof (buf)); 2929 2930 /* The payoff... */ 2931 return global_pointer; 2932 } 2933 2934 if (tag == DT_NULL) 2935 break; 2936 2937 addr += 16; 2938 } 2939 } 2940 } 2941 return 0; 2942} 2943 2944/* Given a function's address, attempt to find (and return) the 2945 corresponding (canonical) function descriptor. Return 0 if 2946 not found. */ 2947static CORE_ADDR 2948find_extant_func_descr (CORE_ADDR faddr) 2949{ 2950 struct obj_section *faddr_sect; 2951 2952 /* Return early if faddr is already a function descriptor. */ 2953 faddr_sect = find_pc_section (faddr); 2954 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0) 2955 return faddr; 2956 2957 if (faddr_sect != NULL) 2958 { 2959 struct obj_section *osect; 2960 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect) 2961 { 2962 if (strcmp (osect->the_bfd_section->name, ".opd") == 0) 2963 break; 2964 } 2965 2966 if (osect < faddr_sect->objfile->sections_end) 2967 { 2968 CORE_ADDR addr; 2969 2970 addr = osect->addr; 2971 while (addr < osect->endaddr) 2972 { 2973 int status; 2974 LONGEST faddr2; 2975 char buf[8]; 2976 2977 status = target_read_memory (addr, buf, sizeof (buf)); 2978 if (status != 0) 2979 break; 2980 faddr2 = extract_signed_integer (buf, sizeof (buf)); 2981 2982 if (faddr == faddr2) 2983 return addr; 2984 2985 addr += 16; 2986 } 2987 } 2988 } 2989 return 0; 2990} 2991 2992/* Attempt to find a function descriptor corresponding to the 2993 given address. If none is found, construct one on the 2994 stack using the address at fdaptr. */ 2995 2996static CORE_ADDR 2997find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr) 2998{ 2999 CORE_ADDR fdesc; 3000 3001 fdesc = find_extant_func_descr (faddr); 3002 3003 if (fdesc == 0) 3004 { 3005 CORE_ADDR global_pointer; 3006 char buf[16]; 3007 3008 fdesc = *fdaptr; 3009 *fdaptr += 16; 3010 3011 global_pointer = FIND_GLOBAL_POINTER (faddr); 3012 3013 if (global_pointer == 0) 3014 global_pointer = read_register (IA64_GR1_REGNUM); 3015 3016 store_unsigned_integer (buf, 8, faddr); 3017 store_unsigned_integer (buf + 8, 8, global_pointer); 3018 3019 write_memory (fdesc, buf, 16); 3020 } 3021 3022 return fdesc; 3023} 3024 3025/* Use the following routine when printing out function pointers 3026 so the user can see the function address rather than just the 3027 function descriptor. */ 3028static CORE_ADDR 3029ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, 3030 struct target_ops *targ) 3031{ 3032 struct obj_section *s; 3033 3034 s = find_pc_section (addr); 3035 3036 /* check if ADDR points to a function descriptor. */ 3037 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0) 3038 return read_memory_unsigned_integer (addr, 8); 3039 3040 return addr; 3041} 3042 3043static CORE_ADDR 3044ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 3045{ 3046 return sp & ~0xfLL; 3047} 3048 3049static CORE_ADDR 3050ia64_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, 3051 struct regcache *regcache, CORE_ADDR bp_addr, 3052 int nargs, struct value **args, CORE_ADDR sp, 3053 int struct_return, CORE_ADDR struct_addr) 3054{ 3055 int argno; 3056 struct value *arg; 3057 struct type *type; 3058 int len, argoffset; 3059 int nslots, rseslots, memslots, slotnum, nfuncargs; 3060 int floatreg; 3061 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer; 3062 3063 nslots = 0; 3064 nfuncargs = 0; 3065 /* Count the number of slots needed for the arguments. */ 3066 for (argno = 0; argno < nargs; argno++) 3067 { 3068 arg = args[argno]; 3069 type = check_typedef (VALUE_TYPE (arg)); 3070 len = TYPE_LENGTH (type); 3071 3072 if ((nslots & 1) && slot_alignment_is_next_even (type)) 3073 nslots++; 3074 3075 if (TYPE_CODE (type) == TYPE_CODE_FUNC) 3076 nfuncargs++; 3077 3078 nslots += (len + 7) / 8; 3079 } 3080 3081 /* Divvy up the slots between the RSE and the memory stack. */ 3082 rseslots = (nslots > 8) ? 8 : nslots; 3083 memslots = nslots - rseslots; 3084 3085 /* Allocate a new RSE frame. */ 3086 cfm = read_register (IA64_CFM_REGNUM); 3087 3088 bsp = read_register (IA64_BSP_REGNUM); 3089 new_bsp = rse_address_add (bsp, rseslots); 3090 write_register (IA64_BSP_REGNUM, new_bsp); 3091 3092 pfs = read_register (IA64_PFS_REGNUM); 3093 pfs &= 0xc000000000000000LL; 3094 pfs |= (cfm & 0xffffffffffffLL); 3095 write_register (IA64_PFS_REGNUM, pfs); 3096 3097 cfm &= 0xc000000000000000LL; 3098 cfm |= rseslots; 3099 write_register (IA64_CFM_REGNUM, cfm); 3100 3101 /* We will attempt to find function descriptors in the .opd segment, 3102 but if we can't we'll construct them ourselves. That being the 3103 case, we'll need to reserve space on the stack for them. */ 3104 funcdescaddr = sp - nfuncargs * 16; 3105 funcdescaddr &= ~0xfLL; 3106 3107 /* Adjust the stack pointer to it's new value. The calling conventions 3108 require us to have 16 bytes of scratch, plus whatever space is 3109 necessary for the memory slots and our function descriptors. */ 3110 sp = sp - 16 - (memslots + nfuncargs) * 8; 3111 sp &= ~0xfLL; /* Maintain 16 byte alignment. */ 3112 3113 /* Place the arguments where they belong. The arguments will be 3114 either placed in the RSE backing store or on the memory stack. 3115 In addition, floating point arguments or HFAs are placed in 3116 floating point registers. */ 3117 slotnum = 0; 3118 floatreg = IA64_FR8_REGNUM; 3119 for (argno = 0; argno < nargs; argno++) 3120 { 3121 struct type *float_elt_type; 3122 3123 arg = args[argno]; 3124 type = check_typedef (VALUE_TYPE (arg)); 3125 len = TYPE_LENGTH (type); 3126 3127 /* Special handling for function parameters. */ 3128 if (len == 8 3129 && TYPE_CODE (type) == TYPE_CODE_PTR 3130 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC) 3131 { 3132 char val_buf[8]; 3133 3134 store_unsigned_integer (val_buf, 8, 3135 find_func_descr (extract_unsigned_integer (VALUE_CONTENTS (arg), 8), 3136 &funcdescaddr)); 3137 if (slotnum < rseslots) 3138 write_memory (rse_address_add (bsp, slotnum), val_buf, 8); 3139 else 3140 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8); 3141 slotnum++; 3142 continue; 3143 } 3144 3145 /* Normal slots. */ 3146 3147 /* Skip odd slot if necessary... */ 3148 if ((slotnum & 1) && slot_alignment_is_next_even (type)) 3149 slotnum++; 3150 3151 argoffset = 0; 3152 while (len > 0) 3153 { 3154 char val_buf[8]; 3155 3156 memset (val_buf, 0, 8); 3157 memcpy (val_buf, VALUE_CONTENTS (arg) + argoffset, (len > 8) ? 8 : len); 3158 3159 if (slotnum < rseslots) 3160 write_memory (rse_address_add (bsp, slotnum), val_buf, 8); 3161 else 3162 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8); 3163 3164 argoffset += 8; 3165 len -= 8; 3166 slotnum++; 3167 } 3168 3169 /* Handle floating point types (including HFAs). */ 3170 float_elt_type = is_float_or_hfa_type (type); 3171 if (float_elt_type != NULL) 3172 { 3173 argoffset = 0; 3174 len = TYPE_LENGTH (type); 3175 while (len > 0 && floatreg < IA64_FR16_REGNUM) 3176 { 3177 char to[MAX_REGISTER_SIZE]; 3178 convert_typed_floating (VALUE_CONTENTS (arg) + argoffset, float_elt_type, 3179 to, builtin_type_ia64_ext); 3180 regcache_cooked_write (regcache, floatreg, (void *)to); 3181 floatreg++; 3182 argoffset += TYPE_LENGTH (float_elt_type); 3183 len -= TYPE_LENGTH (float_elt_type); 3184 } 3185 } 3186 } 3187 3188 /* Store the struct return value in r8 if necessary. */ 3189 if (struct_return) 3190 { 3191 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr); 3192 } 3193 3194 global_pointer = FIND_GLOBAL_POINTER (func_addr); 3195 3196 if (global_pointer != 0) 3197 write_register (IA64_GR1_REGNUM, global_pointer); 3198 3199 write_register (IA64_BR0_REGNUM, bp_addr); 3200 3201 write_register (sp_regnum, sp); 3202 3203 return sp; 3204} 3205 3206static struct frame_id 3207ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 3208{ 3209 char buf[8]; 3210 CORE_ADDR sp, bsp; 3211 3212 frame_unwind_register (next_frame, sp_regnum, buf); 3213 sp = extract_unsigned_integer (buf, 8); 3214 3215 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf); 3216 bsp = extract_unsigned_integer (buf, 8); 3217 3218 if (gdbarch_debug >= 1) 3219 fprintf_unfiltered (gdb_stdlog, 3220 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n", 3221 paddr_nz (frame_pc_unwind (next_frame)), 3222 paddr_nz (sp), paddr_nz (bsp)); 3223 3224 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp); 3225} 3226 3227static CORE_ADDR 3228ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 3229{ 3230 char buf[8]; 3231 CORE_ADDR ip, psr, pc; 3232 3233 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf); 3234 ip = extract_unsigned_integer (buf, 8); 3235 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf); 3236 psr = extract_unsigned_integer (buf, 8); 3237 3238 pc = (ip & ~0xf) | ((psr >> 41) & 3); 3239 return pc; 3240} 3241 3242static void 3243ia64_store_return_value (struct type *type, struct regcache *regcache, const void *valbuf) 3244{ 3245 if (TYPE_CODE (type) == TYPE_CODE_FLT) 3246 { 3247 char to[MAX_REGISTER_SIZE]; 3248 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext); 3249 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to); 3250 target_store_registers (IA64_FR8_REGNUM); 3251 } 3252 else 3253 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf); 3254} 3255 3256static void 3257ia64_remote_translate_xfer_address (struct gdbarch *gdbarch, 3258 struct regcache *regcache, 3259 CORE_ADDR memaddr, int nr_bytes, 3260 CORE_ADDR *targ_addr, int *targ_len) 3261{ 3262 *targ_addr = memaddr; 3263 *targ_len = nr_bytes; 3264} 3265 3266static int 3267ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info) 3268{ 3269 info->bytes_per_line = SLOT_MULTIPLIER; 3270 return print_insn_ia64 (memaddr, info); 3271} 3272 3273static struct gdbarch * 3274ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 3275{ 3276 struct gdbarch *gdbarch; 3277 struct gdbarch_tdep *tdep; 3278 3279 /* If there is already a candidate, use it. */ 3280 arches = gdbarch_list_lookup_by_info (arches, &info); 3281 if (arches != NULL) 3282 return arches->gdbarch; 3283 3284 tdep = xmalloc (sizeof (struct gdbarch_tdep)); 3285 gdbarch = gdbarch_alloc (&info, tdep); 3286 tdep->osabi = info.osabi; 3287 tdep->sigcontext_register_address = NULL; 3288 tdep->find_global_pointer = ia64_generic_find_global_pointer; 3289 3290 /* Define the ia64 floating-point format to gdb. */ 3291 builtin_type_ia64_ext = 3292 init_type (TYPE_CODE_FLT, 128 / 8, 3293 0, "builtin_type_ia64_ext", NULL); 3294 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext; 3295 3296 /* According to the ia64 specs, instructions that store long double 3297 floats in memory use a long-double format different than that 3298 used in the floating registers. The memory format matches the 3299 x86 extended float format which is 80 bits. An OS may choose to 3300 use this format (e.g. GNU/Linux) or choose to use a different 3301 format for storing long doubles (e.g. HPUX). In the latter case, 3302 the setting of the format may be moved/overridden in an 3303 OS-specific tdep file. */ 3304 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext); 3305 3306 set_gdbarch_short_bit (gdbarch, 16); 3307 set_gdbarch_int_bit (gdbarch, 32); 3308 set_gdbarch_long_bit (gdbarch, 64); 3309 set_gdbarch_long_long_bit (gdbarch, 64); 3310 set_gdbarch_float_bit (gdbarch, 32); 3311 set_gdbarch_double_bit (gdbarch, 64); 3312 set_gdbarch_long_double_bit (gdbarch, 128); 3313 set_gdbarch_ptr_bit (gdbarch, 64); 3314 3315 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS); 3316 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM); 3317 set_gdbarch_sp_regnum (gdbarch, sp_regnum); 3318 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM); 3319 3320 set_gdbarch_register_name (gdbarch, ia64_register_name); 3321 /* FIXME: Following interface should not be needed, however, without it recurse.exp 3322 gets a number of extra failures. */ 3323 set_gdbarch_deprecated_register_size (gdbarch, 8); 3324 set_gdbarch_register_type (gdbarch, ia64_register_type); 3325 3326 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read); 3327 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write); 3328 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum); 3329 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p); 3330 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p); 3331 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value); 3332 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register); 3333 3334 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue); 3335 3336 set_gdbarch_use_struct_convention (gdbarch, ia64_use_struct_convention); 3337 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value); 3338 3339 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value); 3340 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address); 3341 3342 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint); 3343 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint); 3344 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc); 3345 set_gdbarch_read_pc (gdbarch, ia64_read_pc); 3346 set_gdbarch_write_pc (gdbarch, ia64_write_pc); 3347 3348 /* Settings for calling functions in the inferior. */ 3349 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call); 3350 set_gdbarch_frame_align (gdbarch, ia64_frame_align); 3351 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id); 3352 3353 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc); 3354 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer); 3355#ifdef HAVE_LIBUNWIND_IA64_H 3356 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer); 3357 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr); 3358#endif 3359 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer); 3360 frame_base_set_default (gdbarch, &ia64_frame_base); 3361 3362 /* Settings that should be unnecessary. */ 3363 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 3364 3365 set_gdbarch_remote_translate_xfer_address ( 3366 gdbarch, ia64_remote_translate_xfer_address); 3367 3368 set_gdbarch_print_insn (gdbarch, ia64_print_insn); 3369 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr); 3370 3371 gdbarch_init_osabi (info, gdbarch); 3372 3373 return gdbarch; 3374} 3375 3376extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */ 3377 3378void 3379_initialize_ia64_tdep (void) 3380{ 3381 register_gdbarch_init (bfd_arch_ia64, ia64_gdbarch_init); 3382} 3383