1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a copy
3 * of this software and associated documentation files (the "Software"), to
4 * deal in the Software without restriction, including without limitation the
5 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
6 * sell copies of the Software, and to permit persons to whom the Software is
7 * furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
18 * DEALINGS IN THE SOFTWARE.
19 */
20
21#ifndef __XEN_PUBLIC_HVM_PARAMS_H__
22#define __XEN_PUBLIC_HVM_PARAMS_H__
23
24#include "hvm_op.h"
25
26/*
27 * Parameter space for HVMOP_{set,get}_param.
28 */
29
30/*
31 * How should CPU0 event-channel notifications be delivered?
32 * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
33 * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
34 *                  Domain = val[47:32], Bus  = val[31:16],
35 *                  DevFn  = val[15: 8], IntX = val[ 1: 0]
36 * val[63:56] == 2: val[7:0] is a vector number, check for
37 *                  XENFEAT_hvm_callback_vector to know if this delivery
38 *                  method is available.
39 * If val == 0 then CPU0 event-channel notifications are not delivered.
40 */
41#define HVM_PARAM_CALLBACK_IRQ 0
42
43/*
44 * These are not used by Xen. They are here for convenience of HVM-guest
45 * xenbus implementations.
46 */
47#define HVM_PARAM_STORE_PFN    1
48#define HVM_PARAM_STORE_EVTCHN 2
49
50#define HVM_PARAM_PAE_ENABLED  4
51
52#define HVM_PARAM_IOREQ_PFN    5
53
54#define HVM_PARAM_BUFIOREQ_PFN 6
55#define HVM_PARAM_BUFIOREQ_EVTCHN 26
56
57#ifdef __ia64__
58
59#define HVM_PARAM_NVRAM_FD     7
60#define HVM_PARAM_VHPT_SIZE    8
61#define HVM_PARAM_BUFPIOREQ_PFN	9
62
63#elif defined(__i386__) || defined(__x86_64__)
64
65/* Expose Viridian interfaces to this HVM guest? */
66#define HVM_PARAM_VIRIDIAN     9
67
68#endif
69
70/*
71 * Set mode for virtual timers (currently x86 only):
72 *  delay_for_missed_ticks (default):
73 *   Do not advance a vcpu's time beyond the correct delivery time for
74 *   interrupts that have been missed due to preemption. Deliver missed
75 *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
76 *   time stepwise for each one.
77 *  no_delay_for_missed_ticks:
78 *   As above, missed interrupts are delivered, but guest time always tracks
79 *   wallclock (i.e., real) time while doing so.
80 *  no_missed_ticks_pending:
81 *   No missed interrupts are held pending. Instead, to ensure ticks are
82 *   delivered at some non-zero rate, if we detect missed ticks then the
83 *   internal tick alarm is not disabled if the VCPU is preempted during the
84 *   next tick period.
85 *  one_missed_tick_pending:
86 *   Missed interrupts are collapsed together and delivered as one 'late tick'.
87 *   Guest time always tracks wallclock (i.e., real) time.
88 */
89#define HVM_PARAM_TIMER_MODE   10
90#define HVMPTM_delay_for_missed_ticks    0
91#define HVMPTM_no_delay_for_missed_ticks 1
92#define HVMPTM_no_missed_ticks_pending   2
93#define HVMPTM_one_missed_tick_pending   3
94
95/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
96#define HVM_PARAM_HPET_ENABLED 11
97
98/* Identity-map page directory used by Intel EPT when CR0.PG=0. */
99#define HVM_PARAM_IDENT_PT     12
100
101/* Device Model domain, defaults to 0. */
102#define HVM_PARAM_DM_DOMAIN    13
103
104/* ACPI S state: currently support S0 and S3 on x86. */
105#define HVM_PARAM_ACPI_S_STATE 14
106
107/* TSS used on Intel when CR0.PE=0. */
108#define HVM_PARAM_VM86_TSS     15
109
110/* Boolean: Enable aligning all periodic vpts to reduce interrupts */
111#define HVM_PARAM_VPT_ALIGN    16
112
113/* Console debug shared memory ring and event channel */
114#define HVM_PARAM_CONSOLE_PFN    17
115#define HVM_PARAM_CONSOLE_EVTCHN 18
116
117/*
118 * Select location of ACPI PM1a and TMR control blocks. Currently two locations
119 * are supported, specified by version 0 or 1 in this parameter:
120 *   - 0: default, use the old addresses
121 *        PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48
122 *   - 1: use the new default qemu addresses
123 *        PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008
124 * You can find these address definitions in <hvm/ioreq.h>
125 */
126#define HVM_PARAM_ACPI_IOPORTS_LOCATION 19
127
128/* Enable blocking memory events, async or sync (pause vcpu until response)
129 * onchangeonly indicates messages only on a change of value */
130#define HVM_PARAM_MEMORY_EVENT_CR0          20
131#define HVM_PARAM_MEMORY_EVENT_CR3          21
132#define HVM_PARAM_MEMORY_EVENT_CR4          22
133#define HVM_PARAM_MEMORY_EVENT_INT3         23
134#define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP  25
135
136#define HVMPME_MODE_MASK       (3 << 0)
137#define HVMPME_mode_disabled   0
138#define HVMPME_mode_async      1
139#define HVMPME_mode_sync       2
140#define HVMPME_onchangeonly    (1 << 2)
141
142/* Boolean: Enable nestedhvm (hvm only) */
143#define HVM_PARAM_NESTEDHVM    24
144
145/* Params for the mem event rings */
146#define HVM_PARAM_PAGING_RING_PFN   27
147#define HVM_PARAM_ACCESS_RING_PFN   28
148#define HVM_PARAM_SHARING_RING_PFN  29
149
150#define HVM_NR_PARAMS          30
151
152#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
153