1/*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef _LINUX_IO_H_ 30#define _LINUX_IO_H_ 31 32#include <machine/vm.h> 33 34static inline uint32_t 35__raw_readl(const volatile void *addr) 36{ 37 return *(const volatile uint32_t *)addr; 38} 39 40static inline void 41__raw_writel(uint32_t b, volatile void *addr) 42{ 43 *(volatile uint32_t *)addr = b; 44} 45 46static inline uint64_t 47__raw_readq(const volatile void *addr) 48{ 49 return *(const volatile uint64_t *)addr; 50} 51 52static inline void 53__raw_writeq(uint64_t b, volatile void *addr) 54{ 55 *(volatile uint64_t *)addr = b; 56} 57 58/* 59 * XXX This is all x86 specific. It should be bus space access. 60 */ 61#define mmiowb() 62 63#undef writel 64static inline void 65writel(uint32_t b, void *addr) 66{ 67 *(volatile uint32_t *)addr = b; 68} 69 70#undef writeq 71static inline void 72writeq(uint64_t b, void *addr) 73{ 74 *(volatile uint64_t *)addr = b; 75} 76 77#undef writeb 78static inline void 79writeb(uint8_t b, void *addr) 80{ 81 *(volatile uint8_t *)addr = b; 82} 83 84#undef writew 85static inline void 86writew(uint16_t b, void *addr) 87{ 88 *(volatile uint16_t *)addr = b; 89} 90 91void *_ioremap_attr(vm_paddr_t phys_addr, unsigned long size, int attr); 92#define ioremap_nocache(addr, size) \ 93 _ioremap_attr((addr), (size), VM_MEMATTR_UNCACHEABLE) 94#define ioremap_wc(addr, size) \ 95 _ioremap_attr((addr), (size), VM_MEMATTR_WRITE_COMBINING) 96#define ioremap ioremap_nocache 97void iounmap(void *addr); 98 99#define memset_io(a, b, c) memset((a), (b), (c)) 100#define memcpy_fromio(a, b, c) memcpy((a), (b), (c)) 101#define memcpy_toio(a, b, c) memcpy((a), (b), (c)) 102 103static inline void 104__iowrite64_copy(void *to, void *from, size_t count) 105{ 106#ifdef __LP64__ 107 uint64_t *src; 108 uint64_t *dst; 109 int i; 110 111 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) 112 __raw_writeq(*src, dst); 113#else 114 uint32_t *src; 115 uint32_t *dst; 116 int i; 117 118 count *= 2; 119 for (i = 0, src = from, dst = to; i < count; i++, src++, dst++) 120 __raw_writel(*src, dst); 121#endif 122} 123 124 125#endif /* _LINUX_IO_H_ */ 126