1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37#ifndef MLX4_H 38#define MLX4_H 39 40#include <linux/mutex.h> 41#include <linux/radix-tree.h> 42#include <linux/rbtree.h> 43#include <linux/timer.h> 44#include <linux/semaphore.h> 45#include <linux/workqueue.h> 46 47#include <linux/mlx4/device.h> 48#include <linux/mlx4/driver.h> 49#include <linux/mlx4/doorbell.h> 50#include <linux/mlx4/cmd.h> 51 52#define DRV_NAME "mlx4_core" 53#define PFX DRV_NAME ": " 54#define DRV_VERSION "1.1" 55#define DRV_RELDATE "Dec, 2011" 56 57#define MLX4_FS_UDP_UC_EN (1 << 1) 58#define MLX4_FS_TCP_UC_EN (1 << 2) 59#define MLX4_FS_NUM_OF_L2_ADDR 8 60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 61#define MLX4_FS_NUM_MCG (1 << 17) 62 63struct mlx4_set_port_prio2tc_context { 64 u8 prio2tc[4]; 65}; 66 67struct mlx4_port_scheduler_tc_cfg_be { 68 __be16 pg; 69 __be16 bw_precentage; 70 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ 71 __be16 max_bw_value; 72}; 73 74struct mlx4_set_port_scheduler_context { 75 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; 76}; 77 78enum { 79 MLX4_HCR_BASE = 0x80680, 80 MLX4_HCR_SIZE = 0x0001c, 81 MLX4_CLR_INT_SIZE = 0x00008, 82 MLX4_SLAVE_COMM_BASE = 0x0, 83 MLX4_COMM_PAGESIZE = 0x1000, 84 MLX4_CLOCK_SIZE = 0x00008 85}; 86 87enum { 88 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, 89 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, 90 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, 91 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE)/16 - 2), 92}; 93 94enum { 95 MLX4_NUM_PDS = 1 << 15 96}; 97 98enum { 99 MLX4_CMPT_TYPE_QP = 0, 100 MLX4_CMPT_TYPE_SRQ = 1, 101 MLX4_CMPT_TYPE_CQ = 2, 102 MLX4_CMPT_TYPE_EQ = 3, 103 MLX4_CMPT_NUM_TYPE 104}; 105 106enum { 107 MLX4_CMPT_SHIFT = 24, 108 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT 109}; 110 111enum mlx4_mr_state { 112 MLX4_MR_DISABLED = 0, 113 MLX4_MR_EN_HW, 114 MLX4_MR_EN_SW 115}; 116 117#define MLX4_COMM_TIME 10000 118enum { 119 MLX4_COMM_CMD_RESET, 120 MLX4_COMM_CMD_VHCR0, 121 MLX4_COMM_CMD_VHCR1, 122 MLX4_COMM_CMD_VHCR2, 123 MLX4_COMM_CMD_VHCR_EN, 124 MLX4_COMM_CMD_VHCR_POST, 125 MLX4_COMM_CMD_FLR = 254 126}; 127 128/*The flag indicates that the slave should delay the RESET cmd*/ 129#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb 130/*indicates how many retries will be done if we are in the middle of FLR*/ 131#define NUM_OF_RESET_RETRIES 10 132#define SLEEP_TIME_IN_RESET (2 * 1000) 133enum mlx4_resource { 134 RES_QP, 135 RES_CQ, 136 RES_SRQ, 137 RES_XRCD, 138 RES_MPT, 139 RES_MTT, 140 RES_MAC, 141 RES_VLAN, 142 RES_EQ, 143 RES_COUNTER, 144 RES_FS_RULE, 145 MLX4_NUM_OF_RESOURCE_TYPE 146}; 147 148enum mlx4_alloc_mode { 149 RES_OP_RESERVE, 150 RES_OP_RESERVE_AND_MAP, 151 RES_OP_MAP_ICM, 152}; 153 154enum mlx4_res_tracker_free_type { 155 RES_TR_FREE_ALL, 156 RES_TR_FREE_SLAVES_ONLY, 157 RES_TR_FREE_STRUCTS_ONLY, 158}; 159 160/* 161 *Virtual HCR structures. 162 * mlx4_vhcr is the sw representation, in machine endianess 163 * 164 * mlx4_vhcr_cmd is the formalized structure, the one that is passed 165 * to FW to go through communication channel. 166 * It is big endian, and has the same structure as the physical HCR 167 * used by command interface 168 */ 169struct mlx4_vhcr { 170 u64 in_param; 171 u64 out_param; 172 u32 in_modifier; 173 u32 errno; 174 u16 op; 175 u16 token; 176 u8 op_modifier; 177 u8 e_bit; 178}; 179 180struct mlx4_vhcr_cmd { 181 __be64 in_param; 182 __be32 in_modifier; 183 __be64 out_param; 184 __be16 token; 185 u16 reserved; 186 u8 status; 187 u8 flags; 188 __be16 opcode; 189}; 190 191struct mlx4_cmd_info { 192 u16 opcode; 193 bool has_inbox; 194 bool has_outbox; 195 bool out_is_imm; 196 bool encode_slave_id; 197 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 198 struct mlx4_cmd_mailbox *inbox); 199 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, 200 struct mlx4_cmd_mailbox *inbox, 201 struct mlx4_cmd_mailbox *outbox, 202 struct mlx4_cmd_info *cmd); 203}; 204 205#ifdef CONFIG_MLX4_DEBUG 206extern int mlx4_debug_level; 207#else /* CONFIG_MLX4_DEBUG */ 208#define mlx4_debug_level (0) 209#endif /* CONFIG_MLX4_DEBUG */ 210 211#define mlx4_dbg(mdev, format, arg...) \ 212do { \ 213 if (mlx4_debug_level) \ 214 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \ 215} while (0) 216 217#define mlx4_err(mdev, format, arg...) \ 218 dev_err(&mdev->pdev->dev, format, ##arg) 219#define mlx4_info(mdev, format, arg...) \ 220 dev_info(&mdev->pdev->dev, format, ##arg) 221#define mlx4_warn(mdev, format, arg...) \ 222 dev_warn(&mdev->pdev->dev, format, ##arg) 223 224extern int mlx4_log_num_mgm_entry_size; 225extern int log_mtts_per_seg; 226extern int mlx4_blck_lb; 227extern int mlx4_set_4k_mtu; 228 229#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) 230#define ALL_SLAVES 0xff 231 232struct mlx4_bitmap { 233 u32 last; 234 u32 top; 235 u32 max; 236 u32 reserved_top; 237 u32 mask; 238 u32 avail; 239 spinlock_t lock; 240 unsigned long *table; 241}; 242 243struct mlx4_buddy { 244 unsigned long **bits; 245 unsigned int *num_free; 246 u32 max_order; 247 spinlock_t lock; 248}; 249 250struct mlx4_icm; 251 252struct mlx4_icm_table { 253 u64 virt; 254 int num_icm; 255 u32 num_obj; 256 int obj_size; 257 int lowmem; 258 int coherent; 259 struct mutex mutex; 260 struct mlx4_icm **icm; 261}; 262 263/* 264 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. 265 */ 266struct mlx4_mpt_entry { 267 __be32 flags; 268 __be32 qpn; 269 __be32 key; 270 __be32 pd_flags; 271 __be64 start; 272 __be64 length; 273 __be32 lkey; 274 __be32 win_cnt; 275 u8 reserved1[3]; 276 u8 mtt_rep; 277 __be64 mtt_addr; 278 __be32 mtt_sz; 279 __be32 entity_size; 280 __be32 first_byte_offset; 281} __packed; 282 283/* 284 * Must be packed because start is 64 bits but only aligned to 32 bits. 285 */ 286struct mlx4_eq_context { 287 __be32 flags; 288 u16 reserved1[3]; 289 __be16 page_offset; 290 u8 log_eq_size; 291 u8 reserved2[4]; 292 u8 eq_period; 293 u8 reserved3; 294 u8 eq_max_count; 295 u8 reserved4[3]; 296 u8 intr; 297 u8 log_page_size; 298 u8 reserved5[2]; 299 u8 mtt_base_addr_h; 300 __be32 mtt_base_addr_l; 301 u32 reserved6[2]; 302 __be32 consumer_index; 303 __be32 producer_index; 304 u32 reserved7[4]; 305}; 306 307struct mlx4_cq_context { 308 __be32 flags; 309 u16 reserved1[3]; 310 __be16 page_offset; 311 __be32 logsize_usrpage; 312 __be16 cq_period; 313 __be16 cq_max_count; 314 u8 reserved2[3]; 315 u8 comp_eqn; 316 u8 log_page_size; 317 u8 reserved3[2]; 318 u8 mtt_base_addr_h; 319 __be32 mtt_base_addr_l; 320 __be32 last_notified_index; 321 __be32 solicit_producer_index; 322 __be32 consumer_index; 323 __be32 producer_index; 324 u32 reserved4[2]; 325 __be64 db_rec_addr; 326}; 327 328struct mlx4_srq_context { 329 __be32 state_logsize_srqn; 330 u8 logstride; 331 u8 reserved1; 332 __be16 xrcd; 333 __be32 pg_offset_cqn; 334 u32 reserved2; 335 u8 log_page_size; 336 u8 reserved3[2]; 337 u8 mtt_base_addr_h; 338 __be32 mtt_base_addr_l; 339 __be32 pd; 340 __be16 limit_watermark; 341 __be16 wqe_cnt; 342 u16 reserved4; 343 __be16 wqe_counter; 344 u32 reserved5; 345 __be64 db_rec_addr; 346}; 347 348struct mlx4_eq { 349 struct mlx4_dev *dev; 350 void __iomem *doorbell; 351 int eqn; 352 u32 cons_index; 353 u16 irq; 354 u16 have_irq; 355 int nent; 356 int load; 357 struct mlx4_buf_list *page_list; 358 struct mlx4_mtt mtt; 359}; 360 361struct mlx4_slave_eqe { 362 u8 type; 363 u8 port; 364 u32 param; 365}; 366 367struct mlx4_slave_event_eq_info { 368 int eqn; 369 u16 token; 370}; 371 372struct mlx4_profile { 373 int num_qp; 374 int rdmarc_per_qp; 375 int num_srq; 376 int num_cq; 377 int num_mcg; 378 int num_mpt; 379 unsigned num_mtt; 380}; 381 382struct mlx4_fw { 383 u64 clr_int_base; 384 u64 catas_offset; 385 u64 comm_base; 386 u64 clock_offset; 387 struct mlx4_icm *fw_icm; 388 struct mlx4_icm *aux_icm; 389 u32 catas_size; 390 u16 fw_pages; 391 u8 clr_int_bar; 392 u8 catas_bar; 393 u8 comm_bar; 394 u8 clock_bar; 395}; 396 397struct mlx4_comm { 398 u32 slave_write; 399 u32 slave_read; 400}; 401 402enum { 403 MLX4_MCAST_CONFIG = 0, 404 MLX4_MCAST_DISABLE = 1, 405 MLX4_MCAST_ENABLE = 2, 406}; 407 408#define VLAN_FLTR_SIZE 128 409 410struct mlx4_vlan_fltr { 411 __be32 entry[VLAN_FLTR_SIZE]; 412}; 413 414struct mlx4_mcast_entry { 415 struct list_head list; 416 u64 addr; 417}; 418 419struct mlx4_promisc_qp { 420 struct list_head list; 421 u32 qpn; 422}; 423 424struct mlx4_steer_index { 425 struct list_head list; 426 unsigned int index; 427 struct list_head duplicates; 428}; 429 430#define MLX4_EVENT_TYPES_NUM 64 431 432struct mlx4_slave_state { 433 u8 comm_toggle; 434 u8 last_cmd; 435 u8 init_port_mask; 436 bool active; 437 u8 function; 438 dma_addr_t vhcr_dma; 439 u16 mtu[MLX4_MAX_PORTS + 1]; 440 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; 441 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; 442 struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; 443 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; 444 /* event type to eq number lookup */ 445 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; 446 u16 eq_pi; 447 u16 eq_ci; 448 spinlock_t lock; 449 /*initialized via the kzalloc*/ 450 u8 is_slave_going_down; 451 u32 cookie; 452 enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; 453}; 454 455#define MLX4_VGT 4095 456#define NO_INDX (-1) 457 458struct mlx4_vport_state { 459 u64 mac; 460 u16 default_vlan; 461 u8 default_qos; 462 u32 tx_rate; 463 bool spoofchk; 464}; 465 466struct mlx4_vf_admin_state { 467 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; 468}; 469 470struct mlx4_vport_oper_state { 471 struct mlx4_vport_state state; 472 int mac_idx; 473 int vlan_idx; 474}; 475struct mlx4_vf_oper_state { 476 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; 477}; 478 479struct slave_list { 480 struct mutex mutex; 481 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; 482}; 483 484struct resource_allocator { 485 spinlock_t alloc_lock; 486 union { 487 int res_reserved; 488 int res_port_rsvd[MLX4_MAX_PORTS]; 489 }; 490 union { 491 int res_free; 492 int res_port_free[MLX4_MAX_PORTS]; 493 }; 494 int *quota; 495 int *allocated; 496 int *guaranteed; 497}; 498 499struct mlx4_resource_tracker { 500 spinlock_t lock; 501 /* tree for each resources */ 502 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; 503 /* num_of_slave's lists, one per slave */ 504 struct slave_list *slave_list; 505 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; 506}; 507 508#define SLAVE_EVENT_EQ_SIZE 128 509struct mlx4_slave_event_eq { 510 u32 eqn; 511 u32 cons; 512 u32 prod; 513 spinlock_t event_lock; 514 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; 515}; 516 517struct mlx4_master_qp0_state { 518 int proxy_qp0_active; 519 int qp0_active; 520 int port_active; 521}; 522 523struct mlx4_mfunc_master_ctx { 524 struct mlx4_slave_state *slave_state; 525 struct mlx4_vf_admin_state *vf_admin; 526 struct mlx4_vf_oper_state *vf_oper; 527 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; 528 int init_port_ref[MLX4_MAX_PORTS + 1]; 529 u16 max_mtu[MLX4_MAX_PORTS + 1]; 530 int disable_mcast_ref[MLX4_MAX_PORTS + 1]; 531 struct mlx4_resource_tracker res_tracker; 532 struct workqueue_struct *comm_wq; 533 struct work_struct comm_work; 534 struct work_struct slave_event_work; 535 struct work_struct slave_flr_event_work; 536 spinlock_t slave_state_lock; 537 __be32 comm_arm_bit_vector[4]; 538 struct mlx4_eqe cmd_eqe; 539 struct mlx4_slave_event_eq slave_eq; 540 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; 541}; 542 543struct mlx4_mfunc { 544 struct mlx4_comm __iomem *comm; 545 struct mlx4_vhcr_cmd *vhcr; 546 dma_addr_t vhcr_dma; 547 548 struct mlx4_mfunc_master_ctx master; 549}; 550 551#define MGM_QPN_MASK 0x00FFFFFF 552#define MGM_BLCK_LB_BIT 30 553 554struct mlx4_mgm { 555 __be32 next_gid_index; 556 __be32 members_count; 557 u32 reserved[2]; 558 u8 gid[16]; 559 __be32 qp[MLX4_MAX_QP_PER_MGM]; 560}; 561 562struct mlx4_cmd { 563 struct pci_pool *pool; 564 void __iomem *hcr; 565 struct mutex hcr_mutex; 566 struct mutex slave_cmd_mutex; 567 struct semaphore poll_sem; 568 struct semaphore event_sem; 569 int max_cmds; 570 spinlock_t context_lock; 571 int free_head; 572 struct mlx4_cmd_context *context; 573 u16 token_mask; 574 u8 use_events; 575 u8 toggle; 576 u8 comm_toggle; 577}; 578 579struct mlx4_uar_table { 580 struct mlx4_bitmap bitmap; 581}; 582 583struct mlx4_mr_table { 584 struct mlx4_bitmap mpt_bitmap; 585 struct mlx4_buddy mtt_buddy; 586 u64 mtt_base; 587 u64 mpt_base; 588 struct mlx4_icm_table mtt_table; 589 struct mlx4_icm_table dmpt_table; 590}; 591 592struct mlx4_cq_table { 593 struct mlx4_bitmap bitmap; 594 spinlock_t lock; 595 struct radix_tree_root tree; 596 struct mlx4_icm_table table; 597 struct mlx4_icm_table cmpt_table; 598}; 599 600struct mlx4_eq_table { 601 struct mlx4_bitmap bitmap; 602 char *irq_names; 603 void __iomem *clr_int; 604 void __iomem **uar_map; 605 u32 clr_mask; 606 struct mlx4_eq *eq; 607 struct mlx4_icm_table table; 608 struct mlx4_icm_table cmpt_table; 609 int have_irq; 610 u8 inta_pin; 611}; 612 613struct mlx4_srq_table { 614 struct mlx4_bitmap bitmap; 615 spinlock_t lock; 616 struct radix_tree_root tree; 617 struct mlx4_icm_table table; 618 struct mlx4_icm_table cmpt_table; 619}; 620 621struct mlx4_qp_table { 622 struct mlx4_bitmap bitmap; 623 u32 rdmarc_base; 624 int rdmarc_shift; 625 spinlock_t lock; 626 struct mlx4_icm_table qp_table; 627 struct mlx4_icm_table auxc_table; 628 struct mlx4_icm_table altc_table; 629 struct mlx4_icm_table rdmarc_table; 630 struct mlx4_icm_table cmpt_table; 631}; 632 633struct mlx4_mcg_table { 634 struct mutex mutex; 635 struct mlx4_bitmap bitmap; 636 struct mlx4_icm_table table; 637}; 638 639struct mlx4_catas_err { 640 u32 __iomem *map; 641 struct timer_list timer; 642 struct list_head list; 643}; 644 645#define MLX4_MAX_MAC_NUM 128 646#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) 647 648struct mlx4_mac_table { 649 __be64 entries[MLX4_MAX_MAC_NUM]; 650 int refs[MLX4_MAX_MAC_NUM]; 651 struct mutex mutex; 652 int total; 653 int max; 654}; 655 656#define MLX4_MAX_VLAN_NUM 128 657#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) 658 659struct mlx4_vlan_table { 660 __be32 entries[MLX4_MAX_VLAN_NUM]; 661 int refs[MLX4_MAX_VLAN_NUM]; 662 struct mutex mutex; 663 int total; 664 int max; 665}; 666 667#define SET_PORT_GEN_ALL_VALID 0x7 668#define SET_PORT_PROMISC_SHIFT 31 669#define SET_PORT_MC_PROMISC_SHIFT 30 670 671enum { 672 MCAST_DIRECT_ONLY = 0, 673 MCAST_DIRECT = 1, 674 MCAST_DEFAULT = 2 675}; 676 677 678struct mlx4_set_port_general_context { 679 u8 reserved[3]; 680 u8 flags; 681 u16 reserved2; 682 __be16 mtu; 683 u8 pptx; 684 u8 pfctx; 685 u16 reserved3; 686 u8 pprx; 687 u8 pfcrx; 688 u16 reserved4; 689}; 690 691struct mlx4_set_port_rqp_calc_context { 692 __be32 base_qpn; 693 u8 rererved; 694 u8 n_mac; 695 u8 n_vlan; 696 u8 n_prio; 697 u8 reserved2[3]; 698 u8 mac_miss; 699 u8 intra_no_vlan; 700 u8 no_vlan; 701 u8 intra_vlan_miss; 702 u8 vlan_miss; 703 u8 reserved3[3]; 704 u8 no_vlan_prio; 705 __be32 promisc; 706 __be32 mcast; 707}; 708 709struct mlx4_port_info { 710 struct mlx4_dev *dev; 711 int port; 712 char dev_name[16]; 713 struct device_attribute port_attr; 714 enum mlx4_port_type tmp_type; 715 char dev_mtu_name[16]; 716 struct device_attribute port_mtu_attr; 717 struct mlx4_mac_table mac_table; 718 struct mlx4_vlan_table vlan_table; 719 int base_qpn; 720}; 721 722struct mlx4_sense { 723 struct mlx4_dev *dev; 724 u8 do_sense_port[MLX4_MAX_PORTS + 1]; 725 u8 sense_allowed[MLX4_MAX_PORTS + 1]; 726 struct delayed_work sense_poll; 727 struct workqueue_struct *sense_wq; 728 u32 resched; 729}; 730 731struct mlx4_msix_ctl { 732 u64 pool_bm; 733 struct mutex pool_lock; 734}; 735 736struct mlx4_steer { 737 struct list_head promisc_qps[MLX4_NUM_STEERS]; 738 struct list_head steer_entries[MLX4_NUM_STEERS]; 739}; 740 741struct mlx4_net_trans_rule_hw_ctrl { 742 __be32 ctrl; 743 u8 rsvd1; 744 u8 funcid; 745 u8 vep; 746 u8 port; 747 __be32 qpn; 748 __be32 rsvd2; 749}; 750 751struct mlx4_net_trans_rule_hw_ib { 752 u8 size; 753 u8 rsvd1; 754 __be16 id; 755 u32 rsvd2; 756 __be32 r_u_qpn; 757 __be32 qpn_mask; 758 u8 dst_gid[16]; 759 u8 dst_gid_msk[16]; 760} __packed; 761 762struct mlx4_net_trans_rule_hw_eth { 763 u8 size; 764 u8 rsvd; 765 __be16 id; 766 u8 rsvd1[6]; 767 u8 dst_mac[6]; 768 u16 rsvd2; 769 u8 dst_mac_msk[6]; 770 u16 rsvd3; 771 u8 src_mac[6]; 772 u16 rsvd4; 773 u8 src_mac_msk[6]; 774 u8 rsvd5; 775 u8 ether_type_enable; 776 __be16 ether_type; 777 __be16 vlan_id_msk; 778 __be16 vlan_id; 779} __packed; 780 781struct mlx4_net_trans_rule_hw_tcp_udp { 782 u8 size; 783 u8 rsvd; 784 __be16 id; 785 __be16 rsvd1[3]; 786 __be16 dst_port; 787 __be16 rsvd2; 788 __be16 dst_port_msk; 789 __be16 rsvd3; 790 __be16 src_port; 791 __be16 rsvd4; 792 __be16 src_port_msk; 793} __packed; 794 795struct mlx4_net_trans_rule_hw_ipv4 { 796 u8 size; 797 u8 rsvd; 798 __be16 id; 799 __be32 rsvd1; 800 __be32 dst_ip; 801 __be32 dst_ip_msk; 802 __be32 src_ip; 803 __be32 src_ip_msk; 804} __packed; 805 806struct _rule_hw { 807 union { 808 struct { 809 u8 size; 810 u8 rsvd; 811 __be16 id; 812 }; 813 struct mlx4_net_trans_rule_hw_eth eth; 814 struct mlx4_net_trans_rule_hw_ib ib; 815 struct mlx4_net_trans_rule_hw_ipv4 ipv4; 816 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; 817 }; 818}; 819 820enum { 821 MLX4_PCI_DEV_IS_VF = 1 << 0, 822 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, 823}; 824 825struct mlx4_roce_gid_entry { 826 u8 raw[16]; 827}; 828 829struct mlx4_priv { 830 struct mlx4_dev dev; 831 832 struct list_head dev_list; 833 struct list_head ctx_list; 834 spinlock_t ctx_lock; 835 836 int pci_dev_data; 837 838 struct list_head pgdir_list; 839 struct mutex pgdir_mutex; 840 841 struct mlx4_fw fw; 842 struct mlx4_cmd cmd; 843 struct mlx4_mfunc mfunc; 844 845 struct mlx4_bitmap pd_bitmap; 846 struct mlx4_bitmap xrcd_bitmap; 847 struct mlx4_uar_table uar_table; 848 struct mlx4_mr_table mr_table; 849 struct mlx4_cq_table cq_table; 850 struct mlx4_eq_table eq_table; 851 struct mlx4_srq_table srq_table; 852 struct mlx4_qp_table qp_table; 853 struct mlx4_mcg_table mcg_table; 854 struct mlx4_bitmap counters_bitmap; 855 856 struct mlx4_catas_err catas_err; 857 858 void __iomem *clr_base; 859 860 struct mlx4_uar driver_uar; 861 void __iomem *kar; 862 struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; 863 struct mlx4_sense sense; 864 struct mutex port_mutex; 865 struct mlx4_msix_ctl msix_ctl; 866 struct mlx4_steer *steer; 867 struct list_head bf_list; 868 struct mutex bf_mutex; 869 struct io_mapping *bf_mapping; 870 void __iomem *clock_mapping; 871 int reserved_mtts; 872 int fs_hash_mode; 873 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; 874 __be64 slave_node_guids[MLX4_MFUNC_MAX]; 875 struct mlx4_roce_gid_entry roce_gids[MLX4_MAX_PORTS][128]; 876 atomic_t opreq_count; 877 struct work_struct opreq_task; 878}; 879 880static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) 881{ 882 return container_of(dev, struct mlx4_priv, dev); 883} 884 885#define MLX4_SENSE_RANGE (HZ * 3) 886 887extern struct workqueue_struct *mlx4_wq; 888 889u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); 890void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj); 891u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, 892 int align, u32 skip_mask); 893void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt); 894u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); 895int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, 896 u32 reserved_bot, u32 resetrved_top); 897void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); 898 899int mlx4_reset(struct mlx4_dev *dev); 900 901int mlx4_alloc_eq_table(struct mlx4_dev *dev); 902void mlx4_free_eq_table(struct mlx4_dev *dev); 903 904int mlx4_init_pd_table(struct mlx4_dev *dev); 905int mlx4_init_xrcd_table(struct mlx4_dev *dev); 906int mlx4_init_uar_table(struct mlx4_dev *dev); 907int mlx4_init_mr_table(struct mlx4_dev *dev); 908int mlx4_init_eq_table(struct mlx4_dev *dev); 909int mlx4_init_cq_table(struct mlx4_dev *dev); 910int mlx4_init_qp_table(struct mlx4_dev *dev); 911int mlx4_init_srq_table(struct mlx4_dev *dev); 912int mlx4_init_mcg_table(struct mlx4_dev *dev); 913 914void mlx4_cleanup_pd_table(struct mlx4_dev *dev); 915void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); 916void mlx4_cleanup_uar_table(struct mlx4_dev *dev); 917void mlx4_cleanup_mr_table(struct mlx4_dev *dev); 918void mlx4_cleanup_eq_table(struct mlx4_dev *dev); 919void mlx4_cleanup_cq_table(struct mlx4_dev *dev); 920void mlx4_cleanup_qp_table(struct mlx4_dev *dev); 921void mlx4_cleanup_srq_table(struct mlx4_dev *dev); 922void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); 923int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn); 924void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); 925int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); 926void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); 927int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); 928void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); 929int __mlx4_mr_reserve(struct mlx4_dev *dev); 930void __mlx4_mr_release(struct mlx4_dev *dev, u32 index); 931int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index); 932void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index); 933u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); 934void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); 935 936int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, 937 struct mlx4_vhcr *vhcr, 938 struct mlx4_cmd_mailbox *inbox, 939 struct mlx4_cmd_mailbox *outbox, 940 struct mlx4_cmd_info *cmd); 941int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, 942 struct mlx4_vhcr *vhcr, 943 struct mlx4_cmd_mailbox *inbox, 944 struct mlx4_cmd_mailbox *outbox, 945 struct mlx4_cmd_info *cmd); 946int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, 947 struct mlx4_vhcr *vhcr, 948 struct mlx4_cmd_mailbox *inbox, 949 struct mlx4_cmd_mailbox *outbox, 950 struct mlx4_cmd_info *cmd); 951int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, 952 struct mlx4_vhcr *vhcr, 953 struct mlx4_cmd_mailbox *inbox, 954 struct mlx4_cmd_mailbox *outbox, 955 struct mlx4_cmd_info *cmd); 956int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, 957 struct mlx4_vhcr *vhcr, 958 struct mlx4_cmd_mailbox *inbox, 959 struct mlx4_cmd_mailbox *outbox, 960 struct mlx4_cmd_info *cmd); 961int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, 962 struct mlx4_vhcr *vhcr, 963 struct mlx4_cmd_mailbox *inbox, 964 struct mlx4_cmd_mailbox *outbox, 965 struct mlx4_cmd_info *cmd); 966int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, 967 struct mlx4_vhcr *vhcr, 968 struct mlx4_cmd_mailbox *inbox, 969 struct mlx4_cmd_mailbox *outbox, 970 struct mlx4_cmd_info *cmd); 971int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, 972 int *base, u8 bf_qp); 973void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 974int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); 975void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); 976int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 977 int start_index, int npages, u64 *page_list); 978int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 979void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 980int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 981void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 982 983void mlx4_start_catas_poll(struct mlx4_dev *dev); 984void mlx4_stop_catas_poll(struct mlx4_dev *dev); 985void mlx4_catas_init(void); 986int mlx4_restart_one(struct pci_dev *pdev); 987int mlx4_register_device(struct mlx4_dev *dev); 988void mlx4_unregister_device(struct mlx4_dev *dev); 989void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, 990 unsigned long param); 991 992struct mlx4_dev_cap; 993struct mlx4_init_hca_param; 994 995u64 mlx4_make_profile(struct mlx4_dev *dev, 996 struct mlx4_profile *request, 997 struct mlx4_dev_cap *dev_cap, 998 struct mlx4_init_hca_param *init_hca); 999void mlx4_master_comm_channel(struct work_struct *work); 1000void mlx4_gen_slave_eqe(struct work_struct *work); 1001void mlx4_master_handle_slave_flr(struct work_struct *work); 1002 1003int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, 1004 struct mlx4_vhcr *vhcr, 1005 struct mlx4_cmd_mailbox *inbox, 1006 struct mlx4_cmd_mailbox *outbox, 1007 struct mlx4_cmd_info *cmd); 1008int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, 1009 struct mlx4_vhcr *vhcr, 1010 struct mlx4_cmd_mailbox *inbox, 1011 struct mlx4_cmd_mailbox *outbox, 1012 struct mlx4_cmd_info *cmd); 1013int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 1014 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, 1015 struct mlx4_cmd_mailbox *outbox, 1016 struct mlx4_cmd_info *cmd); 1017int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, 1018 struct mlx4_vhcr *vhcr, 1019 struct mlx4_cmd_mailbox *inbox, 1020 struct mlx4_cmd_mailbox *outbox, 1021 struct mlx4_cmd_info *cmd); 1022int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, 1023 struct mlx4_vhcr *vhcr, 1024 struct mlx4_cmd_mailbox *inbox, 1025 struct mlx4_cmd_mailbox *outbox, 1026 struct mlx4_cmd_info *cmd); 1027int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, 1028 struct mlx4_vhcr *vhcr, 1029 struct mlx4_cmd_mailbox *inbox, 1030 struct mlx4_cmd_mailbox *outbox, 1031 struct mlx4_cmd_info *cmd); 1032int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1033 struct mlx4_vhcr *vhcr, 1034 struct mlx4_cmd_mailbox *inbox, 1035 struct mlx4_cmd_mailbox *outbox, 1036 struct mlx4_cmd_info *cmd); 1037int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, 1038 struct mlx4_vhcr *vhcr, 1039 struct mlx4_cmd_mailbox *inbox, 1040 struct mlx4_cmd_mailbox *outbox, 1041 struct mlx4_cmd_info *cmd); 1042int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1043 struct mlx4_vhcr *vhcr, 1044 struct mlx4_cmd_mailbox *inbox, 1045 struct mlx4_cmd_mailbox *outbox, 1046 struct mlx4_cmd_info *cmd); 1047int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, 1048 struct mlx4_vhcr *vhcr, 1049 struct mlx4_cmd_mailbox *inbox, 1050 struct mlx4_cmd_mailbox *outbox, 1051 struct mlx4_cmd_info *cmd); 1052int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1053 struct mlx4_vhcr *vhcr, 1054 struct mlx4_cmd_mailbox *inbox, 1055 struct mlx4_cmd_mailbox *outbox, 1056 struct mlx4_cmd_info *cmd); 1057int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1058 struct mlx4_vhcr *vhcr, 1059 struct mlx4_cmd_mailbox *inbox, 1060 struct mlx4_cmd_mailbox *outbox, 1061 struct mlx4_cmd_info *cmd); 1062int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1063 struct mlx4_vhcr *vhcr, 1064 struct mlx4_cmd_mailbox *inbox, 1065 struct mlx4_cmd_mailbox *outbox, 1066 struct mlx4_cmd_info *cmd); 1067int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, 1068 struct mlx4_vhcr *vhcr, 1069 struct mlx4_cmd_mailbox *inbox, 1070 struct mlx4_cmd_mailbox *outbox, 1071 struct mlx4_cmd_info *cmd); 1072int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, 1073 struct mlx4_vhcr *vhcr, 1074 struct mlx4_cmd_mailbox *inbox, 1075 struct mlx4_cmd_mailbox *outbox, 1076 struct mlx4_cmd_info *cmd); 1077int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1078 struct mlx4_vhcr *vhcr, 1079 struct mlx4_cmd_mailbox *inbox, 1080 struct mlx4_cmd_mailbox *outbox, 1081 struct mlx4_cmd_info *cmd); 1082int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, 1083 struct mlx4_vhcr *vhcr, 1084 struct mlx4_cmd_mailbox *inbox, 1085 struct mlx4_cmd_mailbox *outbox, 1086 struct mlx4_cmd_info *cmd); 1087int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, 1088 struct mlx4_vhcr *vhcr, 1089 struct mlx4_cmd_mailbox *inbox, 1090 struct mlx4_cmd_mailbox *outbox, 1091 struct mlx4_cmd_info *cmd); 1092int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1093 struct mlx4_vhcr *vhcr, 1094 struct mlx4_cmd_mailbox *inbox, 1095 struct mlx4_cmd_mailbox *outbox, 1096 struct mlx4_cmd_info *cmd); 1097int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1098 struct mlx4_vhcr *vhcr, 1099 struct mlx4_cmd_mailbox *inbox, 1100 struct mlx4_cmd_mailbox *outbox, 1101 struct mlx4_cmd_info *cmd); 1102int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1103 struct mlx4_vhcr *vhcr, 1104 struct mlx4_cmd_mailbox *inbox, 1105 struct mlx4_cmd_mailbox *outbox, 1106 struct mlx4_cmd_info *cmd); 1107int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, 1108 struct mlx4_vhcr *vhcr, 1109 struct mlx4_cmd_mailbox *inbox, 1110 struct mlx4_cmd_mailbox *outbox, 1111 struct mlx4_cmd_info *cmd); 1112int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1113 struct mlx4_vhcr *vhcr, 1114 struct mlx4_cmd_mailbox *inbox, 1115 struct mlx4_cmd_mailbox *outbox, 1116 struct mlx4_cmd_info *cmd); 1117int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, 1118 struct mlx4_vhcr *vhcr, 1119 struct mlx4_cmd_mailbox *inbox, 1120 struct mlx4_cmd_mailbox *outbox, 1121 struct mlx4_cmd_info *cmd); 1122int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, 1123 struct mlx4_vhcr *vhcr, 1124 struct mlx4_cmd_mailbox *inbox, 1125 struct mlx4_cmd_mailbox *outbox, 1126 struct mlx4_cmd_info *cmd); 1127int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, 1128 struct mlx4_vhcr *vhcr, 1129 struct mlx4_cmd_mailbox *inbox, 1130 struct mlx4_cmd_mailbox *outbox, 1131 struct mlx4_cmd_info *cmd); 1132int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, 1133 struct mlx4_vhcr *vhcr, 1134 struct mlx4_cmd_mailbox *inbox, 1135 struct mlx4_cmd_mailbox *outbox, 1136 struct mlx4_cmd_info *cmd); 1137 1138int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); 1139 1140int mlx4_cmd_init(struct mlx4_dev *dev); 1141void mlx4_cmd_cleanup(struct mlx4_dev *dev); 1142int mlx4_multi_func_init(struct mlx4_dev *dev); 1143void mlx4_multi_func_cleanup(struct mlx4_dev *dev); 1144void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); 1145int mlx4_cmd_use_events(struct mlx4_dev *dev); 1146void mlx4_cmd_use_polling(struct mlx4_dev *dev); 1147 1148int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, 1149 unsigned long timeout); 1150 1151void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); 1152void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); 1153 1154void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); 1155 1156void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); 1157 1158void mlx4_handle_catas_err(struct mlx4_dev *dev); 1159 1160int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, 1161 enum mlx4_port_type *type); 1162void mlx4_do_sense_ports(struct mlx4_dev *dev, 1163 enum mlx4_port_type *stype, 1164 enum mlx4_port_type *defaults); 1165void mlx4_start_sense(struct mlx4_dev *dev); 1166void mlx4_stop_sense(struct mlx4_dev *dev); 1167void mlx4_sense_cleanup(struct mlx4_dev *dev); 1168int mlx4_sense_init(struct mlx4_dev *dev); 1169int mlx4_check_port_params(struct mlx4_dev *dev, 1170 enum mlx4_port_type *port_type); 1171int mlx4_change_port_types(struct mlx4_dev *dev, 1172 enum mlx4_port_type *port_types); 1173 1174void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); 1175void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); 1176void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); 1177int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 1178 1179int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); 1180/* resource tracker functions*/ 1181int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, 1182 enum mlx4_resource resource_type, 1183 u64 resource_id, int *slave); 1184void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); 1185int mlx4_init_resource_tracker(struct mlx4_dev *dev); 1186 1187void mlx4_free_resource_tracker(struct mlx4_dev *dev, 1188 enum mlx4_res_tracker_free_type type); 1189 1190int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, 1191 struct mlx4_vhcr *vhcr, 1192 struct mlx4_cmd_mailbox *inbox, 1193 struct mlx4_cmd_mailbox *outbox, 1194 struct mlx4_cmd_info *cmd); 1195int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, 1196 struct mlx4_vhcr *vhcr, 1197 struct mlx4_cmd_mailbox *inbox, 1198 struct mlx4_cmd_mailbox *outbox, 1199 struct mlx4_cmd_info *cmd); 1200int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, 1201 struct mlx4_vhcr *vhcr, 1202 struct mlx4_cmd_mailbox *inbox, 1203 struct mlx4_cmd_mailbox *outbox, 1204 struct mlx4_cmd_info *cmd); 1205int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, 1206 struct mlx4_vhcr *vhcr, 1207 struct mlx4_cmd_mailbox *inbox, 1208 struct mlx4_cmd_mailbox *outbox, 1209 struct mlx4_cmd_info *cmd); 1210int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, 1211 struct mlx4_vhcr *vhcr, 1212 struct mlx4_cmd_mailbox *inbox, 1213 struct mlx4_cmd_mailbox *outbox, 1214 struct mlx4_cmd_info *cmd); 1215int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, 1216 struct mlx4_vhcr *vhcr, 1217 struct mlx4_cmd_mailbox *inbox, 1218 struct mlx4_cmd_mailbox *outbox, 1219 struct mlx4_cmd_info *cmd); 1220int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); 1221 1222int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, 1223 int *gid_tbl_len, int *pkey_tbl_len); 1224 1225int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1226 struct mlx4_vhcr *vhcr, 1227 struct mlx4_cmd_mailbox *inbox, 1228 struct mlx4_cmd_mailbox *outbox, 1229 struct mlx4_cmd_info *cmd); 1230 1231int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, 1232 struct mlx4_vhcr *vhcr, 1233 struct mlx4_cmd_mailbox *inbox, 1234 struct mlx4_cmd_mailbox *outbox, 1235 struct mlx4_cmd_info *cmd); 1236int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1237 enum mlx4_protocol prot, enum mlx4_steer_type steer); 1238int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 1239 int block_mcast_loopback, enum mlx4_protocol prot, 1240 enum mlx4_steer_type steer); 1241int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1242 struct mlx4_vhcr *vhcr, 1243 struct mlx4_cmd_mailbox *inbox, 1244 struct mlx4_cmd_mailbox *outbox, 1245 struct mlx4_cmd_info *cmd); 1246int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, 1247 struct mlx4_vhcr *vhcr, 1248 struct mlx4_cmd_mailbox *inbox, 1249 struct mlx4_cmd_mailbox *outbox, 1250 struct mlx4_cmd_info *cmd); 1251int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, 1252 int port, void *buf); 1253int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, 1254 struct mlx4_cmd_mailbox *outbox); 1255int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, 1256 struct mlx4_vhcr *vhcr, 1257 struct mlx4_cmd_mailbox *inbox, 1258 struct mlx4_cmd_mailbox *outbox, 1259 struct mlx4_cmd_info *cmd); 1260int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, 1261 struct mlx4_vhcr *vhcr, 1262 struct mlx4_cmd_mailbox *inbox, 1263 struct mlx4_cmd_mailbox *outbox, 1264 struct mlx4_cmd_info *cmd); 1265int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, 1266 struct mlx4_vhcr *vhcr, 1267 struct mlx4_cmd_mailbox *inbox, 1268 struct mlx4_cmd_mailbox *outbox, 1269 struct mlx4_cmd_info *cmd); 1270int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, 1271 struct mlx4_vhcr *vhcr, 1272 struct mlx4_cmd_mailbox *inbox, 1273 struct mlx4_cmd_mailbox *outbox, 1274 struct mlx4_cmd_info *cmd); 1275int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, 1276 struct mlx4_vhcr *vhcr, 1277 struct mlx4_cmd_mailbox *inbox, 1278 struct mlx4_cmd_mailbox *outbox, 1279 struct mlx4_cmd_info *cmd); 1280 1281int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); 1282int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); 1283 1284static inline void set_param_l(u64 *arg, u32 val) 1285{ 1286 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; 1287} 1288 1289static inline void set_param_h(u64 *arg, u32 val) 1290{ 1291 *arg = (*arg & 0xffffffff) | ((u64) val << 32); 1292} 1293 1294static inline u32 get_param_l(u64 *arg) 1295{ 1296 return (u32) (*arg & 0xffffffff); 1297} 1298 1299static inline u32 get_param_h(u64 *arg) 1300{ 1301 return (u32)(*arg >> 32); 1302} 1303 1304static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) 1305{ 1306 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; 1307} 1308 1309#define NOT_MASKED_PD_BITS 17 1310 1311void sys_tune_init(void); 1312void sys_tune_fini(void); 1313 1314void mlx4_init_quotas(struct mlx4_dev *dev); 1315 1316int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave); 1317int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave); 1318 1319#endif /* MLX4_H */ 1320