pmap.c revision 210627
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 210627 2010-07-29 20:02:56Z jchandra $"); 70 71#include "opt_msgbuf.h" 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/proc.h> 75#include <sys/msgbuf.h> 76#include <sys/vmmeter.h> 77#include <sys/mman.h> 78#include <sys/smp.h> 79 80#include <vm/vm.h> 81#include <vm/vm_param.h> 82#include <vm/vm_phys.h> 83#include <sys/lock.h> 84#include <sys/mutex.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93#include <sys/pcpu.h> 94#include <sys/sched.h> 95#ifdef SMP 96#include <sys/smp.h> 97#endif 98 99#include <machine/cache.h> 100#include <machine/md_var.h> 101#include <machine/tlb.h> 102 103#if defined(DIAGNOSTIC) 104#define PMAP_DIAGNOSTIC 105#endif 106 107#undef PMAP_DEBUG 108 109#ifndef PMAP_SHPGPERPROC 110#define PMAP_SHPGPERPROC 200 111#endif 112 113#if !defined(PMAP_DIAGNOSTIC) 114#define PMAP_INLINE __inline 115#else 116#define PMAP_INLINE 117#endif 118 119/* 120 * Get PDEs and PTEs for user/kernel address space 121 * 122 * XXX The & for pmap_segshift() is wrong, as is the fact that it doesn't 123 * trim off gratuitous bits of the address space. By having the & 124 * there, we break defining NUSERPGTBLS below because the address space 125 * is defined such that it ends immediately after NPDEPG*NPTEPG*PAGE_SIZE, 126 * so we end up getting NUSERPGTBLS of 0. 127 */ 128#define pmap_segshift(v) (((v) >> SEGSHIFT) & (NPDEPG - 1)) 129#define segtab_pde(m, v) ((m)[pmap_segshift((v))]) 130 131#if defined(__mips_n64) 132#define NUSERPGTBLS (NPDEPG) 133#else 134#define NUSERPGTBLS (pmap_segshift(VM_MAXUSER_ADDRESS)) 135#endif 136#define mips_segtrunc(va) ((va) & ~SEGMASK) 137#define is_kernel_pmap(x) ((x) == kernel_pmap) 138 139/* 140 * Given a virtual address, get the offset of its PTE within its page 141 * directory page. 142 */ 143#define PDE_OFFSET(va) (((vm_offset_t)(va) >> PAGE_SHIFT) & (NPTEPG - 1)) 144 145struct pmap kernel_pmap_store; 146pd_entry_t *kernel_segmap; 147 148vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 149vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 150 151static int nkpt; 152unsigned pmap_max_asid; /* max ASID supported by the system */ 153 154 155#define PMAP_ASID_RESERVED 0 156 157vm_offset_t kernel_vm_end; 158 159static void pmap_asid_alloc(pmap_t pmap); 160 161/* 162 * Data for the pv entry allocation mechanism 163 */ 164static uma_zone_t pvzone; 165static struct vm_object pvzone_obj; 166static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 167 168static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 169static pv_entry_t get_pv_entry(pmap_t locked_pmap); 170static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 171static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 172 vm_offset_t va); 173static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 174 175static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 176 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 177static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 178static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 179static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 180static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 181 vm_offset_t va, vm_page_t m); 182static __inline void 183pmap_invalidate_page(pmap_t pmap, vm_offset_t va); 184 185static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 186 187static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 188static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 189static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 190static vm_page_t pmap_alloc_pte_page(unsigned int index, int req); 191static void pmap_grow_pte_page_cache(void); 192 193#ifdef SMP 194static void pmap_invalidate_page_action(void *arg); 195static void pmap_invalidate_all_action(void *arg); 196static void pmap_update_page_action(void *arg); 197#endif 198 199#if !defined(__mips_n64) 200struct local_sysmaps { 201 vm_offset_t base; 202 uint16_t valid1, valid2; 203}; 204 205/* This structure is for large memory 206 * above 512Meg. We can't (in 32 bit mode) 207 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 208 * macros since we can't see the memory and must 209 * map it in when we need to access it. In 64 210 * bit mode this goes away. 211 */ 212static struct local_sysmaps sysmap_lmem[MAXCPU]; 213 214#define PMAP_LMEM_MAP1(va, phys) \ 215 int cpu; \ 216 struct local_sysmaps *sysm; \ 217 pt_entry_t *pte, npte; \ 218 \ 219 intr = intr_disable(); \ 220 cpu = PCPU_GET(cpuid); \ 221 sysm = &sysmap_lmem[cpu]; \ 222 va = sysm->base; \ 223 npte = TLBLO_PA_TO_PFN(phys) | \ 224 PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; \ 225 pte = pmap_pte(kernel_pmap, va); \ 226 *pte = npte; \ 227 sysm->valid1 = 1 228 229#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 230 int cpu; \ 231 struct local_sysmaps *sysm; \ 232 pt_entry_t *pte, npte; \ 233 \ 234 intr = intr_disable(); \ 235 cpu = PCPU_GET(cpuid); \ 236 sysm = &sysmap_lmem[cpu]; \ 237 va1 = sysm->base; \ 238 va2 = sysm->base + PAGE_SIZE; \ 239 npte = TLBLO_PA_TO_PFN(phys1) | \ 240 PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; \ 241 pte = pmap_pte(kernel_pmap, va1); \ 242 *pte = npte; \ 243 npte = TLBLO_PA_TO_PFN(phys2) | \ 244 PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; \ 245 pte = pmap_pte(kernel_pmap, va2); \ 246 *pte = npte; \ 247 sysm->valid1 = 1; \ 248 sysm->valid2 = 1; 249 250#define PMAP_LMEM_UNMAP() \ 251 pte = pmap_pte(kernel_pmap, sysm->base); \ 252 *pte = PTE_G; \ 253 tlb_invalidate_address(kernel_pmap, sysm->base); \ 254 sysm->valid1 = 0; \ 255 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 256 *pte = PTE_G; \ 257 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE); \ 258 sysm->valid2 = 0; \ 259 intr_restore(intr) 260#endif 261 262static inline pt_entry_t * 263pmap_segmap(pmap_t pmap, vm_offset_t va) 264{ 265 if (pmap->pm_segtab != NULL) 266 return (segtab_pde(pmap->pm_segtab, va)); 267 else 268 return (NULL); 269} 270 271/* 272 * Routine: pmap_pte 273 * Function: 274 * Extract the page table entry associated 275 * with the given map/virtual_address pair. 276 */ 277pt_entry_t * 278pmap_pte(pmap_t pmap, vm_offset_t va) 279{ 280 pt_entry_t *pdeaddr; 281 282 if (pmap) { 283 pdeaddr = pmap_segmap(pmap, va); 284 if (pdeaddr) { 285 return pdeaddr + PDE_OFFSET(va); 286 } 287 } 288 return ((pt_entry_t *)0); 289} 290 291 292vm_offset_t 293pmap_steal_memory(vm_size_t size) 294{ 295 vm_size_t bank_size; 296 vm_offset_t pa, va; 297 298 size = round_page(size); 299 300 bank_size = phys_avail[1] - phys_avail[0]; 301 while (size > bank_size) { 302 int i; 303 304 for (i = 0; phys_avail[i + 2]; i += 2) { 305 phys_avail[i] = phys_avail[i + 2]; 306 phys_avail[i + 1] = phys_avail[i + 3]; 307 } 308 phys_avail[i] = 0; 309 phys_avail[i + 1] = 0; 310 if (!phys_avail[0]) 311 panic("pmap_steal_memory: out of memory"); 312 bank_size = phys_avail[1] - phys_avail[0]; 313 } 314 315 pa = phys_avail[0]; 316 phys_avail[0] += size; 317 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 318 panic("Out of memory below 512Meg?"); 319 } 320 va = MIPS_PHYS_TO_KSEG0(pa); 321 bzero((caddr_t)va, size); 322 return va; 323} 324 325/* 326 * Bootstrap the system enough to run with virtual memory. This 327 * assumes that the phys_avail array has been initialized. 328 */ 329void 330pmap_bootstrap(void) 331{ 332 pt_entry_t *pgtab; 333 pt_entry_t *pte; 334 int i, j; 335#if !defined(__mips_n64) 336 int memory_larger_than_512meg = 0; 337#endif 338 339 /* Sort. */ 340again: 341 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 342 /* 343 * Keep the memory aligned on page boundary. 344 */ 345 phys_avail[i] = round_page(phys_avail[i]); 346 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 347 348 if (i < 2) 349 continue; 350 if (phys_avail[i - 2] > phys_avail[i]) { 351 vm_paddr_t ptemp[2]; 352 353 ptemp[0] = phys_avail[i + 0]; 354 ptemp[1] = phys_avail[i + 1]; 355 356 phys_avail[i + 0] = phys_avail[i - 2]; 357 phys_avail[i + 1] = phys_avail[i - 1]; 358 359 phys_avail[i - 2] = ptemp[0]; 360 phys_avail[i - 1] = ptemp[1]; 361 goto again; 362 } 363 } 364 365#if !defined(__mips_n64) 366 if (phys_avail[i - 1] >= MIPS_KSEG0_LARGEST_PHYS) 367 memory_larger_than_512meg = 1; 368#endif 369 370 /* 371 * Copy the phys_avail[] array before we start stealing memory from it. 372 */ 373 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 374 physmem_desc[i] = phys_avail[i]; 375 physmem_desc[i + 1] = phys_avail[i + 1]; 376 } 377 378 Maxmem = atop(phys_avail[i - 1]); 379 380 if (bootverbose) { 381 printf("Physical memory chunk(s):\n"); 382 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 383 vm_paddr_t size; 384 385 size = phys_avail[i + 1] - phys_avail[i]; 386 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 387 (uintmax_t) phys_avail[i], 388 (uintmax_t) phys_avail[i + 1] - 1, 389 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 390 } 391 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 392 } 393 /* 394 * Steal the message buffer from the beginning of memory. 395 */ 396 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 397 msgbufinit(msgbufp, MSGBUF_SIZE); 398 399 /* 400 * Steal thread0 kstack. 401 */ 402 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 403 404 virtual_avail = VM_MIN_KERNEL_ADDRESS; 405 virtual_end = VM_MAX_KERNEL_ADDRESS; 406 407#ifdef SMP 408 /* 409 * Steal some virtual address space to map the pcpu area. 410 */ 411 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 412 pcpup = (struct pcpu *)virtual_avail; 413 virtual_avail += PAGE_SIZE * 2; 414 415 /* 416 * Initialize the wired TLB entry mapping the pcpu region for 417 * the BSP at 'pcpup'. Up until this point we were operating 418 * with the 'pcpup' for the BSP pointing to a virtual address 419 * in KSEG0 so there was no need for a TLB mapping. 420 */ 421 mips_pcpu_tlb_init(PCPU_ADDR(0)); 422 423 if (bootverbose) 424 printf("pcpu is available at virtual address %p.\n", pcpup); 425#endif 426 427#if !defined(__mips_n64) 428 /* 429 * Steal some virtual space that will not be in kernel_segmap. This 430 * va memory space will be used to map in kernel pages that are 431 * outside the 512Meg region. Note that we only do this steal when 432 * we do have memory in this region, that way for systems with 433 * smaller memory we don't "steal" any va ranges :-) 434 */ 435 if (memory_larger_than_512meg) { 436 for (i = 0; i < MAXCPU; i++) { 437 sysmap_lmem[i].base = virtual_avail; 438 virtual_avail += PAGE_SIZE * 2; 439 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 440 } 441 } 442#endif 443 444 /* 445 * Allocate segment table for the kernel 446 */ 447 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 448 449 /* 450 * Allocate second level page tables for the kernel 451 */ 452 nkpt = NKPT; 453#if !defined(__mips_n64) 454 if (memory_larger_than_512meg) { 455 /* 456 * If we have a large memory system we CANNOT afford to hit 457 * pmap_growkernel() and allocate memory. Since we MAY end 458 * up with a page that is NOT mappable. For that reason we 459 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 460 * this gives us 480meg of kernel virtual addresses at the 461 * cost of 120 pages (each page gets us 4 Meg). Since the 462 * kernel starts at virtual_avail, we can use this to 463 * calculate how many entris are left from there to the end 464 * of the segmap, we want to allocate all of it, which would 465 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 466 * in about 256 entries or so instead of the 120. 467 */ 468 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 469 } 470#endif 471 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 472 473 /* 474 * The R[4-7]?00 stores only one copy of the Global bit in the 475 * translation lookaside buffer for each 2 page entry. Thus invalid 476 * entrys must have the Global bit set so when Entry LO and Entry HI 477 * G bits are anded together they will produce a global bit to store 478 * in the tlb. 479 */ 480 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 481 *pte = PTE_G; 482 483 /* 484 * The segment table contains the KVA of the pages in the second 485 * level page table. 486 */ 487 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 488 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 489 490 /* 491 * The kernel's pmap is statically allocated so we don't have to use 492 * pmap_create, which is unlikely to work correctly at this part of 493 * the boot sequence (XXX and which no longer exists). 494 */ 495 PMAP_LOCK_INIT(kernel_pmap); 496 kernel_pmap->pm_segtab = kernel_segmap; 497 kernel_pmap->pm_active = ~0; 498 TAILQ_INIT(&kernel_pmap->pm_pvlist); 499 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 500 kernel_pmap->pm_asid[0].gen = 0; 501 pmap_max_asid = VMNUM_PIDS; 502 mips_wr_entryhi(0); 503} 504 505/* 506 * Initialize a vm_page's machine-dependent fields. 507 */ 508void 509pmap_page_init(vm_page_t m) 510{ 511 512 TAILQ_INIT(&m->md.pv_list); 513 m->md.pv_list_count = 0; 514 m->md.pv_flags = 0; 515} 516 517/* 518 * Initialize the pmap module. 519 * Called by vm_init, to initialize any structures that the pmap 520 * system needs to map virtual memory. 521 * pmap_init has been enhanced to support in a fairly consistant 522 * way, discontiguous physical memory. 523 */ 524void 525pmap_init(void) 526{ 527 528 /* 529 * Initialize the address space (zone) for the pv entries. Set a 530 * high water mark so that the system can recover from excessive 531 * numbers of pv entries. 532 */ 533 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 534 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 535 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 536 pv_entry_high_water = 9 * (pv_entry_max / 10); 537 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 538} 539 540/*************************************************** 541 * Low level helper routines..... 542 ***************************************************/ 543 544#if defined(PMAP_DIAGNOSTIC) 545 546/* 547 * This code checks for non-writeable/modified pages. 548 * This should be an invalid condition. 549 */ 550static int 551pmap_nw_modified(pt_entry_t pte) 552{ 553 if ((pte & (PTE_D | PTE_RO)) == (PTE_D | PTE_RO)) 554 return (1); 555 else 556 return (0); 557} 558 559#endif 560 561static void 562pmap_invalidate_all(pmap_t pmap) 563{ 564#ifdef SMP 565 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 566} 567 568static void 569pmap_invalidate_all_action(void *arg) 570{ 571 pmap_t pmap = (pmap_t)arg; 572 573#endif 574 575 if (pmap == kernel_pmap) { 576 tlb_invalidate_all(); 577 return; 578 } 579 580 if (pmap->pm_active & PCPU_GET(cpumask)) 581 tlb_invalidate_all_user(pmap); 582 else 583 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 584} 585 586struct pmap_invalidate_page_arg { 587 pmap_t pmap; 588 vm_offset_t va; 589}; 590 591static __inline void 592pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 593{ 594#ifdef SMP 595 struct pmap_invalidate_page_arg arg; 596 597 arg.pmap = pmap; 598 arg.va = va; 599 600 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 601} 602 603static void 604pmap_invalidate_page_action(void *arg) 605{ 606 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 607 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 608 609#endif 610 611 if (is_kernel_pmap(pmap)) { 612 tlb_invalidate_address(pmap, va); 613 return; 614 } 615 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 616 return; 617 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 618 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 619 return; 620 } 621 tlb_invalidate_address(pmap, va); 622} 623 624struct pmap_update_page_arg { 625 pmap_t pmap; 626 vm_offset_t va; 627 pt_entry_t pte; 628}; 629 630void 631pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 632{ 633#ifdef SMP 634 struct pmap_update_page_arg arg; 635 636 arg.pmap = pmap; 637 arg.va = va; 638 arg.pte = pte; 639 640 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 641} 642 643static void 644pmap_update_page_action(void *arg) 645{ 646 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 647 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 648 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 649 650#endif 651 if (is_kernel_pmap(pmap)) { 652 tlb_update(pmap, va, pte); 653 return; 654 } 655 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 656 return; 657 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 658 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 659 return; 660 } 661 tlb_update(pmap, va, pte); 662} 663 664/* 665 * Routine: pmap_extract 666 * Function: 667 * Extract the physical page address associated 668 * with the given map/virtual_address pair. 669 */ 670vm_paddr_t 671pmap_extract(pmap_t pmap, vm_offset_t va) 672{ 673 pt_entry_t *pte; 674 vm_offset_t retval = 0; 675 676 PMAP_LOCK(pmap); 677 pte = pmap_pte(pmap, va); 678 if (pte) { 679 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK); 680 } 681 PMAP_UNLOCK(pmap); 682 return retval; 683} 684 685/* 686 * Routine: pmap_extract_and_hold 687 * Function: 688 * Atomically extract and hold the physical page 689 * with the given pmap and virtual address pair 690 * if that mapping permits the given protection. 691 */ 692vm_page_t 693pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 694{ 695 pt_entry_t pte; 696 vm_page_t m; 697 vm_paddr_t pa; 698 699 m = NULL; 700 pa = 0; 701 PMAP_LOCK(pmap); 702retry: 703 pte = *pmap_pte(pmap, va); 704 if (pte != 0 && pte_test(&pte, PTE_V) && 705 (pte_test(&pte, PTE_D) || (prot & VM_PROT_WRITE) == 0)) { 706 if (vm_page_pa_tryrelock(pmap, TLBLO_PTE_TO_PA(pte), &pa)) 707 goto retry; 708 709 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(pte)); 710 vm_page_hold(m); 711 } 712 PA_UNLOCK_COND(pa); 713 PMAP_UNLOCK(pmap); 714 return (m); 715} 716 717/*************************************************** 718 * Low level mapping routines..... 719 ***************************************************/ 720 721/* 722 * add a wired page to the kva 723 */ 724 /* PMAP_INLINE */ void 725pmap_kenter(vm_offset_t va, vm_paddr_t pa) 726{ 727 pt_entry_t *pte; 728 pt_entry_t opte, npte; 729 730#ifdef PMAP_DEBUG 731 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 732#endif 733 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | PTE_W; 734 735 if (is_cacheable_mem(pa)) 736 npte |= PTE_C_CACHE; 737 else 738 npte |= PTE_C_UNCACHED; 739 740 pte = pmap_pte(kernel_pmap, va); 741 opte = *pte; 742 *pte = npte; 743 744 pmap_update_page(kernel_pmap, va, npte); 745} 746 747/* 748 * remove a page from the kernel pagetables 749 */ 750 /* PMAP_INLINE */ void 751pmap_kremove(vm_offset_t va) 752{ 753 pt_entry_t *pte; 754 755 /* 756 * Write back all caches from the page being destroyed 757 */ 758 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 759 760 pte = pmap_pte(kernel_pmap, va); 761 *pte = PTE_G; 762 pmap_invalidate_page(kernel_pmap, va); 763} 764 765/* 766 * Used to map a range of physical addresses into kernel 767 * virtual address space. 768 * 769 * The value passed in '*virt' is a suggested virtual address for 770 * the mapping. Architectures which can support a direct-mapped 771 * physical to virtual region can return the appropriate address 772 * within that region, leaving '*virt' unchanged. Other 773 * architectures should map the pages starting at '*virt' and 774 * update '*virt' with the first usable address after the mapped 775 * region. 776 * 777 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 778 */ 779#if defined(__mips_n64) 780vm_offset_t 781pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 782{ 783 return (MIPS_PHYS_TO_XKPHYS_CACHED(start)); 784} 785#else 786vm_offset_t 787pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 788{ 789 vm_offset_t va, sva; 790 791 if (end <= MIPS_KSEG0_LARGEST_PHYS) 792 return (MIPS_PHYS_TO_KSEG0(start)); 793 794 va = sva = *virt; 795 while (start < end) { 796 pmap_kenter(va, start); 797 va += PAGE_SIZE; 798 start += PAGE_SIZE; 799 } 800 *virt = va; 801 return (sva); 802} 803#endif 804 805/* 806 * Add a list of wired pages to the kva 807 * this routine is only used for temporary 808 * kernel mappings that do not need to have 809 * page modification or references recorded. 810 * Note that old mappings are simply written 811 * over. The page *must* be wired. 812 */ 813void 814pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 815{ 816 int i; 817 vm_offset_t origva = va; 818 819 for (i = 0; i < count; i++) { 820 pmap_flush_pvcache(m[i]); 821 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 822 va += PAGE_SIZE; 823 } 824 825 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 826} 827 828/* 829 * this routine jerks page mappings from the 830 * kernel -- it is meant only for temporary mappings. 831 */ 832void 833pmap_qremove(vm_offset_t va, int count) 834{ 835 /* 836 * No need to wb/inv caches here, 837 * pmap_kremove will do it for us 838 */ 839 840 while (count-- > 0) { 841 pmap_kremove(va); 842 va += PAGE_SIZE; 843 } 844} 845 846/*************************************************** 847 * Page table page management routines..... 848 ***************************************************/ 849 850/* Revision 1.507 851 * 852 * Simplify the reference counting of page table pages. Specifically, use 853 * the page table page's wired count rather than its hold count to contain 854 * the reference count. 855 */ 856 857/* 858 * This routine unholds page table pages, and if the hold count 859 * drops to zero, then it decrements the wire count. 860 */ 861static int 862_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 863{ 864 865 /* 866 * unmap the page table page 867 */ 868 pmap->pm_segtab[m->pindex] = 0; 869 --pmap->pm_stats.resident_count; 870 871 if (pmap->pm_ptphint == m) 872 pmap->pm_ptphint = NULL; 873 874 /* 875 * If the page is finally unwired, simply free it. 876 */ 877 vm_page_free_zero(m); 878 atomic_subtract_int(&cnt.v_wire_count, 1); 879 return (1); 880} 881 882static PMAP_INLINE int 883pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 884{ 885 --m->wire_count; 886 if (m->wire_count == 0) 887 return (_pmap_unwire_pte_hold(pmap, m)); 888 else 889 return (0); 890} 891 892/* 893 * After removing a page table entry, this routine is used to 894 * conditionally free the page, and manage the hold/wire counts. 895 */ 896static int 897pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 898{ 899 unsigned ptepindex; 900 pd_entry_t pteva; 901 902 if (va >= VM_MAXUSER_ADDRESS) 903 return (0); 904 905 if (mpte == NULL) { 906 ptepindex = pmap_segshift(va); 907 if (pmap->pm_ptphint && 908 (pmap->pm_ptphint->pindex == ptepindex)) { 909 mpte = pmap->pm_ptphint; 910 } else { 911 pteva = pmap_segmap(pmap, va); 912 mpte = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 913 pmap->pm_ptphint = mpte; 914 } 915 } 916 return pmap_unwire_pte_hold(pmap, mpte); 917} 918 919void 920pmap_pinit0(pmap_t pmap) 921{ 922 int i; 923 924 PMAP_LOCK_INIT(pmap); 925 pmap->pm_segtab = kernel_segmap; 926 pmap->pm_active = 0; 927 pmap->pm_ptphint = NULL; 928 for (i = 0; i < MAXCPU; i++) { 929 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 930 pmap->pm_asid[i].gen = 0; 931 } 932 PCPU_SET(curpmap, pmap); 933 TAILQ_INIT(&pmap->pm_pvlist); 934 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 935} 936 937static void 938pmap_grow_pte_page_cache() 939{ 940 941 vm_contig_grow_cache(3, 0, MIPS_KSEG0_LARGEST_PHYS); 942} 943 944static vm_page_t 945pmap_alloc_pte_page(unsigned int index, int req) 946{ 947 vm_page_t m; 948 949 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, 0, req); 950 if (m == NULL) 951 return (NULL); 952 953 if ((m->flags & PG_ZERO) == 0) 954 pmap_zero_page(m); 955 956 m->pindex = index; 957 atomic_add_int(&cnt.v_wire_count, 1); 958 m->wire_count = 1; 959 return (m); 960} 961 962/* 963 * Initialize a preallocated and zeroed pmap structure, 964 * such as one in a vmspace structure. 965 */ 966int 967pmap_pinit(pmap_t pmap) 968{ 969 vm_offset_t ptdva; 970 vm_page_t ptdpg; 971 int i; 972 973 PMAP_LOCK_INIT(pmap); 974 975 /* 976 * allocate the page directory page 977 */ 978 while ((ptdpg = pmap_alloc_pte_page(NUSERPGTBLS, VM_ALLOC_NORMAL)) == NULL) 979 pmap_grow_pte_page_cache(); 980 981 ptdva = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(ptdpg)); 982 pmap->pm_segtab = (pd_entry_t *)ptdva; 983 pmap->pm_active = 0; 984 pmap->pm_ptphint = NULL; 985 for (i = 0; i < MAXCPU; i++) { 986 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 987 pmap->pm_asid[i].gen = 0; 988 } 989 TAILQ_INIT(&pmap->pm_pvlist); 990 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 991 992 return (1); 993} 994 995/* 996 * this routine is called if the page table page is not 997 * mapped correctly. 998 */ 999static vm_page_t 1000_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1001{ 1002 vm_offset_t pteva; 1003 vm_page_t m; 1004 1005 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1006 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1007 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1008 1009 /* 1010 * Find or fabricate a new pagetable page 1011 */ 1012 if ((m = pmap_alloc_pte_page(ptepindex, VM_ALLOC_NORMAL)) == NULL) { 1013 if (flags & M_WAITOK) { 1014 PMAP_UNLOCK(pmap); 1015 vm_page_unlock_queues(); 1016 pmap_grow_pte_page_cache(); 1017 vm_page_lock_queues(); 1018 PMAP_LOCK(pmap); 1019 } 1020 1021 /* 1022 * Indicate the need to retry. While waiting, the page 1023 * table page may have been allocated. 1024 */ 1025 return (NULL); 1026 } 1027 1028 /* 1029 * Map the pagetable page into the process address space, if it 1030 * isn't already there. 1031 */ 1032 1033 pteva = MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(m)); 1034 pmap->pm_stats.resident_count++; 1035 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1036 1037 /* 1038 * Set the page table hint 1039 */ 1040 pmap->pm_ptphint = m; 1041 return (m); 1042} 1043 1044static vm_page_t 1045pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1046{ 1047 unsigned ptepindex; 1048 vm_offset_t pteva; 1049 vm_page_t m; 1050 1051 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1052 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1053 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1054 1055 /* 1056 * Calculate pagetable page index 1057 */ 1058 ptepindex = pmap_segshift(va); 1059retry: 1060 /* 1061 * Get the page directory entry 1062 */ 1063 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1064 1065 /* 1066 * If the page table page is mapped, we just increment the hold 1067 * count, and activate it. 1068 */ 1069 if (pteva) { 1070 /* 1071 * In order to get the page table page, try the hint first. 1072 */ 1073 if (pmap->pm_ptphint && 1074 (pmap->pm_ptphint->pindex == ptepindex)) { 1075 m = pmap->pm_ptphint; 1076 } else { 1077 m = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 1078 pmap->pm_ptphint = m; 1079 } 1080 m->wire_count++; 1081 } else { 1082 /* 1083 * Here if the pte page isn't mapped, or if it has been 1084 * deallocated. 1085 */ 1086 m = _pmap_allocpte(pmap, ptepindex, flags); 1087 if (m == NULL && (flags & M_WAITOK)) 1088 goto retry; 1089 } 1090 return m; 1091} 1092 1093 1094/*************************************************** 1095* Pmap allocation/deallocation routines. 1096 ***************************************************/ 1097/* 1098 * Revision 1.397 1099 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1100 * called only the page directory page(s) can be left in the pmap pte 1101 * object, since all page table pages will have been freed by 1102 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1103 * reference to the pmap and the page directory is wired, so the page(s) 1104 * can never be busy. So all there is to do is clear the magic mappings 1105 * from the page directory and free the page(s). 1106 */ 1107 1108 1109/* 1110 * Release any resources held by the given physical map. 1111 * Called when a pmap initialized by pmap_pinit is being released. 1112 * Should only be called if the map contains no valid mappings. 1113 */ 1114void 1115pmap_release(pmap_t pmap) 1116{ 1117 vm_offset_t ptdva; 1118 vm_page_t ptdpg; 1119 1120 KASSERT(pmap->pm_stats.resident_count == 0, 1121 ("pmap_release: pmap resident count %ld != 0", 1122 pmap->pm_stats.resident_count)); 1123 1124 ptdva = (vm_offset_t)pmap->pm_segtab; 1125 ptdpg = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(ptdva)); 1126 1127 ptdpg->wire_count--; 1128 atomic_subtract_int(&cnt.v_wire_count, 1); 1129 vm_page_free_zero(ptdpg); 1130 PMAP_LOCK_DESTROY(pmap); 1131} 1132 1133/* 1134 * grow the number of kernel page table entries, if needed 1135 */ 1136void 1137pmap_growkernel(vm_offset_t addr) 1138{ 1139 vm_page_t nkpg; 1140 pt_entry_t *pte; 1141 int i; 1142 1143 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1144 if (kernel_vm_end == 0) { 1145 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1146 nkpt = 0; 1147 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1148 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1149 ~(PAGE_SIZE * NPTEPG - 1); 1150 nkpt++; 1151 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1152 kernel_vm_end = kernel_map->max_offset; 1153 break; 1154 } 1155 } 1156 } 1157 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1158 if (addr - 1 >= kernel_map->max_offset) 1159 addr = kernel_map->max_offset; 1160 while (kernel_vm_end < addr) { 1161 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1162 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1163 ~(PAGE_SIZE * NPTEPG - 1); 1164 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1165 kernel_vm_end = kernel_map->max_offset; 1166 break; 1167 } 1168 continue; 1169 } 1170 /* 1171 * This index is bogus, but out of the way 1172 */ 1173 nkpg = pmap_alloc_pte_page(nkpt, VM_ALLOC_INTERRUPT); 1174 if (!nkpg) 1175 panic("pmap_growkernel: no memory to grow kernel"); 1176 1177 nkpt++; 1178 pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(VM_PAGE_TO_PHYS(nkpg)); 1179 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1180 1181 /* 1182 * The R[4-7]?00 stores only one copy of the Global bit in 1183 * the translation lookaside buffer for each 2 page entry. 1184 * Thus invalid entrys must have the Global bit set so when 1185 * Entry LO and Entry HI G bits are anded together they will 1186 * produce a global bit to store in the tlb. 1187 */ 1188 for (i = 0; i < NPTEPG; i++, pte++) 1189 *pte = PTE_G; 1190 1191 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1192 ~(PAGE_SIZE * NPTEPG - 1); 1193 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1194 kernel_vm_end = kernel_map->max_offset; 1195 break; 1196 } 1197 } 1198} 1199 1200/*************************************************** 1201* page management routines. 1202 ***************************************************/ 1203 1204/* 1205 * free the pv_entry back to the free list 1206 */ 1207static PMAP_INLINE void 1208free_pv_entry(pv_entry_t pv) 1209{ 1210 1211 pv_entry_count--; 1212 uma_zfree(pvzone, pv); 1213} 1214 1215/* 1216 * get a new pv_entry, allocating a block from the system 1217 * when needed. 1218 * the memory allocation is performed bypassing the malloc code 1219 * because of the possibility of allocations at interrupt time. 1220 */ 1221static pv_entry_t 1222get_pv_entry(pmap_t locked_pmap) 1223{ 1224 static const struct timeval printinterval = { 60, 0 }; 1225 static struct timeval lastprint; 1226 struct vpgqueues *vpq; 1227 pt_entry_t *pte, oldpte; 1228 pmap_t pmap; 1229 pv_entry_t allocated_pv, next_pv, pv; 1230 vm_offset_t va; 1231 vm_page_t m; 1232 1233 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1234 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1235 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1236 if (allocated_pv != NULL) { 1237 pv_entry_count++; 1238 if (pv_entry_count > pv_entry_high_water) 1239 pagedaemon_wakeup(); 1240 else 1241 return (allocated_pv); 1242 } 1243 /* 1244 * Reclaim pv entries: At first, destroy mappings to inactive 1245 * pages. After that, if a pv entry is still needed, destroy 1246 * mappings to active pages. 1247 */ 1248 if (ratecheck(&lastprint, &printinterval)) 1249 printf("Approaching the limit on PV entries, " 1250 "increase the vm.pmap.shpgperproc tunable.\n"); 1251 vpq = &vm_page_queues[PQ_INACTIVE]; 1252retry: 1253 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1254 if (m->hold_count || m->busy) 1255 continue; 1256 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1257 va = pv->pv_va; 1258 pmap = pv->pv_pmap; 1259 /* Avoid deadlock and lock recursion. */ 1260 if (pmap > locked_pmap) 1261 PMAP_LOCK(pmap); 1262 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1263 continue; 1264 pmap->pm_stats.resident_count--; 1265 pte = pmap_pte(pmap, va); 1266 KASSERT(pte != NULL, ("pte")); 1267 oldpte = loadandclear((u_int *)pte); 1268 if (is_kernel_pmap(pmap)) 1269 *pte = PTE_G; 1270 KASSERT(!pte_test(&oldpte, PTE_W), 1271 ("wired pte for unwired page")); 1272 if (m->md.pv_flags & PV_TABLE_REF) 1273 vm_page_flag_set(m, PG_REFERENCED); 1274 if (pte_test(&oldpte, PTE_D)) 1275 vm_page_dirty(m); 1276 pmap_invalidate_page(pmap, va); 1277 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1278 m->md.pv_list_count--; 1279 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1280 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1281 if (pmap != locked_pmap) 1282 PMAP_UNLOCK(pmap); 1283 if (allocated_pv == NULL) 1284 allocated_pv = pv; 1285 else 1286 free_pv_entry(pv); 1287 } 1288 if (TAILQ_EMPTY(&m->md.pv_list)) { 1289 vm_page_flag_clear(m, PG_WRITEABLE); 1290 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1291 } 1292 } 1293 if (allocated_pv == NULL) { 1294 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1295 vpq = &vm_page_queues[PQ_ACTIVE]; 1296 goto retry; 1297 } 1298 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1299 } 1300 return (allocated_pv); 1301} 1302 1303/* 1304 * Revision 1.370 1305 * 1306 * Move pmap_collect() out of the machine-dependent code, rename it 1307 * to reflect its new location, and add page queue and flag locking. 1308 * 1309 * Notes: (1) alpha, i386, and ia64 had identical implementations 1310 * of pmap_collect() in terms of machine-independent interfaces; 1311 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1312 * 1313 * MIPS implementation was identical to alpha [Junos 8.2] 1314 */ 1315 1316/* 1317 * If it is the first entry on the list, it is actually 1318 * in the header and we must copy the following entry up 1319 * to the header. Otherwise we must search the list for 1320 * the entry. In either case we free the now unused entry. 1321 */ 1322 1323static pv_entry_t 1324pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1325{ 1326 pv_entry_t pv; 1327 1328 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1329 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1330 if (pvh->pv_list_count < pmap->pm_stats.resident_count) { 1331 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 1332 if (pmap == pv->pv_pmap && va == pv->pv_va) 1333 break; 1334 } 1335 } else { 1336 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1337 if (va == pv->pv_va) 1338 break; 1339 } 1340 } 1341 if (pv != NULL) { 1342 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 1343 pvh->pv_list_count--; 1344 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1345 } 1346 return (pv); 1347} 1348 1349static void 1350pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1351{ 1352 pv_entry_t pv; 1353 1354 pv = pmap_pvh_remove(pvh, pmap, va); 1355 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx", 1356 (u_long)VM_PAGE_TO_PHYS(member2struct(vm_page, md, pvh)), 1357 (u_long)va)); 1358 free_pv_entry(pv); 1359} 1360 1361static void 1362pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1363{ 1364 1365 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1366 pmap_pvh_free(&m->md, pmap, va); 1367 if (TAILQ_EMPTY(&m->md.pv_list)) 1368 vm_page_flag_clear(m, PG_WRITEABLE); 1369} 1370 1371/* 1372 * Conditionally create a pv entry. 1373 */ 1374static boolean_t 1375pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1376 vm_page_t m) 1377{ 1378 pv_entry_t pv; 1379 1380 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1381 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1382 if (pv_entry_count < pv_entry_high_water && 1383 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1384 pv_entry_count++; 1385 pv->pv_va = va; 1386 pv->pv_pmap = pmap; 1387 pv->pv_ptem = mpte; 1388 pv->pv_wired = FALSE; 1389 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1390 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1391 m->md.pv_list_count++; 1392 return (TRUE); 1393 } else 1394 return (FALSE); 1395} 1396 1397/* 1398 * pmap_remove_pte: do the things to unmap a page in a process 1399 */ 1400static int 1401pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1402{ 1403 pt_entry_t oldpte; 1404 vm_page_t m; 1405 vm_offset_t pa; 1406 1407 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1408 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1409 1410 oldpte = loadandclear((u_int *)ptq); 1411 if (is_kernel_pmap(pmap)) 1412 *ptq = PTE_G; 1413 1414 if (pte_test(&oldpte, PTE_W)) 1415 pmap->pm_stats.wired_count -= 1; 1416 1417 pmap->pm_stats.resident_count -= 1; 1418 pa = TLBLO_PTE_TO_PA(oldpte); 1419 1420 if (page_is_managed(pa)) { 1421 m = PHYS_TO_VM_PAGE(pa); 1422 if (pte_test(&oldpte, PTE_D)) { 1423#if defined(PMAP_DIAGNOSTIC) 1424 if (pmap_nw_modified(oldpte)) { 1425 printf( 1426 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1427 va, oldpte); 1428 } 1429#endif 1430 vm_page_dirty(m); 1431 } 1432 if (m->md.pv_flags & PV_TABLE_REF) 1433 vm_page_flag_set(m, PG_REFERENCED); 1434 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1435 1436 pmap_remove_entry(pmap, m, va); 1437 } 1438 return pmap_unuse_pt(pmap, va, NULL); 1439} 1440 1441/* 1442 * Remove a single page from a process address space 1443 */ 1444static void 1445pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1446{ 1447 pt_entry_t *ptq; 1448 1449 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1450 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1451 ptq = pmap_pte(pmap, va); 1452 1453 /* 1454 * if there is no pte for this address, just skip it!!! 1455 */ 1456 if (!ptq || !pte_test(ptq, PTE_V)) { 1457 return; 1458 } 1459 1460 /* 1461 * Write back all caches from the page being destroyed 1462 */ 1463 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1464 1465 /* 1466 * get a local va for mappings for this pmap. 1467 */ 1468 (void)pmap_remove_pte(pmap, ptq, va); 1469 pmap_invalidate_page(pmap, va); 1470 1471 return; 1472} 1473 1474/* 1475 * Remove the given range of addresses from the specified map. 1476 * 1477 * It is assumed that the start and end are properly 1478 * rounded to the page size. 1479 */ 1480void 1481pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1482{ 1483 vm_offset_t va, nva; 1484 1485 if (pmap == NULL) 1486 return; 1487 1488 if (pmap->pm_stats.resident_count == 0) 1489 return; 1490 1491 vm_page_lock_queues(); 1492 PMAP_LOCK(pmap); 1493 1494 /* 1495 * special handling of removing one page. a very common operation 1496 * and easy to short circuit some code. 1497 */ 1498 if ((sva + PAGE_SIZE) == eva) { 1499 pmap_remove_page(pmap, sva); 1500 goto out; 1501 } 1502 for (va = sva; va < eva; va = nva) { 1503 if (pmap_segmap(pmap, va) == NULL) { 1504 nva = mips_segtrunc(va + NBSEG); 1505 continue; 1506 } 1507 pmap_remove_page(pmap, va); 1508 nva = va + PAGE_SIZE; 1509 } 1510 1511out: 1512 vm_page_unlock_queues(); 1513 PMAP_UNLOCK(pmap); 1514} 1515 1516/* 1517 * Routine: pmap_remove_all 1518 * Function: 1519 * Removes this physical page from 1520 * all physical maps in which it resides. 1521 * Reflects back modify bits to the pager. 1522 * 1523 * Notes: 1524 * Original versions of this routine were very 1525 * inefficient because they iteratively called 1526 * pmap_remove (slow...) 1527 */ 1528 1529void 1530pmap_remove_all(vm_page_t m) 1531{ 1532 pv_entry_t pv; 1533 pt_entry_t *pte, tpte; 1534 1535 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1536 ("pmap_remove_all: page %p is fictitious", m)); 1537 vm_page_lock_queues(); 1538 1539 if (m->md.pv_flags & PV_TABLE_REF) 1540 vm_page_flag_set(m, PG_REFERENCED); 1541 1542 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1543 PMAP_LOCK(pv->pv_pmap); 1544 1545 /* 1546 * If it's last mapping writeback all caches from 1547 * the page being destroyed 1548 */ 1549 if (m->md.pv_list_count == 1) 1550 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1551 1552 pv->pv_pmap->pm_stats.resident_count--; 1553 1554 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1555 1556 tpte = loadandclear((u_int *)pte); 1557 if (is_kernel_pmap(pv->pv_pmap)) 1558 *pte = PTE_G; 1559 1560 if (pte_test(&tpte, PTE_W)) 1561 pv->pv_pmap->pm_stats.wired_count--; 1562 1563 /* 1564 * Update the vm_page_t clean and reference bits. 1565 */ 1566 if (pte_test(&tpte, PTE_D)) { 1567#if defined(PMAP_DIAGNOSTIC) 1568 if (pmap_nw_modified(tpte)) { 1569 printf( 1570 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1571 pv->pv_va, tpte); 1572 } 1573#endif 1574 vm_page_dirty(m); 1575 } 1576 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1577 1578 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1579 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1580 m->md.pv_list_count--; 1581 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1582 PMAP_UNLOCK(pv->pv_pmap); 1583 free_pv_entry(pv); 1584 } 1585 1586 vm_page_flag_clear(m, PG_WRITEABLE); 1587 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1588 vm_page_unlock_queues(); 1589} 1590 1591/* 1592 * Set the physical protection on the 1593 * specified range of this map as requested. 1594 */ 1595void 1596pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1597{ 1598 pt_entry_t *pte; 1599 1600 if (pmap == NULL) 1601 return; 1602 1603 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1604 pmap_remove(pmap, sva, eva); 1605 return; 1606 } 1607 if (prot & VM_PROT_WRITE) 1608 return; 1609 1610 vm_page_lock_queues(); 1611 PMAP_LOCK(pmap); 1612 while (sva < eva) { 1613 pt_entry_t pbits, obits; 1614 vm_page_t m; 1615 vm_offset_t pa; 1616 1617 /* 1618 * If segment table entry is empty, skip this segment. 1619 */ 1620 if (pmap_segmap(pmap, sva) == NULL) { 1621 sva = mips_segtrunc(sva + NBSEG); 1622 continue; 1623 } 1624 /* 1625 * If pte is invalid, skip this page 1626 */ 1627 pte = pmap_pte(pmap, sva); 1628 if (!pte_test(pte, PTE_V)) { 1629 sva += PAGE_SIZE; 1630 continue; 1631 } 1632retry: 1633 obits = pbits = *pte; 1634 pa = TLBLO_PTE_TO_PA(pbits); 1635 1636 if (page_is_managed(pa) && pte_test(&pbits, PTE_D)) { 1637 m = PHYS_TO_VM_PAGE(pa); 1638 vm_page_dirty(m); 1639 m->md.pv_flags &= ~PV_TABLE_MOD; 1640 } 1641 pte_clear(&pbits, PTE_D); 1642 pte_set(&pbits, PTE_RO); 1643 1644 if (pbits != *pte) { 1645 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1646 goto retry; 1647 pmap_update_page(pmap, sva, pbits); 1648 } 1649 sva += PAGE_SIZE; 1650 } 1651 vm_page_unlock_queues(); 1652 PMAP_UNLOCK(pmap); 1653} 1654 1655/* 1656 * Insert the given physical page (p) at 1657 * the specified virtual address (v) in the 1658 * target physical map with the protection requested. 1659 * 1660 * If specified, the page will be wired down, meaning 1661 * that the related pte can not be reclaimed. 1662 * 1663 * NB: This is the only routine which MAY NOT lazy-evaluate 1664 * or lose information. That is, this routine must actually 1665 * insert this page into the given map NOW. 1666 */ 1667void 1668pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1669 vm_prot_t prot, boolean_t wired) 1670{ 1671 vm_offset_t pa, opa; 1672 pt_entry_t *pte; 1673 pt_entry_t origpte, newpte; 1674 pv_entry_t pv; 1675 vm_page_t mpte, om; 1676 int rw = 0; 1677 1678 if (pmap == NULL) 1679 return; 1680 1681 va &= ~PAGE_MASK; 1682 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 1683 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1684 (m->oflags & VPO_BUSY) != 0, 1685 ("pmap_enter: page %p is not busy", m)); 1686 1687 mpte = NULL; 1688 1689 vm_page_lock_queues(); 1690 PMAP_LOCK(pmap); 1691 1692 /* 1693 * In the case that a page table page is not resident, we are 1694 * creating it here. 1695 */ 1696 if (va < VM_MAXUSER_ADDRESS) { 1697 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1698 } 1699 pte = pmap_pte(pmap, va); 1700 1701 /* 1702 * Page Directory table entry not valid, we need a new PT page 1703 */ 1704 if (pte == NULL) { 1705 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1706 (void *)pmap->pm_segtab, (void *)va); 1707 } 1708 pa = VM_PAGE_TO_PHYS(m); 1709 om = NULL; 1710 origpte = *pte; 1711 opa = TLBLO_PTE_TO_PA(origpte); 1712 1713 /* 1714 * Mapping has not changed, must be protection or wiring change. 1715 */ 1716 if (pte_test(&origpte, PTE_V) && opa == pa) { 1717 /* 1718 * Wiring change, just update stats. We don't worry about 1719 * wiring PT pages as they remain resident as long as there 1720 * are valid mappings in them. Hence, if a user page is 1721 * wired, the PT page will be also. 1722 */ 1723 if (wired && !pte_test(&origpte, PTE_W)) 1724 pmap->pm_stats.wired_count++; 1725 else if (!wired && pte_test(&origpte, PTE_W)) 1726 pmap->pm_stats.wired_count--; 1727 1728#if defined(PMAP_DIAGNOSTIC) 1729 if (pmap_nw_modified(origpte)) { 1730 printf( 1731 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1732 va, origpte); 1733 } 1734#endif 1735 1736 /* 1737 * Remove extra pte reference 1738 */ 1739 if (mpte) 1740 mpte->wire_count--; 1741 1742 if (page_is_managed(opa)) { 1743 om = m; 1744 } 1745 goto validate; 1746 } 1747 1748 pv = NULL; 1749 1750 /* 1751 * Mapping has changed, invalidate old range and fall through to 1752 * handle validating new mapping. 1753 */ 1754 if (opa) { 1755 if (pte_test(&origpte, PTE_W)) 1756 pmap->pm_stats.wired_count--; 1757 1758 if (page_is_managed(opa)) { 1759 om = PHYS_TO_VM_PAGE(opa); 1760 pv = pmap_pvh_remove(&om->md, pmap, va); 1761 } 1762 if (mpte != NULL) { 1763 mpte->wire_count--; 1764 KASSERT(mpte->wire_count > 0, 1765 ("pmap_enter: missing reference to page table page," 1766 " va: %p", (void *)va)); 1767 } 1768 } else 1769 pmap->pm_stats.resident_count++; 1770 1771 /* 1772 * Enter on the PV list if part of our managed memory. Note that we 1773 * raise IPL while manipulating pv_table since pmap_enter can be 1774 * called at interrupt time. 1775 */ 1776 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1777 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1778 ("pmap_enter: managed mapping within the clean submap")); 1779 if (pv == NULL) 1780 pv = get_pv_entry(pmap); 1781 pv->pv_va = va; 1782 pv->pv_pmap = pmap; 1783 pv->pv_ptem = mpte; 1784 pv->pv_wired = wired; 1785 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1786 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1787 m->md.pv_list_count++; 1788 } else if (pv != NULL) 1789 free_pv_entry(pv); 1790 1791 /* 1792 * Increment counters 1793 */ 1794 if (wired) 1795 pmap->pm_stats.wired_count++; 1796 1797validate: 1798 if ((access & VM_PROT_WRITE) != 0) 1799 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1800 rw = init_pte_prot(va, m, prot); 1801 1802#ifdef PMAP_DEBUG 1803 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 1804#endif 1805 /* 1806 * Now validate mapping with desired protection/wiring. 1807 */ 1808 newpte = TLBLO_PA_TO_PFN(pa) | rw | PTE_V; 1809 1810 if (is_cacheable_mem(pa)) 1811 newpte |= PTE_C_CACHE; 1812 else 1813 newpte |= PTE_C_UNCACHED; 1814 1815 if (wired) 1816 newpte |= PTE_W; 1817 1818 if (is_kernel_pmap(pmap)) 1819 newpte |= PTE_G; 1820 1821 /* 1822 * if the mapping or permission bits are different, we need to 1823 * update the pte. 1824 */ 1825 if (origpte != newpte) { 1826 if (pte_test(&origpte, PTE_V)) { 1827 *pte = newpte; 1828 if (page_is_managed(opa) && (opa != pa)) { 1829 if (om->md.pv_flags & PV_TABLE_REF) 1830 vm_page_flag_set(om, PG_REFERENCED); 1831 om->md.pv_flags &= 1832 ~(PV_TABLE_REF | PV_TABLE_MOD); 1833 } 1834 if (pte_test(&origpte, PTE_D)) { 1835 KASSERT(!pte_test(&origpte, PTE_RO), 1836 ("pmap_enter: modified page not writable:" 1837 " va: %p, pte: 0x%x", (void *)va, origpte)); 1838 if (page_is_managed(opa)) 1839 vm_page_dirty(om); 1840 } 1841 if (page_is_managed(opa) && 1842 TAILQ_EMPTY(&om->md.pv_list)) 1843 vm_page_flag_clear(om, PG_WRITEABLE); 1844 } else { 1845 *pte = newpte; 1846 } 1847 } 1848 pmap_update_page(pmap, va, newpte); 1849 1850 /* 1851 * Sync I & D caches for executable pages. Do this only if the the 1852 * target pmap belongs to the current process. Otherwise, an 1853 * unresolvable TLB miss may occur. 1854 */ 1855 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1856 (prot & VM_PROT_EXECUTE)) { 1857 mips_icache_sync_range(va, PAGE_SIZE); 1858 mips_dcache_wbinv_range(va, PAGE_SIZE); 1859 } 1860 vm_page_unlock_queues(); 1861 PMAP_UNLOCK(pmap); 1862} 1863 1864/* 1865 * this code makes some *MAJOR* assumptions: 1866 * 1. Current pmap & pmap exists. 1867 * 2. Not wired. 1868 * 3. Read access. 1869 * 4. No page table pages. 1870 * but is *MUCH* faster than pmap_enter... 1871 */ 1872 1873void 1874pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1875{ 1876 1877 vm_page_lock_queues(); 1878 PMAP_LOCK(pmap); 1879 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1880 vm_page_unlock_queues(); 1881 PMAP_UNLOCK(pmap); 1882} 1883 1884static vm_page_t 1885pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1886 vm_prot_t prot, vm_page_t mpte) 1887{ 1888 pt_entry_t *pte; 1889 vm_offset_t pa; 1890 1891 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1892 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1893 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1894 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1895 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1896 1897 /* 1898 * In the case that a page table page is not resident, we are 1899 * creating it here. 1900 */ 1901 if (va < VM_MAXUSER_ADDRESS) { 1902 unsigned ptepindex; 1903 vm_offset_t pteva; 1904 1905 /* 1906 * Calculate pagetable page index 1907 */ 1908 ptepindex = pmap_segshift(va); 1909 if (mpte && (mpte->pindex == ptepindex)) { 1910 mpte->wire_count++; 1911 } else { 1912 /* 1913 * Get the page directory entry 1914 */ 1915 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1916 1917 /* 1918 * If the page table page is mapped, we just 1919 * increment the hold count, and activate it. 1920 */ 1921 if (pteva) { 1922 if (pmap->pm_ptphint && 1923 (pmap->pm_ptphint->pindex == ptepindex)) { 1924 mpte = pmap->pm_ptphint; 1925 } else { 1926 mpte = PHYS_TO_VM_PAGE( 1927 MIPS_KSEG0_TO_PHYS(pteva)); 1928 pmap->pm_ptphint = mpte; 1929 } 1930 mpte->wire_count++; 1931 } else { 1932 mpte = _pmap_allocpte(pmap, ptepindex, 1933 M_NOWAIT); 1934 if (mpte == NULL) 1935 return (mpte); 1936 } 1937 } 1938 } else { 1939 mpte = NULL; 1940 } 1941 1942 pte = pmap_pte(pmap, va); 1943 if (pte_test(pte, PTE_V)) { 1944 if (mpte != NULL) { 1945 mpte->wire_count--; 1946 mpte = NULL; 1947 } 1948 return (mpte); 1949 } 1950 1951 /* 1952 * Enter on the PV list if part of our managed memory. 1953 */ 1954 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 1955 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 1956 if (mpte != NULL) { 1957 pmap_unwire_pte_hold(pmap, mpte); 1958 mpte = NULL; 1959 } 1960 return (mpte); 1961 } 1962 1963 /* 1964 * Increment counters 1965 */ 1966 pmap->pm_stats.resident_count++; 1967 1968 pa = VM_PAGE_TO_PHYS(m); 1969 1970 /* 1971 * Now validate mapping with RO protection 1972 */ 1973 *pte = TLBLO_PA_TO_PFN(pa) | PTE_V; 1974 1975 if (is_cacheable_mem(pa)) 1976 *pte |= PTE_C_CACHE; 1977 else 1978 *pte |= PTE_C_UNCACHED; 1979 1980 if (is_kernel_pmap(pmap)) 1981 *pte |= PTE_G; 1982 else { 1983 *pte |= PTE_RO; 1984 /* 1985 * Sync I & D caches. Do this only if the the target pmap 1986 * belongs to the current process. Otherwise, an 1987 * unresolvable TLB miss may occur. */ 1988 if (pmap == &curproc->p_vmspace->vm_pmap) { 1989 va &= ~PAGE_MASK; 1990 mips_icache_sync_range(va, PAGE_SIZE); 1991 mips_dcache_wbinv_range(va, PAGE_SIZE); 1992 } 1993 } 1994 return (mpte); 1995} 1996 1997/* 1998 * Make a temporary mapping for a physical address. This is only intended 1999 * to be used for panic dumps. 2000 * 2001 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2002 */ 2003#if defined(__mips_n64) 2004void * 2005pmap_kenter_temporary(vm_paddr_t pa, int i) 2006{ 2007 return ((void *)MIPS_PHYS_TO_XKPHYS_CACHED(pa)); 2008} 2009void 2010pmap_kenter_temporary_free(vm_paddr_t pa) 2011{ 2012} 2013#else 2014void * 2015pmap_kenter_temporary(vm_paddr_t pa, int i) 2016{ 2017 vm_offset_t va; 2018 register_t intr; 2019 if (i != 0) 2020 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2021 __func__); 2022 2023 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2024 va = MIPS_PHYS_TO_KSEG0(pa); 2025 } else { 2026 int cpu; 2027 struct local_sysmaps *sysm; 2028 pt_entry_t *pte, npte; 2029 2030 /* If this is used other than for dumps, we may need to leave 2031 * interrupts disasbled on return. If crash dumps don't work when 2032 * we get to this point, we might want to consider this (leaving things 2033 * disabled as a starting point ;-) 2034 */ 2035 intr = intr_disable(); 2036 cpu = PCPU_GET(cpuid); 2037 sysm = &sysmap_lmem[cpu]; 2038 /* Since this is for the debugger, no locks or any other fun */ 2039 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G | PTE_W | PTE_C_CACHE; 2040 pte = pmap_pte(kernel_pmap, sysm->base); 2041 *pte = npte; 2042 sysm->valid1 = 1; 2043 pmap_update_page(kernel_pmap, sysm->base, npte); 2044 va = sysm->base; 2045 intr_restore(intr); 2046 } 2047 return ((void *)va); 2048} 2049 2050void 2051pmap_kenter_temporary_free(vm_paddr_t pa) 2052{ 2053 int cpu; 2054 register_t intr; 2055 struct local_sysmaps *sysm; 2056 2057 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2058 /* nothing to do for this case */ 2059 return; 2060 } 2061 cpu = PCPU_GET(cpuid); 2062 sysm = &sysmap_lmem[cpu]; 2063 if (sysm->valid1) { 2064 pt_entry_t *pte; 2065 2066 intr = intr_disable(); 2067 pte = pmap_pte(kernel_pmap, sysm->base); 2068 *pte = PTE_G; 2069 pmap_invalidate_page(kernel_pmap, sysm->base); 2070 intr_restore(intr); 2071 sysm->valid1 = 0; 2072 } 2073} 2074#endif 2075 2076/* 2077 * Moved the code to Machine Independent 2078 * vm_map_pmap_enter() 2079 */ 2080 2081/* 2082 * Maps a sequence of resident pages belonging to the same object. 2083 * The sequence begins with the given page m_start. This page is 2084 * mapped at the given virtual address start. Each subsequent page is 2085 * mapped at a virtual address that is offset from start by the same 2086 * amount as the page is offset from m_start within the object. The 2087 * last page in the sequence is the page with the largest offset from 2088 * m_start that can be mapped at a virtual address less than the given 2089 * virtual address end. Not every virtual page between start and end 2090 * is mapped; only those for which a resident page exists with the 2091 * corresponding offset from m_start are mapped. 2092 */ 2093void 2094pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2095 vm_page_t m_start, vm_prot_t prot) 2096{ 2097 vm_page_t m, mpte; 2098 vm_pindex_t diff, psize; 2099 2100 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2101 psize = atop(end - start); 2102 mpte = NULL; 2103 m = m_start; 2104 vm_page_lock_queues(); 2105 PMAP_LOCK(pmap); 2106 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2107 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2108 prot, mpte); 2109 m = TAILQ_NEXT(m, listq); 2110 } 2111 vm_page_unlock_queues(); 2112 PMAP_UNLOCK(pmap); 2113} 2114 2115/* 2116 * pmap_object_init_pt preloads the ptes for a given object 2117 * into the specified pmap. This eliminates the blast of soft 2118 * faults on process startup and immediately after an mmap. 2119 */ 2120void 2121pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2122 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2123{ 2124 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2125 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2126 ("pmap_object_init_pt: non-device object")); 2127} 2128 2129/* 2130 * Routine: pmap_change_wiring 2131 * Function: Change the wiring attribute for a map/virtual-address 2132 * pair. 2133 * In/out conditions: 2134 * The mapping must already exist in the pmap. 2135 */ 2136void 2137pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2138{ 2139 pt_entry_t *pte; 2140 2141 if (pmap == NULL) 2142 return; 2143 2144 PMAP_LOCK(pmap); 2145 pte = pmap_pte(pmap, va); 2146 2147 if (wired && !pte_test(pte, PTE_W)) 2148 pmap->pm_stats.wired_count++; 2149 else if (!wired && pte_test(pte, PTE_W)) 2150 pmap->pm_stats.wired_count--; 2151 2152 /* 2153 * Wiring is not a hardware characteristic so there is no need to 2154 * invalidate TLB. 2155 */ 2156 if (wired) 2157 pte_set(pte, PTE_W); 2158 else 2159 pte_clear(pte, PTE_W); 2160 PMAP_UNLOCK(pmap); 2161} 2162 2163/* 2164 * Copy the range specified by src_addr/len 2165 * from the source map to the range dst_addr/len 2166 * in the destination map. 2167 * 2168 * This routine is only advisory and need not do anything. 2169 */ 2170 2171void 2172pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2173 vm_size_t len, vm_offset_t src_addr) 2174{ 2175} 2176 2177/* 2178 * pmap_zero_page zeros the specified hardware page by mapping 2179 * the page into KVM and using bzero to clear its contents. 2180 * 2181 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2182 */ 2183#if defined (__mips_n64) 2184void 2185pmap_zero_page(vm_page_t m) 2186{ 2187 vm_offset_t va; 2188 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2189 2190 va = MIPS_PHYS_TO_XKPHYS_CACHED(phys); 2191 bzero((caddr_t)va, PAGE_SIZE); 2192 mips_dcache_wbinv_range(va, PAGE_SIZE); 2193} 2194#else 2195void 2196pmap_zero_page(vm_page_t m) 2197{ 2198 vm_offset_t va; 2199 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2200 register_t intr; 2201 2202 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2203 va = MIPS_PHYS_TO_KSEG0(phys); 2204 2205 bzero((caddr_t)va, PAGE_SIZE); 2206 mips_dcache_wbinv_range(va, PAGE_SIZE); 2207 } else { 2208 PMAP_LMEM_MAP1(va, phys); 2209 2210 bzero((caddr_t)va, PAGE_SIZE); 2211 mips_dcache_wbinv_range(va, PAGE_SIZE); 2212 2213 PMAP_LMEM_UNMAP(); 2214 } 2215} 2216#endif 2217/* 2218 * pmap_zero_page_area zeros the specified hardware page by mapping 2219 * the page into KVM and using bzero to clear its contents. 2220 * 2221 * off and size may not cover an area beyond a single hardware page. 2222 */ 2223#if defined (__mips_n64) 2224void 2225pmap_zero_page_area(vm_page_t m, int off, int size) 2226{ 2227 vm_offset_t va; 2228 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2229 2230 va = MIPS_PHYS_TO_XKPHYS_CACHED(phys); 2231 bzero((char *)(caddr_t)va + off, size); 2232 mips_dcache_wbinv_range(va + off, size); 2233} 2234#else 2235void 2236pmap_zero_page_area(vm_page_t m, int off, int size) 2237{ 2238 vm_offset_t va; 2239 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2240 register_t intr; 2241 2242 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2243 va = MIPS_PHYS_TO_KSEG0(phys); 2244 bzero((char *)(caddr_t)va + off, size); 2245 mips_dcache_wbinv_range(va + off, size); 2246 } else { 2247 PMAP_LMEM_MAP1(va, phys); 2248 2249 bzero((char *)va + off, size); 2250 mips_dcache_wbinv_range(va + off, size); 2251 2252 PMAP_LMEM_UNMAP(); 2253 } 2254} 2255#endif 2256 2257#if defined (__mips_n64) 2258void 2259pmap_zero_page_idle(vm_page_t m) 2260{ 2261 vm_offset_t va; 2262 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2263 2264 va = MIPS_PHYS_TO_XKPHYS_CACHED(phys); 2265 bzero((caddr_t)va, PAGE_SIZE); 2266 mips_dcache_wbinv_range(va, PAGE_SIZE); 2267} 2268#else 2269void 2270pmap_zero_page_idle(vm_page_t m) 2271{ 2272 vm_offset_t va; 2273 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2274 register_t intr; 2275 2276 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2277 va = MIPS_PHYS_TO_KSEG0(phys); 2278 bzero((caddr_t)va, PAGE_SIZE); 2279 mips_dcache_wbinv_range(va, PAGE_SIZE); 2280 } else { 2281 PMAP_LMEM_MAP1(va, phys); 2282 2283 bzero((caddr_t)va, PAGE_SIZE); 2284 mips_dcache_wbinv_range(va, PAGE_SIZE); 2285 2286 PMAP_LMEM_UNMAP(); 2287 } 2288} 2289#endif 2290 2291/* 2292 * pmap_copy_page copies the specified (machine independent) 2293 * page by mapping the page into virtual memory and using 2294 * bcopy to copy the page, one machine dependent page at a 2295 * time. 2296 * 2297 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2298 */ 2299#if defined (__mips_n64) 2300void 2301pmap_copy_page(vm_page_t src, vm_page_t dst) 2302{ 2303 vm_offset_t va_src, va_dst; 2304 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2305 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2306 2307 pmap_flush_pvcache(src); 2308 mips_dcache_wbinv_range_index(MIPS_PHYS_TO_XKPHYS_CACHED(phy_dst), PAGE_SIZE); 2309 va_src = MIPS_PHYS_TO_XKPHYS_CACHED(phy_src); 2310 va_dst = MIPS_PHYS_TO_XKPHYS_CACHED(phy_dst); 2311 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2312 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2313} 2314#else 2315void 2316pmap_copy_page(vm_page_t src, vm_page_t dst) 2317{ 2318 vm_offset_t va_src, va_dst; 2319 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2320 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2321 register_t intr; 2322 2323 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2324 /* easy case, all can be accessed via KSEG0 */ 2325 /* 2326 * Flush all caches for VA that are mapped to this page 2327 * to make sure that data in SDRAM is up to date 2328 */ 2329 pmap_flush_pvcache(src); 2330 mips_dcache_wbinv_range_index( 2331 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2332 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2333 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2334 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2335 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2336 } else { 2337 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2338 2339 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2340 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2341 2342 PMAP_LMEM_UNMAP(); 2343 } 2344} 2345#endif 2346 2347/* 2348 * Returns true if the pmap's pv is one of the first 2349 * 16 pvs linked to from this page. This count may 2350 * be changed upwards or downwards in the future; it 2351 * is only necessary that true be returned for a small 2352 * subset of pmaps for proper page aging. 2353 */ 2354boolean_t 2355pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2356{ 2357 pv_entry_t pv; 2358 int loops = 0; 2359 boolean_t rv; 2360 2361 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2362 ("pmap_page_exists_quick: page %p is not managed", m)); 2363 rv = FALSE; 2364 vm_page_lock_queues(); 2365 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2366 if (pv->pv_pmap == pmap) { 2367 rv = TRUE; 2368 break; 2369 } 2370 loops++; 2371 if (loops >= 16) 2372 break; 2373 } 2374 vm_page_unlock_queues(); 2375 return (rv); 2376} 2377 2378/* 2379 * Remove all pages from specified address space 2380 * this aids process exit speeds. Also, this code 2381 * is special cased for current process only, but 2382 * can have the more generic (and slightly slower) 2383 * mode enabled. This is much faster than pmap_remove 2384 * in the case of running down an entire address space. 2385 */ 2386void 2387pmap_remove_pages(pmap_t pmap) 2388{ 2389 pt_entry_t *pte, tpte; 2390 pv_entry_t pv, npv; 2391 vm_page_t m; 2392 2393 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2394 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2395 return; 2396 } 2397 vm_page_lock_queues(); 2398 PMAP_LOCK(pmap); 2399 sched_pin(); 2400 //XXX need to be TAILQ_FOREACH_SAFE ? 2401 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2402 2403 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2404 if (!pte_test(pte, PTE_V)) 2405 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2406 tpte = *pte; 2407 2408/* 2409 * We cannot remove wired pages from a process' mapping at this time 2410 */ 2411 if (pte_test(&tpte, PTE_W)) { 2412 npv = TAILQ_NEXT(pv, pv_plist); 2413 continue; 2414 } 2415 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2416 2417 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); 2418 KASSERT(m != NULL, 2419 ("pmap_remove_pages: bad tpte %x", tpte)); 2420 2421 pv->pv_pmap->pm_stats.resident_count--; 2422 2423 /* 2424 * Update the vm_page_t clean and reference bits. 2425 */ 2426 if (pte_test(&tpte, PTE_D)) { 2427 vm_page_dirty(m); 2428 } 2429 npv = TAILQ_NEXT(pv, pv_plist); 2430 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2431 2432 m->md.pv_list_count--; 2433 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2434 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2435 vm_page_flag_clear(m, PG_WRITEABLE); 2436 } 2437 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2438 free_pv_entry(pv); 2439 } 2440 sched_unpin(); 2441 pmap_invalidate_all(pmap); 2442 PMAP_UNLOCK(pmap); 2443 vm_page_unlock_queues(); 2444} 2445 2446/* 2447 * pmap_testbit tests bits in pte's 2448 * note that the testbit/changebit routines are inline, 2449 * and a lot of things compile-time evaluate. 2450 */ 2451static boolean_t 2452pmap_testbit(vm_page_t m, int bit) 2453{ 2454 pv_entry_t pv; 2455 pt_entry_t *pte; 2456 boolean_t rv = FALSE; 2457 2458 if (m->flags & PG_FICTITIOUS) 2459 return rv; 2460 2461 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2462 return rv; 2463 2464 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2465 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2466#if defined(PMAP_DIAGNOSTIC) 2467 if (!pv->pv_pmap) { 2468 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2469 continue; 2470 } 2471#endif 2472 PMAP_LOCK(pv->pv_pmap); 2473 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2474 rv = pte_test(pte, bit); 2475 PMAP_UNLOCK(pv->pv_pmap); 2476 if (rv) 2477 break; 2478 } 2479 return (rv); 2480} 2481 2482/* 2483 * this routine is used to clear dirty bits in ptes 2484 */ 2485static __inline void 2486pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2487{ 2488 pv_entry_t pv; 2489 pt_entry_t *pte; 2490 2491 if (m->flags & PG_FICTITIOUS) 2492 return; 2493 2494 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2495 /* 2496 * Loop over all current mappings setting/clearing as appropos If 2497 * setting RO do we need to clear the VAC? 2498 */ 2499 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2500#if defined(PMAP_DIAGNOSTIC) 2501 if (!pv->pv_pmap) { 2502 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2503 continue; 2504 } 2505#endif 2506 2507 PMAP_LOCK(pv->pv_pmap); 2508 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2509 2510 if (setem) { 2511 *(int *)pte |= bit; 2512 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2513 } else { 2514 vm_offset_t pbits = *(vm_offset_t *)pte; 2515 2516 if (pbits & bit) { 2517 if (bit == PTE_D) { 2518 if (pbits & PTE_D) { 2519 vm_page_dirty(m); 2520 } 2521 *(int *)pte = (pbits & ~PTE_D) | PTE_RO; 2522 } else { 2523 *(int *)pte = pbits & ~bit; 2524 } 2525 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2526 } 2527 } 2528 PMAP_UNLOCK(pv->pv_pmap); 2529 } 2530 if (!setem && bit == PTE_D) 2531 vm_page_flag_clear(m, PG_WRITEABLE); 2532} 2533 2534/* 2535 * pmap_page_wired_mappings: 2536 * 2537 * Return the number of managed mappings to the given physical page 2538 * that are wired. 2539 */ 2540int 2541pmap_page_wired_mappings(vm_page_t m) 2542{ 2543 pv_entry_t pv; 2544 int count; 2545 2546 count = 0; 2547 if ((m->flags & PG_FICTITIOUS) != 0) 2548 return (count); 2549 vm_page_lock_queues(); 2550 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2551 if (pv->pv_wired) 2552 count++; 2553 vm_page_unlock_queues(); 2554 return (count); 2555} 2556 2557/* 2558 * Clear the write and modified bits in each of the given page's mappings. 2559 */ 2560void 2561pmap_remove_write(vm_page_t m) 2562{ 2563 pv_entry_t pv, npv; 2564 vm_offset_t va; 2565 pt_entry_t *pte; 2566 2567 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2568 ("pmap_remove_write: page %p is not managed", m)); 2569 2570 /* 2571 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 2572 * another thread while the object is locked. Thus, if PG_WRITEABLE 2573 * is clear, no page table entries need updating. 2574 */ 2575 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2576 if ((m->oflags & VPO_BUSY) == 0 && 2577 (m->flags & PG_WRITEABLE) == 0) 2578 return; 2579 2580 /* 2581 * Loop over all current mappings setting/clearing as appropos. 2582 */ 2583 vm_page_lock_queues(); 2584 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2585 npv = TAILQ_NEXT(pv, pv_plist); 2586 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2587 if (pte == NULL || !pte_test(pte, PTE_V)) 2588 panic("page on pm_pvlist has no pte\n"); 2589 2590 va = pv->pv_va; 2591 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2592 VM_PROT_READ | VM_PROT_EXECUTE); 2593 } 2594 vm_page_flag_clear(m, PG_WRITEABLE); 2595 vm_page_unlock_queues(); 2596} 2597 2598/* 2599 * pmap_ts_referenced: 2600 * 2601 * Return the count of reference bits for a page, clearing all of them. 2602 */ 2603int 2604pmap_ts_referenced(vm_page_t m) 2605{ 2606 2607 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2608 ("pmap_ts_referenced: page %p is not managed", m)); 2609 if (m->md.pv_flags & PV_TABLE_REF) { 2610 vm_page_lock_queues(); 2611 m->md.pv_flags &= ~PV_TABLE_REF; 2612 vm_page_unlock_queues(); 2613 return (1); 2614 } 2615 return (0); 2616} 2617 2618/* 2619 * pmap_is_modified: 2620 * 2621 * Return whether or not the specified physical page was modified 2622 * in any physical maps. 2623 */ 2624boolean_t 2625pmap_is_modified(vm_page_t m) 2626{ 2627 boolean_t rv; 2628 2629 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2630 ("pmap_is_modified: page %p is not managed", m)); 2631 2632 /* 2633 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2634 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2635 * is clear, no PTEs can have PTE_D set. 2636 */ 2637 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2638 if ((m->oflags & VPO_BUSY) == 0 && 2639 (m->flags & PG_WRITEABLE) == 0) 2640 return (FALSE); 2641 vm_page_lock_queues(); 2642 if (m->md.pv_flags & PV_TABLE_MOD) 2643 rv = TRUE; 2644 else 2645 rv = pmap_testbit(m, PTE_D); 2646 vm_page_unlock_queues(); 2647 return (rv); 2648} 2649 2650/* N/C */ 2651 2652/* 2653 * pmap_is_prefaultable: 2654 * 2655 * Return whether or not the specified virtual address is elgible 2656 * for prefault. 2657 */ 2658boolean_t 2659pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2660{ 2661 pt_entry_t *pte; 2662 boolean_t rv; 2663 2664 rv = FALSE; 2665 PMAP_LOCK(pmap); 2666 if (pmap_segmap(pmap, addr) != NULL) { 2667 pte = pmap_pte(pmap, addr); 2668 rv = (*pte == 0); 2669 } 2670 PMAP_UNLOCK(pmap); 2671 return (rv); 2672} 2673 2674/* 2675 * Clear the modify bits on the specified physical page. 2676 */ 2677void 2678pmap_clear_modify(vm_page_t m) 2679{ 2680 2681 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2682 ("pmap_clear_modify: page %p is not managed", m)); 2683 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2684 KASSERT((m->oflags & VPO_BUSY) == 0, 2685 ("pmap_clear_modify: page %p is busy", m)); 2686 2687 /* 2688 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_D set. 2689 * If the object containing the page is locked and the page is not 2690 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2691 */ 2692 if ((m->flags & PG_WRITEABLE) == 0) 2693 return; 2694 vm_page_lock_queues(); 2695 if (m->md.pv_flags & PV_TABLE_MOD) { 2696 pmap_changebit(m, PTE_D, FALSE); 2697 m->md.pv_flags &= ~PV_TABLE_MOD; 2698 } 2699 vm_page_unlock_queues(); 2700} 2701 2702/* 2703 * pmap_is_referenced: 2704 * 2705 * Return whether or not the specified physical page was referenced 2706 * in any physical maps. 2707 */ 2708boolean_t 2709pmap_is_referenced(vm_page_t m) 2710{ 2711 2712 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2713 ("pmap_is_referenced: page %p is not managed", m)); 2714 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 2715} 2716 2717/* 2718 * pmap_clear_reference: 2719 * 2720 * Clear the reference bit on the specified physical page. 2721 */ 2722void 2723pmap_clear_reference(vm_page_t m) 2724{ 2725 2726 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2727 ("pmap_clear_reference: page %p is not managed", m)); 2728 vm_page_lock_queues(); 2729 if (m->md.pv_flags & PV_TABLE_REF) { 2730 m->md.pv_flags &= ~PV_TABLE_REF; 2731 } 2732 vm_page_unlock_queues(); 2733} 2734 2735/* 2736 * Miscellaneous support routines follow 2737 */ 2738 2739/* 2740 * Map a set of physical memory pages into the kernel virtual 2741 * address space. Return a pointer to where it is mapped. This 2742 * routine is intended to be used for mapping device memory, 2743 * NOT real memory. 2744 */ 2745 2746/* 2747 * Map a set of physical memory pages into the kernel virtual 2748 * address space. Return a pointer to where it is mapped. This 2749 * routine is intended to be used for mapping device memory, 2750 * NOT real memory. 2751 * 2752 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit. 2753 */ 2754#if defined(__mips_n64) 2755void * 2756pmap_mapdev(vm_offset_t pa, vm_size_t size) 2757{ 2758 return ((void *)MIPS_PHYS_TO_XKPHYS_UNCACHED(pa)); 2759} 2760 2761void 2762pmap_unmapdev(vm_offset_t va, vm_size_t size) 2763{ 2764} 2765#else 2766void * 2767pmap_mapdev(vm_offset_t pa, vm_size_t size) 2768{ 2769 vm_offset_t va, tmpva, offset; 2770 2771 /* 2772 * KSEG1 maps only first 512M of phys address space. For 2773 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2774 */ 2775 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2776 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2777 else { 2778 offset = pa & PAGE_MASK; 2779 size = roundup(size + offset, PAGE_SIZE); 2780 2781 va = kmem_alloc_nofault(kernel_map, size); 2782 if (!va) 2783 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2784 pa = trunc_page(pa); 2785 for (tmpva = va; size > 0;) { 2786 pmap_kenter(tmpva, pa); 2787 size -= PAGE_SIZE; 2788 tmpva += PAGE_SIZE; 2789 pa += PAGE_SIZE; 2790 } 2791 } 2792 2793 return ((void *)(va + offset)); 2794} 2795 2796void 2797pmap_unmapdev(vm_offset_t va, vm_size_t size) 2798{ 2799 vm_offset_t base, offset, tmpva; 2800 2801 /* If the address is within KSEG1 then there is nothing to do */ 2802 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2803 return; 2804 2805 base = trunc_page(va); 2806 offset = va & PAGE_MASK; 2807 size = roundup(size + offset, PAGE_SIZE); 2808 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2809 pmap_kremove(tmpva); 2810 kmem_free(kernel_map, base, size); 2811} 2812#endif 2813 2814/* 2815 * perform the pmap work for mincore 2816 */ 2817int 2818pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 2819{ 2820 pt_entry_t *ptep, pte; 2821 vm_offset_t pa; 2822 vm_page_t m; 2823 int val; 2824 boolean_t managed; 2825 2826 PMAP_LOCK(pmap); 2827retry: 2828 ptep = pmap_pte(pmap, addr); 2829 pte = (ptep != NULL) ? *ptep : 0; 2830 if (!pte_test(&pte, PTE_V)) { 2831 val = 0; 2832 goto out; 2833 } 2834 val = MINCORE_INCORE; 2835 if (pte_test(&pte, PTE_D)) 2836 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2837 pa = TLBLO_PTE_TO_PA(pte); 2838 managed = page_is_managed(pa); 2839 if (managed) { 2840 /* 2841 * This may falsely report the given address as 2842 * MINCORE_REFERENCED. Unfortunately, due to the lack of 2843 * per-PTE reference information, it is impossible to 2844 * determine if the address is MINCORE_REFERENCED. 2845 */ 2846 m = PHYS_TO_VM_PAGE(pa); 2847 if ((m->flags & PG_REFERENCED) != 0) 2848 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2849 } 2850 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 2851 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 2852 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 2853 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 2854 goto retry; 2855 } else 2856out: 2857 PA_UNLOCK_COND(*locked_pa); 2858 PMAP_UNLOCK(pmap); 2859 return (val); 2860} 2861 2862void 2863pmap_activate(struct thread *td) 2864{ 2865 pmap_t pmap, oldpmap; 2866 struct proc *p = td->td_proc; 2867 2868 critical_enter(); 2869 2870 pmap = vmspace_pmap(p->p_vmspace); 2871 oldpmap = PCPU_GET(curpmap); 2872 2873 if (oldpmap) 2874 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2875 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2876 pmap_asid_alloc(pmap); 2877 if (td == curthread) { 2878 PCPU_SET(segbase, pmap->pm_segtab); 2879 mips_wr_entryhi(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2880 } 2881 2882 PCPU_SET(curpmap, pmap); 2883 critical_exit(); 2884} 2885 2886void 2887pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2888{ 2889} 2890 2891/* 2892 * Increase the starting virtual address of the given mapping if a 2893 * different alignment might result in more superpage mappings. 2894 */ 2895void 2896pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2897 vm_offset_t *addr, vm_size_t size) 2898{ 2899 vm_offset_t superpage_offset; 2900 2901 if (size < NBSEG) 2902 return; 2903 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2904 offset += ptoa(object->pg_color); 2905 superpage_offset = offset & SEGMASK; 2906 if (size - ((NBSEG - superpage_offset) & SEGMASK) < NBSEG || 2907 (*addr & SEGMASK) == superpage_offset) 2908 return; 2909 if ((*addr & SEGMASK) < superpage_offset) 2910 *addr = (*addr & ~SEGMASK) + superpage_offset; 2911 else 2912 *addr = ((*addr + SEGMASK) & ~SEGMASK) + superpage_offset; 2913} 2914 2915/* 2916 * Increase the starting virtual address of the given mapping so 2917 * that it is aligned to not be the second page in a TLB entry. 2918 * This routine assumes that the length is appropriately-sized so 2919 * that the allocation does not share a TLB entry at all if required. 2920 */ 2921void 2922pmap_align_tlb(vm_offset_t *addr) 2923{ 2924 if ((*addr & PAGE_SIZE) == 0) 2925 return; 2926 *addr += PAGE_SIZE; 2927 return; 2928} 2929 2930int pmap_pid_dump(int pid); 2931 2932int 2933pmap_pid_dump(int pid) 2934{ 2935 pmap_t pmap; 2936 struct proc *p; 2937 int npte = 0; 2938 int index; 2939 2940 sx_slock(&allproc_lock); 2941 LIST_FOREACH(p, &allproc, p_list) { 2942 if (p->p_pid != pid) 2943 continue; 2944 2945 if (p->p_vmspace) { 2946 int i, j; 2947 2948 printf("vmspace is %p\n", 2949 p->p_vmspace); 2950 index = 0; 2951 pmap = vmspace_pmap(p->p_vmspace); 2952 printf("pmap asid:%x generation:%x\n", 2953 pmap->pm_asid[0].asid, 2954 pmap->pm_asid[0].gen); 2955 for (i = 0; i < NUSERPGTBLS; i++) { 2956 pd_entry_t *pde; 2957 pt_entry_t *pte; 2958 unsigned base = i << SEGSHIFT; 2959 2960 pde = &pmap->pm_segtab[i]; 2961 if (pde && *pde != 0) { 2962 for (j = 0; j < 1024; j++) { 2963 vm_offset_t va = base + 2964 (j << PAGE_SHIFT); 2965 2966 pte = pmap_pte(pmap, va); 2967 if (pte && pte_test(pte, PTE_V)) { 2968 vm_offset_t pa; 2969 vm_page_t m; 2970 2971 pa = TLBLO_PFN_TO_PA(*pte); 2972 m = PHYS_TO_VM_PAGE(pa); 2973 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2974 (void *)va, 2975 (void *)pa, 2976 m->hold_count, 2977 m->wire_count, 2978 m->flags); 2979 npte++; 2980 index++; 2981 if (index >= 2) { 2982 index = 0; 2983 printf("\n"); 2984 } else { 2985 printf(" "); 2986 } 2987 } 2988 } 2989 } 2990 } 2991 } else { 2992 printf("Process pid:%d has no vm_space\n", pid); 2993 } 2994 break; 2995 } 2996 sx_sunlock(&allproc_lock); 2997 return npte; 2998} 2999 3000 3001#if defined(DEBUG) 3002 3003static void pads(pmap_t pm); 3004void pmap_pvdump(vm_offset_t pa); 3005 3006/* print address space of pmap*/ 3007static void 3008pads(pmap_t pm) 3009{ 3010 unsigned va, i, j; 3011 pt_entry_t *ptep; 3012 3013 if (pm == kernel_pmap) 3014 return; 3015 for (i = 0; i < NPTEPG; i++) 3016 if (pm->pm_segtab[i]) 3017 for (j = 0; j < NPTEPG; j++) { 3018 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 3019 if (pm == kernel_pmap && va < KERNBASE) 3020 continue; 3021 if (pm != kernel_pmap && 3022 va >= VM_MAXUSER_ADDRESS) 3023 continue; 3024 ptep = pmap_pte(pm, va); 3025 if (pmap_pte_v(ptep)) 3026 printf("%x:%x ", va, *(int *)ptep); 3027 } 3028 3029} 3030 3031void 3032pmap_pvdump(vm_offset_t pa) 3033{ 3034 register pv_entry_t pv; 3035 vm_page_t m; 3036 3037 printf("pa %x", pa); 3038 m = PHYS_TO_VM_PAGE(pa); 3039 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3040 pv = TAILQ_NEXT(pv, pv_list)) { 3041 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 3042 pads(pv->pv_pmap); 3043 } 3044 printf(" "); 3045} 3046 3047/* N/C */ 3048#endif 3049 3050 3051/* 3052 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3053 * It takes almost as much or more time to search the TLB for a 3054 * specific ASID and flush those entries as it does to flush the entire TLB. 3055 * Therefore, when we allocate a new ASID, we just take the next number. When 3056 * we run out of numbers, we flush the TLB, increment the generation count 3057 * and start over. ASID zero is reserved for kernel use. 3058 */ 3059static void 3060pmap_asid_alloc(pmap) 3061 pmap_t pmap; 3062{ 3063 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3064 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3065 else { 3066 if (PCPU_GET(next_asid) == pmap_max_asid) { 3067 tlb_invalidate_all_user(NULL); 3068 PCPU_SET(asid_generation, 3069 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3070 if (PCPU_GET(asid_generation) == 0) { 3071 PCPU_SET(asid_generation, 1); 3072 } 3073 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3074 } 3075 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3076 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3077 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3078 } 3079} 3080 3081int 3082page_is_managed(vm_offset_t pa) 3083{ 3084 vm_offset_t pgnum = mips_btop(pa); 3085 3086 if (pgnum >= first_page) { 3087 vm_page_t m; 3088 3089 m = PHYS_TO_VM_PAGE(pa); 3090 if (m == NULL) 3091 return 0; 3092 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3093 return 1; 3094 } 3095 return 0; 3096} 3097 3098static int 3099init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3100{ 3101 int rw; 3102 3103 if (!(prot & VM_PROT_WRITE)) 3104 rw = PTE_V | PTE_RO | PTE_C_CACHE; 3105 else if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3106 if ((m->md.pv_flags & PV_TABLE_MOD) != 0) 3107 rw = PTE_V | PTE_D | PTE_C_CACHE; 3108 else 3109 rw = PTE_V | PTE_C_CACHE; 3110 vm_page_flag_set(m, PG_WRITEABLE); 3111 } else 3112 /* Needn't emulate a modified bit for unmanaged pages. */ 3113 rw = PTE_V | PTE_D | PTE_C_CACHE; 3114 return (rw); 3115} 3116 3117/* 3118 * pmap_set_modified: 3119 * 3120 * Sets the page modified and reference bits for the specified page. 3121 */ 3122void 3123pmap_set_modified(vm_offset_t pa) 3124{ 3125 3126 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3127} 3128 3129 3130/* 3131 * Routine: pmap_kextract 3132 * Function: 3133 * Extract the physical page address associated 3134 * virtual address. 3135 */ 3136 /* PMAP_INLINE */ vm_offset_t 3137pmap_kextract(vm_offset_t va) 3138{ 3139 int mapped; 3140 3141 /* 3142 * First, the direct-mapped regions. 3143 */ 3144#if defined(__mips_n64) 3145 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END) 3146 return (MIPS_XKPHYS_TO_PHYS(va)); 3147#endif 3148 3149 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END) 3150 return (MIPS_KSEG0_TO_PHYS(va)); 3151 3152 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END) 3153 return (MIPS_KSEG1_TO_PHYS(va)); 3154 3155 /* 3156 * User virtual addresses. 3157 */ 3158 if (va < VM_MAXUSER_ADDRESS) { 3159 pt_entry_t *ptep; 3160 3161 if (curproc && curproc->p_vmspace) { 3162 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3163 if (ptep) { 3164 return (TLBLO_PTE_TO_PA(*ptep) | 3165 (va & PAGE_MASK)); 3166 } 3167 return (0); 3168 } 3169 } 3170 3171 /* 3172 * Should be kernel virtual here, otherwise fail 3173 */ 3174 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END); 3175#if defined(__mips_n64) 3176 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END); 3177#endif 3178 /* 3179 * Kernel virtual. 3180 */ 3181 3182 if (mapped) { 3183 pt_entry_t *ptep; 3184 3185 /* Is the kernel pmap initialized? */ 3186 if (kernel_pmap->pm_active) { 3187 /* It's inside the virtual address range */ 3188 ptep = pmap_pte(kernel_pmap, va); 3189 if (ptep) { 3190 return (TLBLO_PTE_TO_PA(*ptep) | 3191 (va & PAGE_MASK)); 3192 } 3193 } 3194 return (0); 3195 } 3196 3197 panic("%s for unknown address space %p.", __func__, (void *)va); 3198} 3199 3200 3201void 3202pmap_flush_pvcache(vm_page_t m) 3203{ 3204 pv_entry_t pv; 3205 3206 if (m != NULL) { 3207 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3208 pv = TAILQ_NEXT(pv, pv_list)) { 3209 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3210 } 3211 } 3212} 3213