1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * Since the information managed by this module is 46 * also stored by the logical address mapping module, 47 * this module may throw away valid virtual-to-physical 48 * mappings at almost any time. However, invalidations 49 * of virtual-to-physical mappings must be done as 50 * requested. 51 * 52 * In order to cope with hardware architectures which 53 * make virtual-to-physical map invalidates expensive, 54 * this module may delay invalidate or reduced protection 55 * operations until such time as they are actually 56 * necessary. This module is given full information as 57 * to which processors are currently using which maps, 58 * and to when physical maps must be made correct. 59 */ 60 61#include <sys/cdefs.h> 62__FBSDID("$FreeBSD$"); 63 64#include "opt_ddb.h" 65#include "opt_pmap.h" 66 67#include <sys/param.h> 68#include <sys/systm.h> 69#include <sys/lock.h> 70#include <sys/mman.h> 71#include <sys/msgbuf.h> 72#include <sys/mutex.h> 73#include <sys/pcpu.h> 74#include <sys/proc.h> 75#include <sys/rwlock.h> 76#include <sys/sched.h> 77#ifdef SMP 78#include <sys/smp.h> 79#else 80#include <sys/cpuset.h> 81#endif 82#include <sys/sysctl.h> 83#include <sys/vmmeter.h> 84 85#ifdef DDB 86#include <ddb/ddb.h> 87#endif 88 89#include <vm/vm.h> 90#include <vm/vm_param.h> 91#include <vm/vm_kern.h> 92#include <vm/vm_page.h> 93#include <vm/vm_map.h> 94#include <vm/vm_object.h> 95#include <vm/vm_extern.h> 96#include <vm/vm_pageout.h> 97#include <vm/vm_pager.h> 98#include <vm/uma.h> 99 100#include <machine/cache.h> 101#include <machine/md_var.h> 102#include <machine/tlb.h> 103 104#undef PMAP_DEBUG 105 106#if !defined(DIAGNOSTIC) 107#define PMAP_INLINE __inline 108#else 109#define PMAP_INLINE 110#endif 111 112#ifdef PV_STATS 113#define PV_STAT(x) do { x ; } while (0) 114#else 115#define PV_STAT(x) do { } while (0) 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1)) 122#define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1)) 123#define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1)) 124#define pmap_pde_pindex(v) ((v) >> PDRSHIFT) 125 126#ifdef __mips_n64 127#define NUPDE (NPDEPG * NPDEPG) 128#define NUSERPGTBLS (NUPDE + NPDEPG) 129#else 130#define NUPDE (NPDEPG) 131#define NUSERPGTBLS (NUPDE) 132#endif 133 134#define is_kernel_pmap(x) ((x) == kernel_pmap) 135 136struct pmap kernel_pmap_store; 137pd_entry_t *kernel_segmap; 138 139vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 140vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 141 142static int nkpt; 143unsigned pmap_max_asid; /* max ASID supported by the system */ 144 145#define PMAP_ASID_RESERVED 0 146 147vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 148 149static void pmap_asid_alloc(pmap_t pmap); 150 151static struct rwlock_padalign pvh_global_lock; 152 153/* 154 * Data for the pv entry allocation mechanism 155 */ 156static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 157static int pv_entry_count; 158 159static void free_pv_chunk(struct pv_chunk *pc); 160static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 161static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 162static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap); 163static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 164static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 165 vm_offset_t va); 166static vm_page_t pmap_alloc_direct_page(unsigned int index, int req); 167static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 168 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 169static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 170 pd_entry_t pde); 171static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 172static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 173static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 174 vm_offset_t va, vm_page_t m); 175static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte); 176static void pmap_invalidate_all(pmap_t pmap); 177static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va); 178static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m); 179 180static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 181static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 182static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t); 183static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot); 184 185static void pmap_invalidate_page_action(void *arg); 186static void pmap_invalidate_range_action(void *arg); 187static void pmap_update_page_action(void *arg); 188 189#ifndef __mips_n64 190/* 191 * This structure is for high memory (memory above 512Meg in 32 bit) support. 192 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to 193 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc. 194 * 195 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To 196 * access a highmem physical address on a CPU, we map the physical address to 197 * the reserved virtual address for the CPU in the kernel pagetable. This is 198 * done with interrupts disabled(although a spinlock and sched_pin would be 199 * sufficient). 200 */ 201struct local_sysmaps { 202 vm_offset_t base; 203 uint32_t saved_intr; 204 uint16_t valid1, valid2; 205}; 206static struct local_sysmaps sysmap_lmem[MAXCPU]; 207 208static __inline void 209pmap_alloc_lmem_map(void) 210{ 211 int i; 212 213 for (i = 0; i < MAXCPU; i++) { 214 sysmap_lmem[i].base = virtual_avail; 215 virtual_avail += PAGE_SIZE * 2; 216 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 217 } 218} 219 220static __inline vm_offset_t 221pmap_lmem_map1(vm_paddr_t phys) 222{ 223 struct local_sysmaps *sysm; 224 pt_entry_t *pte, npte; 225 vm_offset_t va; 226 uint32_t intr; 227 int cpu; 228 229 intr = intr_disable(); 230 cpu = PCPU_GET(cpuid); 231 sysm = &sysmap_lmem[cpu]; 232 sysm->saved_intr = intr; 233 va = sysm->base; 234 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 235 pte = pmap_pte(kernel_pmap, va); 236 *pte = npte; 237 sysm->valid1 = 1; 238 return (va); 239} 240 241static __inline vm_offset_t 242pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 243{ 244 struct local_sysmaps *sysm; 245 pt_entry_t *pte, npte; 246 vm_offset_t va1, va2; 247 uint32_t intr; 248 int cpu; 249 250 intr = intr_disable(); 251 cpu = PCPU_GET(cpuid); 252 sysm = &sysmap_lmem[cpu]; 253 sysm->saved_intr = intr; 254 va1 = sysm->base; 255 va2 = sysm->base + PAGE_SIZE; 256 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 257 pte = pmap_pte(kernel_pmap, va1); 258 *pte = npte; 259 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G; 260 pte = pmap_pte(kernel_pmap, va2); 261 *pte = npte; 262 sysm->valid1 = 1; 263 sysm->valid2 = 1; 264 return (va1); 265} 266 267static __inline void 268pmap_lmem_unmap(void) 269{ 270 struct local_sysmaps *sysm; 271 pt_entry_t *pte; 272 int cpu; 273 274 cpu = PCPU_GET(cpuid); 275 sysm = &sysmap_lmem[cpu]; 276 pte = pmap_pte(kernel_pmap, sysm->base); 277 *pte = PTE_G; 278 tlb_invalidate_address(kernel_pmap, sysm->base); 279 sysm->valid1 = 0; 280 if (sysm->valid2) { 281 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); 282 *pte = PTE_G; 283 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE); 284 sysm->valid2 = 0; 285 } 286 intr_restore(sysm->saved_intr); 287} 288#else /* __mips_n64 */ 289 290static __inline void 291pmap_alloc_lmem_map(void) 292{ 293} 294 295static __inline vm_offset_t 296pmap_lmem_map1(vm_paddr_t phys) 297{ 298 299 return (0); 300} 301 302static __inline vm_offset_t 303pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2) 304{ 305 306 return (0); 307} 308 309static __inline vm_offset_t 310pmap_lmem_unmap(void) 311{ 312 313 return (0); 314} 315#endif /* !__mips_n64 */ 316 317/* 318 * Page table entry lookup routines. 319 */ 320static __inline pd_entry_t * 321pmap_segmap(pmap_t pmap, vm_offset_t va) 322{ 323 324 return (&pmap->pm_segtab[pmap_seg_index(va)]); 325} 326 327#ifdef __mips_n64 328static __inline pd_entry_t * 329pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 330{ 331 pd_entry_t *pde; 332 333 pde = (pd_entry_t *)*pdpe; 334 return (&pde[pmap_pde_index(va)]); 335} 336 337static __inline pd_entry_t * 338pmap_pde(pmap_t pmap, vm_offset_t va) 339{ 340 pd_entry_t *pdpe; 341 342 pdpe = pmap_segmap(pmap, va); 343 if (*pdpe == NULL) 344 return (NULL); 345 346 return (pmap_pdpe_to_pde(pdpe, va)); 347} 348#else 349static __inline pd_entry_t * 350pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va) 351{ 352 353 return (pdpe); 354} 355 356static __inline 357pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va) 358{ 359 360 return (pmap_segmap(pmap, va)); 361} 362#endif 363 364static __inline pt_entry_t * 365pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va) 366{ 367 pt_entry_t *pte; 368 369 pte = (pt_entry_t *)*pde; 370 return (&pte[pmap_pte_index(va)]); 371} 372 373pt_entry_t * 374pmap_pte(pmap_t pmap, vm_offset_t va) 375{ 376 pd_entry_t *pde; 377 378 pde = pmap_pde(pmap, va); 379 if (pde == NULL || *pde == NULL) 380 return (NULL); 381 382 return (pmap_pde_to_pte(pde, va)); 383} 384 385vm_offset_t 386pmap_steal_memory(vm_size_t size) 387{ 388 vm_paddr_t bank_size, pa; 389 vm_offset_t va; 390 391 size = round_page(size); 392 bank_size = phys_avail[1] - phys_avail[0]; 393 while (size > bank_size) { 394 int i; 395 396 for (i = 0; phys_avail[i + 2]; i += 2) { 397 phys_avail[i] = phys_avail[i + 2]; 398 phys_avail[i + 1] = phys_avail[i + 3]; 399 } 400 phys_avail[i] = 0; 401 phys_avail[i + 1] = 0; 402 if (!phys_avail[0]) 403 panic("pmap_steal_memory: out of memory"); 404 bank_size = phys_avail[1] - phys_avail[0]; 405 } 406 407 pa = phys_avail[0]; 408 phys_avail[0] += size; 409 if (MIPS_DIRECT_MAPPABLE(pa) == 0) 410 panic("Out of memory below 512Meg?"); 411 va = MIPS_PHYS_TO_DIRECT(pa); 412 bzero((caddr_t)va, size); 413 return (va); 414} 415 416/* 417 * Bootstrap the system enough to run with virtual memory. This 418 * assumes that the phys_avail array has been initialized. 419 */ 420static void 421pmap_create_kernel_pagetable(void) 422{ 423 int i, j; 424 vm_offset_t ptaddr; 425 pt_entry_t *pte; 426#ifdef __mips_n64 427 pd_entry_t *pde; 428 vm_offset_t pdaddr; 429 int npt, npde; 430#endif 431 432 /* 433 * Allocate segment table for the kernel 434 */ 435 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 436 437 /* 438 * Allocate second level page tables for the kernel 439 */ 440#ifdef __mips_n64 441 npde = howmany(NKPT, NPDEPG); 442 pdaddr = pmap_steal_memory(PAGE_SIZE * npde); 443#endif 444 nkpt = NKPT; 445 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt); 446 447 /* 448 * The R[4-7]?00 stores only one copy of the Global bit in the 449 * translation lookaside buffer for each 2 page entry. Thus invalid 450 * entrys must have the Global bit set so when Entry LO and Entry HI 451 * G bits are anded together they will produce a global bit to store 452 * in the tlb. 453 */ 454 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++) 455 *pte = PTE_G; 456 457#ifdef __mips_n64 458 for (i = 0, npt = nkpt; npt > 0; i++) { 459 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE); 460 pde = (pd_entry_t *)kernel_segmap[i]; 461 462 for (j = 0; j < NPDEPG && npt > 0; j++, npt--) 463 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE); 464 } 465#else 466 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++) 467 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE)); 468#endif 469 470 PMAP_LOCK_INIT(kernel_pmap); 471 kernel_pmap->pm_segtab = kernel_segmap; 472 CPU_FILL(&kernel_pmap->pm_active); 473 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 474 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 475 kernel_pmap->pm_asid[0].gen = 0; 476 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE; 477} 478 479void 480pmap_bootstrap(void) 481{ 482 int i; 483 int need_local_mappings = 0; 484 485 /* Sort. */ 486again: 487 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 488 /* 489 * Keep the memory aligned on page boundary. 490 */ 491 phys_avail[i] = round_page(phys_avail[i]); 492 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 493 494 if (i < 2) 495 continue; 496 if (phys_avail[i - 2] > phys_avail[i]) { 497 vm_paddr_t ptemp[2]; 498 499 ptemp[0] = phys_avail[i + 0]; 500 ptemp[1] = phys_avail[i + 1]; 501 502 phys_avail[i + 0] = phys_avail[i - 2]; 503 phys_avail[i + 1] = phys_avail[i - 1]; 504 505 phys_avail[i - 2] = ptemp[0]; 506 phys_avail[i - 1] = ptemp[1]; 507 goto again; 508 } 509 } 510 511 /* 512 * In 32 bit, we may have memory which cannot be mapped directly. 513 * This memory will need temporary mapping before it can be 514 * accessed. 515 */ 516 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1)) 517 need_local_mappings = 1; 518 519 /* 520 * Copy the phys_avail[] array before we start stealing memory from it. 521 */ 522 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 523 physmem_desc[i] = phys_avail[i]; 524 physmem_desc[i + 1] = phys_avail[i + 1]; 525 } 526 527 Maxmem = atop(phys_avail[i - 1]); 528 529 if (bootverbose) { 530 printf("Physical memory chunk(s):\n"); 531 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 532 vm_paddr_t size; 533 534 size = phys_avail[i + 1] - phys_avail[i]; 535 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 536 (uintmax_t) phys_avail[i], 537 (uintmax_t) phys_avail[i + 1] - 1, 538 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 539 } 540 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem)); 541 } 542 /* 543 * Steal the message buffer from the beginning of memory. 544 */ 545 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize); 546 msgbufinit(msgbufp, msgbufsize); 547 548 /* 549 * Steal thread0 kstack. 550 */ 551 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 552 553 virtual_avail = VM_MIN_KERNEL_ADDRESS; 554 virtual_end = VM_MAX_KERNEL_ADDRESS; 555 556#ifdef SMP 557 /* 558 * Steal some virtual address space to map the pcpu area. 559 */ 560 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 561 pcpup = (struct pcpu *)virtual_avail; 562 virtual_avail += PAGE_SIZE * 2; 563 564 /* 565 * Initialize the wired TLB entry mapping the pcpu region for 566 * the BSP at 'pcpup'. Up until this point we were operating 567 * with the 'pcpup' for the BSP pointing to a virtual address 568 * in KSEG0 so there was no need for a TLB mapping. 569 */ 570 mips_pcpu_tlb_init(PCPU_ADDR(0)); 571 572 if (bootverbose) 573 printf("pcpu is available at virtual address %p.\n", pcpup); 574#endif 575 576 if (need_local_mappings) 577 pmap_alloc_lmem_map(); 578 pmap_create_kernel_pagetable(); 579 pmap_max_asid = VMNUM_PIDS; 580 mips_wr_entryhi(0); 581 mips_wr_pagemask(0); 582 583 /* 584 * Initialize the global pv list lock. 585 */ 586 rw_init(&pvh_global_lock, "pmap pv global"); 587} 588 589/* 590 * Initialize a vm_page's machine-dependent fields. 591 */ 592void 593pmap_page_init(vm_page_t m) 594{ 595 596 TAILQ_INIT(&m->md.pv_list); 597 m->md.pv_flags = 0; 598} 599 600/* 601 * Initialize the pmap module. 602 * Called by vm_init, to initialize any structures that the pmap 603 * system needs to map virtual memory. 604 */ 605void 606pmap_init(void) 607{ 608} 609 610/*************************************************** 611 * Low level helper routines..... 612 ***************************************************/ 613 614#ifdef SMP 615static __inline void 616pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 617{ 618 int cpuid, cpu, self; 619 cpuset_t active_cpus; 620 621 sched_pin(); 622 if (is_kernel_pmap(pmap)) { 623 smp_rendezvous(NULL, fn, NULL, arg); 624 goto out; 625 } 626 /* Force ASID update on inactive CPUs */ 627 CPU_FOREACH(cpu) { 628 if (!CPU_ISSET(cpu, &pmap->pm_active)) 629 pmap->pm_asid[cpu].gen = 0; 630 } 631 cpuid = PCPU_GET(cpuid); 632 /* 633 * XXX: barrier/locking for active? 634 * 635 * Take a snapshot of active here, any further changes are ignored. 636 * tlb update/invalidate should be harmless on inactive CPUs 637 */ 638 active_cpus = pmap->pm_active; 639 self = CPU_ISSET(cpuid, &active_cpus); 640 CPU_CLR(cpuid, &active_cpus); 641 /* Optimize for the case where this cpu is the only active one */ 642 if (CPU_EMPTY(&active_cpus)) { 643 if (self) 644 fn(arg); 645 } else { 646 if (self) 647 CPU_SET(cpuid, &active_cpus); 648 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg); 649 } 650out: 651 sched_unpin(); 652} 653#else /* !SMP */ 654static __inline void 655pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg) 656{ 657 int cpuid; 658 659 if (is_kernel_pmap(pmap)) { 660 fn(arg); 661 return; 662 } 663 cpuid = PCPU_GET(cpuid); 664 if (!CPU_ISSET(cpuid, &pmap->pm_active)) 665 pmap->pm_asid[cpuid].gen = 0; 666 else 667 fn(arg); 668} 669#endif /* SMP */ 670 671static void 672pmap_invalidate_all(pmap_t pmap) 673{ 674 675 pmap_call_on_active_cpus(pmap, 676 (void (*)(void *))tlb_invalidate_all_user, pmap); 677} 678 679struct pmap_invalidate_page_arg { 680 pmap_t pmap; 681 vm_offset_t va; 682}; 683 684static void 685pmap_invalidate_page_action(void *arg) 686{ 687 struct pmap_invalidate_page_arg *p = arg; 688 689 tlb_invalidate_address(p->pmap, p->va); 690} 691 692static void 693pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 694{ 695 struct pmap_invalidate_page_arg arg; 696 697 arg.pmap = pmap; 698 arg.va = va; 699 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg); 700} 701 702struct pmap_invalidate_range_arg { 703 pmap_t pmap; 704 vm_offset_t sva; 705 vm_offset_t eva; 706}; 707 708static void 709pmap_invalidate_range_action(void *arg) 710{ 711 struct pmap_invalidate_range_arg *p = arg; 712 713 tlb_invalidate_range(p->pmap, p->sva, p->eva); 714} 715 716static void 717pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 718{ 719 struct pmap_invalidate_range_arg arg; 720 721 arg.pmap = pmap; 722 arg.sva = sva; 723 arg.eva = eva; 724 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg); 725} 726 727struct pmap_update_page_arg { 728 pmap_t pmap; 729 vm_offset_t va; 730 pt_entry_t pte; 731}; 732 733static void 734pmap_update_page_action(void *arg) 735{ 736 struct pmap_update_page_arg *p = arg; 737 738 tlb_update(p->pmap, p->va, p->pte); 739} 740 741static void 742pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 743{ 744 struct pmap_update_page_arg arg; 745 746 arg.pmap = pmap; 747 arg.va = va; 748 arg.pte = pte; 749 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg); 750} 751 752/* 753 * Routine: pmap_extract 754 * Function: 755 * Extract the physical page address associated 756 * with the given map/virtual_address pair. 757 */ 758vm_paddr_t 759pmap_extract(pmap_t pmap, vm_offset_t va) 760{ 761 pt_entry_t *pte; 762 vm_offset_t retval = 0; 763 764 PMAP_LOCK(pmap); 765 pte = pmap_pte(pmap, va); 766 if (pte) { 767 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK); 768 } 769 PMAP_UNLOCK(pmap); 770 return (retval); 771} 772 773/* 774 * Routine: pmap_extract_and_hold 775 * Function: 776 * Atomically extract and hold the physical page 777 * with the given pmap and virtual address pair 778 * if that mapping permits the given protection. 779 */ 780vm_page_t 781pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 782{ 783 pt_entry_t pte, *ptep; 784 vm_paddr_t pa, pte_pa; 785 vm_page_t m; 786 787 m = NULL; 788 pa = 0; 789 PMAP_LOCK(pmap); 790retry: 791 ptep = pmap_pte(pmap, va); 792 if (ptep != NULL) { 793 pte = *ptep; 794 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) || 795 (prot & VM_PROT_WRITE) == 0)) { 796 pte_pa = TLBLO_PTE_TO_PA(pte); 797 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa)) 798 goto retry; 799 m = PHYS_TO_VM_PAGE(pte_pa); 800 vm_page_hold(m); 801 } 802 } 803 PA_UNLOCK_COND(pa); 804 PMAP_UNLOCK(pmap); 805 return (m); 806} 807 808/*************************************************** 809 * Low level mapping routines..... 810 ***************************************************/ 811 812/* 813 * add a wired page to the kva 814 */ 815void 816pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr) 817{ 818 pt_entry_t *pte; 819 pt_entry_t opte, npte; 820 821#ifdef PMAP_DEBUG 822 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 823#endif 824 825 pte = pmap_pte(kernel_pmap, va); 826 opte = *pte; 827 npte = TLBLO_PA_TO_PFN(pa) | attr | PTE_D | PTE_V | PTE_G; 828 *pte = npte; 829 if (pte_test(&opte, PTE_V) && opte != npte) 830 pmap_update_page(kernel_pmap, va, npte); 831} 832 833void 834pmap_kenter(vm_offset_t va, vm_paddr_t pa) 835{ 836 837 KASSERT(is_cacheable_mem(pa), 838 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa)); 839 840 pmap_kenter_attr(va, pa, PTE_C_CACHE); 841} 842 843/* 844 * remove a page from the kernel pagetables 845 */ 846 /* PMAP_INLINE */ void 847pmap_kremove(vm_offset_t va) 848{ 849 pt_entry_t *pte; 850 851 /* 852 * Write back all caches from the page being destroyed 853 */ 854 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 855 856 pte = pmap_pte(kernel_pmap, va); 857 *pte = PTE_G; 858 pmap_invalidate_page(kernel_pmap, va); 859} 860 861/* 862 * Used to map a range of physical addresses into kernel 863 * virtual address space. 864 * 865 * The value passed in '*virt' is a suggested virtual address for 866 * the mapping. Architectures which can support a direct-mapped 867 * physical to virtual region can return the appropriate address 868 * within that region, leaving '*virt' unchanged. Other 869 * architectures should map the pages starting at '*virt' and 870 * update '*virt' with the first usable address after the mapped 871 * region. 872 * 873 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 874 */ 875vm_offset_t 876pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 877{ 878 vm_offset_t va, sva; 879 880 if (MIPS_DIRECT_MAPPABLE(end - 1)) 881 return (MIPS_PHYS_TO_DIRECT(start)); 882 883 va = sva = *virt; 884 while (start < end) { 885 pmap_kenter(va, start); 886 va += PAGE_SIZE; 887 start += PAGE_SIZE; 888 } 889 *virt = va; 890 return (sva); 891} 892 893/* 894 * Add a list of wired pages to the kva 895 * this routine is only used for temporary 896 * kernel mappings that do not need to have 897 * page modification or references recorded. 898 * Note that old mappings are simply written 899 * over. The page *must* be wired. 900 */ 901void 902pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 903{ 904 int i; 905 vm_offset_t origva = va; 906 907 for (i = 0; i < count; i++) { 908 pmap_flush_pvcache(m[i]); 909 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 910 va += PAGE_SIZE; 911 } 912 913 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 914} 915 916/* 917 * this routine jerks page mappings from the 918 * kernel -- it is meant only for temporary mappings. 919 */ 920void 921pmap_qremove(vm_offset_t va, int count) 922{ 923 pt_entry_t *pte; 924 vm_offset_t origva; 925 926 if (count < 1) 927 return; 928 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count); 929 origva = va; 930 do { 931 pte = pmap_pte(kernel_pmap, va); 932 *pte = PTE_G; 933 va += PAGE_SIZE; 934 } while (--count > 0); 935 pmap_invalidate_range(kernel_pmap, origva, va); 936} 937 938/*************************************************** 939 * Page table page management routines..... 940 ***************************************************/ 941 942/* 943 * Decrements a page table page's wire count, which is used to record the 944 * number of valid page table entries within the page. If the wire count 945 * drops to zero, then the page table page is unmapped. Returns TRUE if the 946 * page table page was unmapped and FALSE otherwise. 947 */ 948static PMAP_INLINE boolean_t 949pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 950{ 951 952 --m->wire_count; 953 if (m->wire_count == 0) { 954 _pmap_unwire_ptp(pmap, va, m); 955 return (TRUE); 956 } else 957 return (FALSE); 958} 959 960static void 961_pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m) 962{ 963 pd_entry_t *pde; 964 965 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 966 /* 967 * unmap the page table page 968 */ 969#ifdef __mips_n64 970 if (m->pindex < NUPDE) 971 pde = pmap_pde(pmap, va); 972 else 973 pde = pmap_segmap(pmap, va); 974#else 975 pde = pmap_pde(pmap, va); 976#endif 977 *pde = 0; 978 pmap->pm_stats.resident_count--; 979 980#ifdef __mips_n64 981 if (m->pindex < NUPDE) { 982 pd_entry_t *pdp; 983 vm_page_t pdpg; 984 985 /* 986 * Recursively decrement next level pagetable refcount 987 */ 988 pdp = (pd_entry_t *)*pmap_segmap(pmap, va); 989 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp)); 990 pmap_unwire_ptp(pmap, va, pdpg); 991 } 992#endif 993 994 /* 995 * If the page is finally unwired, simply free it. 996 */ 997 vm_page_free_zero(m); 998 atomic_subtract_int(&cnt.v_wire_count, 1); 999} 1000 1001/* 1002 * After removing a page table entry, this routine is used to 1003 * conditionally free the page, and manage the hold/wire counts. 1004 */ 1005static int 1006pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde) 1007{ 1008 vm_page_t mpte; 1009 1010 if (va >= VM_MAXUSER_ADDRESS) 1011 return (0); 1012 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0")); 1013 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde)); 1014 return (pmap_unwire_ptp(pmap, va, mpte)); 1015} 1016 1017void 1018pmap_pinit0(pmap_t pmap) 1019{ 1020 int i; 1021 1022 PMAP_LOCK_INIT(pmap); 1023 pmap->pm_segtab = kernel_segmap; 1024 CPU_ZERO(&pmap->pm_active); 1025 for (i = 0; i < MAXCPU; i++) { 1026 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1027 pmap->pm_asid[i].gen = 0; 1028 } 1029 PCPU_SET(curpmap, pmap); 1030 TAILQ_INIT(&pmap->pm_pvchunk); 1031 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1032} 1033 1034void 1035pmap_grow_direct_page_cache() 1036{ 1037 1038#ifdef __mips_n64 1039 vm_pageout_grow_cache(3, 0, MIPS_XKPHYS_LARGEST_PHYS); 1040#else 1041 vm_pageout_grow_cache(3, 0, MIPS_KSEG0_LARGEST_PHYS); 1042#endif 1043} 1044 1045static vm_page_t 1046pmap_alloc_direct_page(unsigned int index, int req) 1047{ 1048 vm_page_t m; 1049 1050 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED | 1051 VM_ALLOC_ZERO); 1052 if (m == NULL) 1053 return (NULL); 1054 1055 if ((m->flags & PG_ZERO) == 0) 1056 pmap_zero_page(m); 1057 1058 m->pindex = index; 1059 return (m); 1060} 1061 1062/* 1063 * Initialize a preallocated and zeroed pmap structure, 1064 * such as one in a vmspace structure. 1065 */ 1066int 1067pmap_pinit(pmap_t pmap) 1068{ 1069 vm_offset_t ptdva; 1070 vm_page_t ptdpg; 1071 int i; 1072 1073 /* 1074 * allocate the page directory page 1075 */ 1076 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, VM_ALLOC_NORMAL)) == NULL) 1077 pmap_grow_direct_page_cache(); 1078 1079 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg)); 1080 pmap->pm_segtab = (pd_entry_t *)ptdva; 1081 CPU_ZERO(&pmap->pm_active); 1082 for (i = 0; i < MAXCPU; i++) { 1083 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1084 pmap->pm_asid[i].gen = 0; 1085 } 1086 TAILQ_INIT(&pmap->pm_pvchunk); 1087 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1088 1089 return (1); 1090} 1091 1092/* 1093 * this routine is called if the page table page is not 1094 * mapped correctly. 1095 */ 1096static vm_page_t 1097_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1098{ 1099 vm_offset_t pageva; 1100 vm_page_t m; 1101 1102 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1103 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1104 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1105 1106 /* 1107 * Find or fabricate a new pagetable page 1108 */ 1109 if ((m = pmap_alloc_direct_page(ptepindex, VM_ALLOC_NORMAL)) == NULL) { 1110 if (flags & M_WAITOK) { 1111 PMAP_UNLOCK(pmap); 1112 rw_wunlock(&pvh_global_lock); 1113 pmap_grow_direct_page_cache(); 1114 rw_wlock(&pvh_global_lock); 1115 PMAP_LOCK(pmap); 1116 } 1117 1118 /* 1119 * Indicate the need to retry. While waiting, the page 1120 * table page may have been allocated. 1121 */ 1122 return (NULL); 1123 } 1124 1125 /* 1126 * Map the pagetable page into the process address space, if it 1127 * isn't already there. 1128 */ 1129 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1130 1131#ifdef __mips_n64 1132 if (ptepindex >= NUPDE) { 1133 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva; 1134 } else { 1135 pd_entry_t *pdep, *pde; 1136 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT); 1137 int pdeindex = ptepindex & (NPDEPG - 1); 1138 vm_page_t pg; 1139 1140 pdep = &pmap->pm_segtab[segindex]; 1141 if (*pdep == NULL) { 1142 /* recurse for allocating page dir */ 1143 if (_pmap_allocpte(pmap, NUPDE + segindex, 1144 flags) == NULL) { 1145 /* alloc failed, release current */ 1146 --m->wire_count; 1147 atomic_subtract_int(&cnt.v_wire_count, 1); 1148 vm_page_free_zero(m); 1149 return (NULL); 1150 } 1151 } else { 1152 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep)); 1153 pg->wire_count++; 1154 } 1155 /* Next level entry */ 1156 pde = (pd_entry_t *)*pdep; 1157 pde[pdeindex] = (pd_entry_t)pageva; 1158 } 1159#else 1160 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva; 1161#endif 1162 pmap->pm_stats.resident_count++; 1163 return (m); 1164} 1165 1166static vm_page_t 1167pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1168{ 1169 unsigned ptepindex; 1170 pd_entry_t *pde; 1171 vm_page_t m; 1172 1173 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1174 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1175 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1176 1177 /* 1178 * Calculate pagetable page index 1179 */ 1180 ptepindex = pmap_pde_pindex(va); 1181retry: 1182 /* 1183 * Get the page directory entry 1184 */ 1185 pde = pmap_pde(pmap, va); 1186 1187 /* 1188 * If the page table page is mapped, we just increment the hold 1189 * count, and activate it. 1190 */ 1191 if (pde != NULL && *pde != NULL) { 1192 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde)); 1193 m->wire_count++; 1194 } else { 1195 /* 1196 * Here if the pte page isn't mapped, or if it has been 1197 * deallocated. 1198 */ 1199 m = _pmap_allocpte(pmap, ptepindex, flags); 1200 if (m == NULL && (flags & M_WAITOK)) 1201 goto retry; 1202 } 1203 return (m); 1204} 1205 1206 1207/*************************************************** 1208 * Pmap allocation/deallocation routines. 1209 ***************************************************/ 1210 1211/* 1212 * Release any resources held by the given physical map. 1213 * Called when a pmap initialized by pmap_pinit is being released. 1214 * Should only be called if the map contains no valid mappings. 1215 */ 1216void 1217pmap_release(pmap_t pmap) 1218{ 1219 vm_offset_t ptdva; 1220 vm_page_t ptdpg; 1221 1222 KASSERT(pmap->pm_stats.resident_count == 0, 1223 ("pmap_release: pmap resident count %ld != 0", 1224 pmap->pm_stats.resident_count)); 1225 1226 ptdva = (vm_offset_t)pmap->pm_segtab; 1227 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva)); 1228 1229 ptdpg->wire_count--; 1230 atomic_subtract_int(&cnt.v_wire_count, 1); 1231 vm_page_free_zero(ptdpg); 1232} 1233 1234/* 1235 * grow the number of kernel page table entries, if needed 1236 */ 1237void 1238pmap_growkernel(vm_offset_t addr) 1239{ 1240 vm_page_t nkpg; 1241 pd_entry_t *pde, *pdpe; 1242 pt_entry_t *pte; 1243 int i; 1244 1245 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1246 addr = roundup2(addr, NBSEG); 1247 if (addr - 1 >= kernel_map->max_offset) 1248 addr = kernel_map->max_offset; 1249 while (kernel_vm_end < addr) { 1250 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end); 1251#ifdef __mips_n64 1252 if (*pdpe == 0) { 1253 /* new intermediate page table entry */ 1254 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT); 1255 if (nkpg == NULL) 1256 panic("pmap_growkernel: no memory to grow kernel"); 1257 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1258 continue; /* try again */ 1259 } 1260#endif 1261 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end); 1262 if (*pde != 0) { 1263 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1264 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1265 kernel_vm_end = kernel_map->max_offset; 1266 break; 1267 } 1268 continue; 1269 } 1270 1271 /* 1272 * This index is bogus, but out of the way 1273 */ 1274 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT); 1275 if (!nkpg) 1276 panic("pmap_growkernel: no memory to grow kernel"); 1277 nkpt++; 1278 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg)); 1279 1280 /* 1281 * The R[4-7]?00 stores only one copy of the Global bit in 1282 * the translation lookaside buffer for each 2 page entry. 1283 * Thus invalid entrys must have the Global bit set so when 1284 * Entry LO and Entry HI G bits are anded together they will 1285 * produce a global bit to store in the tlb. 1286 */ 1287 pte = (pt_entry_t *)*pde; 1288 for (i = 0; i < NPTEPG; i++) 1289 pte[i] = PTE_G; 1290 1291 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 1292 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1293 kernel_vm_end = kernel_map->max_offset; 1294 break; 1295 } 1296 } 1297} 1298 1299/*************************************************** 1300 * page management routines. 1301 ***************************************************/ 1302 1303CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1304#ifdef __mips_n64 1305CTASSERT(_NPCM == 3); 1306CTASSERT(_NPCPV == 168); 1307#else 1308CTASSERT(_NPCM == 11); 1309CTASSERT(_NPCPV == 336); 1310#endif 1311 1312static __inline struct pv_chunk * 1313pv_to_chunk(pv_entry_t pv) 1314{ 1315 1316 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1317} 1318 1319#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1320 1321#ifdef __mips_n64 1322#define PC_FREE0_1 0xfffffffffffffffful 1323#define PC_FREE2 0x000000fffffffffful 1324#else 1325#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 1326#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 1327#endif 1328 1329static const u_long pc_freemask[_NPCM] = { 1330#ifdef __mips_n64 1331 PC_FREE0_1, PC_FREE0_1, PC_FREE2 1332#else 1333 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1334 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1335 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 1336 PC_FREE0_9, PC_FREE10 1337#endif 1338}; 1339 1340static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 1341 1342SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1343 "Current number of pv entries"); 1344 1345#ifdef PV_STATS 1346static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1347 1348SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1349 "Current number of pv entry chunks"); 1350SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1351 "Current number of pv entry chunks allocated"); 1352SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1353 "Current number of pv entry chunks frees"); 1354SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1355 "Number of times tried to get a chunk page but failed."); 1356 1357static long pv_entry_frees, pv_entry_allocs; 1358static int pv_entry_spare; 1359 1360SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1361 "Current number of pv entry frees"); 1362SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1363 "Current number of pv entry allocs"); 1364SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1365 "Current number of spare pv entries"); 1366#endif 1367 1368/* 1369 * We are in a serious low memory condition. Resort to 1370 * drastic measures to free some pages so we can allocate 1371 * another pv entry chunk. 1372 */ 1373static vm_page_t 1374pmap_pv_reclaim(pmap_t locked_pmap) 1375{ 1376 struct pch newtail; 1377 struct pv_chunk *pc; 1378 pd_entry_t *pde; 1379 pmap_t pmap; 1380 pt_entry_t *pte, oldpte; 1381 pv_entry_t pv; 1382 vm_offset_t va; 1383 vm_page_t m, m_pc; 1384 u_long inuse; 1385 int bit, field, freed, idx; 1386 1387 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1388 pmap = NULL; 1389 m_pc = NULL; 1390 TAILQ_INIT(&newtail); 1391 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) { 1392 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1393 if (pmap != pc->pc_pmap) { 1394 if (pmap != NULL) { 1395 pmap_invalidate_all(pmap); 1396 if (pmap != locked_pmap) 1397 PMAP_UNLOCK(pmap); 1398 } 1399 pmap = pc->pc_pmap; 1400 /* Avoid deadlock and lock recursion. */ 1401 if (pmap > locked_pmap) 1402 PMAP_LOCK(pmap); 1403 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 1404 pmap = NULL; 1405 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1406 continue; 1407 } 1408 } 1409 1410 /* 1411 * Destroy every non-wired, 4 KB page mapping in the chunk. 1412 */ 1413 freed = 0; 1414 for (field = 0; field < _NPCM; field++) { 1415 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 1416 inuse != 0; inuse &= ~(1UL << bit)) { 1417 bit = ffsl(inuse) - 1; 1418 idx = field * sizeof(inuse) * NBBY + bit; 1419 pv = &pc->pc_pventry[idx]; 1420 va = pv->pv_va; 1421 pde = pmap_pde(pmap, va); 1422 KASSERT(pde != NULL && *pde != 0, 1423 ("pmap_pv_reclaim: pde")); 1424 pte = pmap_pde_to_pte(pde, va); 1425 oldpte = *pte; 1426 if (pte_test(&oldpte, PTE_W)) 1427 continue; 1428 if (is_kernel_pmap(pmap)) 1429 *pte = PTE_G; 1430 else 1431 *pte = 0; 1432 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte)); 1433 if (pte_test(&oldpte, PTE_D)) 1434 vm_page_dirty(m); 1435 if (m->md.pv_flags & PV_TABLE_REF) 1436 vm_page_aflag_set(m, PGA_REFERENCED); 1437 m->md.pv_flags &= ~PV_TABLE_REF; 1438 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1439 if (TAILQ_EMPTY(&m->md.pv_list)) 1440 vm_page_aflag_clear(m, PGA_WRITEABLE); 1441 pc->pc_map[field] |= 1UL << bit; 1442 pmap_unuse_pt(pmap, va, *pde); 1443 freed++; 1444 } 1445 } 1446 if (freed == 0) { 1447 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1448 continue; 1449 } 1450 /* Every freed mapping is for a 4 KB page. */ 1451 pmap->pm_stats.resident_count -= freed; 1452 PV_STAT(pv_entry_frees += freed); 1453 PV_STAT(pv_entry_spare += freed); 1454 pv_entry_count -= freed; 1455 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1456 for (field = 0; field < _NPCM; field++) 1457 if (pc->pc_map[field] != pc_freemask[field]) { 1458 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1459 pc_list); 1460 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 1461 1462 /* 1463 * One freed pv entry in locked_pmap is 1464 * sufficient. 1465 */ 1466 if (pmap == locked_pmap) 1467 goto out; 1468 break; 1469 } 1470 if (field == _NPCM) { 1471 PV_STAT(pv_entry_spare -= _NPCPV); 1472 PV_STAT(pc_chunk_count--); 1473 PV_STAT(pc_chunk_frees++); 1474 /* Entire chunk is free; return it. */ 1475 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS( 1476 (vm_offset_t)pc)); 1477 break; 1478 } 1479 } 1480out: 1481 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 1482 if (pmap != NULL) { 1483 pmap_invalidate_all(pmap); 1484 if (pmap != locked_pmap) 1485 PMAP_UNLOCK(pmap); 1486 } 1487 return (m_pc); 1488} 1489 1490/* 1491 * free the pv_entry back to the free list 1492 */ 1493static void 1494free_pv_entry(pmap_t pmap, pv_entry_t pv) 1495{ 1496 struct pv_chunk *pc; 1497 int bit, field, idx; 1498 1499 rw_assert(&pvh_global_lock, RA_WLOCKED); 1500 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1501 PV_STAT(pv_entry_frees++); 1502 PV_STAT(pv_entry_spare++); 1503 pv_entry_count--; 1504 pc = pv_to_chunk(pv); 1505 idx = pv - &pc->pc_pventry[0]; 1506 field = idx / (sizeof(u_long) * NBBY); 1507 bit = idx % (sizeof(u_long) * NBBY); 1508 pc->pc_map[field] |= 1ul << bit; 1509 for (idx = 0; idx < _NPCM; idx++) 1510 if (pc->pc_map[idx] != pc_freemask[idx]) { 1511 /* 1512 * 98% of the time, pc is already at the head of the 1513 * list. If it isn't already, move it to the head. 1514 */ 1515 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 1516 pc)) { 1517 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1518 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 1519 pc_list); 1520 } 1521 return; 1522 } 1523 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1524 free_pv_chunk(pc); 1525} 1526 1527static void 1528free_pv_chunk(struct pv_chunk *pc) 1529{ 1530 vm_page_t m; 1531 1532 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1533 PV_STAT(pv_entry_spare -= _NPCPV); 1534 PV_STAT(pc_chunk_count--); 1535 PV_STAT(pc_chunk_frees++); 1536 /* entire chunk is free, return it */ 1537 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc)); 1538 vm_page_unwire(m, 0); 1539 vm_page_free(m); 1540} 1541 1542/* 1543 * get a new pv_entry, allocating a block from the system 1544 * when needed. 1545 */ 1546static pv_entry_t 1547get_pv_entry(pmap_t pmap, boolean_t try) 1548{ 1549 struct pv_chunk *pc; 1550 pv_entry_t pv; 1551 vm_page_t m; 1552 int bit, field, idx; 1553 1554 rw_assert(&pvh_global_lock, RA_WLOCKED); 1555 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1556 PV_STAT(pv_entry_allocs++); 1557 pv_entry_count++; 1558retry: 1559 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 1560 if (pc != NULL) { 1561 for (field = 0; field < _NPCM; field++) { 1562 if (pc->pc_map[field]) { 1563 bit = ffsl(pc->pc_map[field]) - 1; 1564 break; 1565 } 1566 } 1567 if (field < _NPCM) { 1568 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit; 1569 pv = &pc->pc_pventry[idx]; 1570 pc->pc_map[field] &= ~(1ul << bit); 1571 /* If this was the last item, move it to tail */ 1572 for (field = 0; field < _NPCM; field++) 1573 if (pc->pc_map[field] != 0) { 1574 PV_STAT(pv_entry_spare--); 1575 return (pv); /* not full, return */ 1576 } 1577 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1578 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 1579 PV_STAT(pv_entry_spare--); 1580 return (pv); 1581 } 1582 } 1583 /* No free items, allocate another chunk */ 1584 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL | 1585 VM_ALLOC_WIRED); 1586 if (m == NULL) { 1587 if (try) { 1588 pv_entry_count--; 1589 PV_STAT(pc_chunk_tryfail++); 1590 return (NULL); 1591 } 1592 m = pmap_pv_reclaim(pmap); 1593 if (m == NULL) 1594 goto retry; 1595 } 1596 PV_STAT(pc_chunk_count++); 1597 PV_STAT(pc_chunk_allocs++); 1598 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m)); 1599 pc->pc_pmap = pmap; 1600 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 1601 for (field = 1; field < _NPCM; field++) 1602 pc->pc_map[field] = pc_freemask[field]; 1603 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 1604 pv = &pc->pc_pventry[0]; 1605 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1606 PV_STAT(pv_entry_spare += _NPCPV - 1); 1607 return (pv); 1608} 1609 1610static pv_entry_t 1611pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1612{ 1613 pv_entry_t pv; 1614 1615 rw_assert(&pvh_global_lock, RA_WLOCKED); 1616 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 1617 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 1618 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 1619 break; 1620 } 1621 } 1622 return (pv); 1623} 1624 1625static void 1626pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1627{ 1628 pv_entry_t pv; 1629 1630 pv = pmap_pvh_remove(pvh, pmap, va); 1631 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx", 1632 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)), 1633 (u_long)va)); 1634 free_pv_entry(pmap, pv); 1635} 1636 1637static void 1638pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1639{ 1640 1641 rw_assert(&pvh_global_lock, RA_WLOCKED); 1642 pmap_pvh_free(&m->md, pmap, va); 1643 if (TAILQ_EMPTY(&m->md.pv_list)) 1644 vm_page_aflag_clear(m, PGA_WRITEABLE); 1645} 1646 1647/* 1648 * Conditionally create a pv entry. 1649 */ 1650static boolean_t 1651pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1652 vm_page_t m) 1653{ 1654 pv_entry_t pv; 1655 1656 rw_assert(&pvh_global_lock, RA_WLOCKED); 1657 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1658 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) { 1659 pv->pv_va = va; 1660 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1661 return (TRUE); 1662 } else 1663 return (FALSE); 1664} 1665 1666/* 1667 * pmap_remove_pte: do the things to unmap a page in a process 1668 */ 1669static int 1670pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va, 1671 pd_entry_t pde) 1672{ 1673 pt_entry_t oldpte; 1674 vm_page_t m; 1675 vm_paddr_t pa; 1676 1677 rw_assert(&pvh_global_lock, RA_WLOCKED); 1678 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1679 1680 /* 1681 * Write back all cache lines from the page being unmapped. 1682 */ 1683 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1684 1685 oldpte = *ptq; 1686 if (is_kernel_pmap(pmap)) 1687 *ptq = PTE_G; 1688 else 1689 *ptq = 0; 1690 1691 if (pte_test(&oldpte, PTE_W)) 1692 pmap->pm_stats.wired_count -= 1; 1693 1694 pmap->pm_stats.resident_count -= 1; 1695 1696 if (pte_test(&oldpte, PTE_MANAGED)) { 1697 pa = TLBLO_PTE_TO_PA(oldpte); 1698 m = PHYS_TO_VM_PAGE(pa); 1699 if (pte_test(&oldpte, PTE_D)) { 1700 KASSERT(!pte_test(&oldpte, PTE_RO), 1701 ("%s: modified page not writable: va: %p, pte: %#jx", 1702 __func__, (void *)va, (uintmax_t)oldpte)); 1703 vm_page_dirty(m); 1704 } 1705 if (m->md.pv_flags & PV_TABLE_REF) 1706 vm_page_aflag_set(m, PGA_REFERENCED); 1707 m->md.pv_flags &= ~PV_TABLE_REF; 1708 1709 pmap_remove_entry(pmap, m, va); 1710 } 1711 return (pmap_unuse_pt(pmap, va, pde)); 1712} 1713 1714/* 1715 * Remove a single page from a process address space 1716 */ 1717static void 1718pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1719{ 1720 pd_entry_t *pde; 1721 pt_entry_t *ptq; 1722 1723 rw_assert(&pvh_global_lock, RA_WLOCKED); 1724 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1725 pde = pmap_pde(pmap, va); 1726 if (pde == NULL || *pde == 0) 1727 return; 1728 ptq = pmap_pde_to_pte(pde, va); 1729 1730 /* 1731 * If there is no pte for this address, just skip it! 1732 */ 1733 if (!pte_test(ptq, PTE_V)) 1734 return; 1735 1736 (void)pmap_remove_pte(pmap, ptq, va, *pde); 1737 pmap_invalidate_page(pmap, va); 1738} 1739 1740/* 1741 * Remove the given range of addresses from the specified map. 1742 * 1743 * It is assumed that the start and end are properly 1744 * rounded to the page size. 1745 */ 1746void 1747pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1748{ 1749 pd_entry_t *pde, *pdpe; 1750 pt_entry_t *pte; 1751 vm_offset_t va, va_next; 1752 1753 /* 1754 * Perform an unsynchronized read. This is, however, safe. 1755 */ 1756 if (pmap->pm_stats.resident_count == 0) 1757 return; 1758 1759 rw_wlock(&pvh_global_lock); 1760 PMAP_LOCK(pmap); 1761 1762 /* 1763 * special handling of removing one page. a very common operation 1764 * and easy to short circuit some code. 1765 */ 1766 if ((sva + PAGE_SIZE) == eva) { 1767 pmap_remove_page(pmap, sva); 1768 goto out; 1769 } 1770 for (; sva < eva; sva = va_next) { 1771 pdpe = pmap_segmap(pmap, sva); 1772#ifdef __mips_n64 1773 if (*pdpe == 0) { 1774 va_next = (sva + NBSEG) & ~SEGMASK; 1775 if (va_next < sva) 1776 va_next = eva; 1777 continue; 1778 } 1779#endif 1780 va_next = (sva + NBPDR) & ~PDRMASK; 1781 if (va_next < sva) 1782 va_next = eva; 1783 1784 pde = pmap_pdpe_to_pde(pdpe, sva); 1785 if (*pde == NULL) 1786 continue; 1787 1788 /* 1789 * Limit our scan to either the end of the va represented 1790 * by the current page table page, or to the end of the 1791 * range being removed. 1792 */ 1793 if (va_next > eva) 1794 va_next = eva; 1795 1796 va = va_next; 1797 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1798 sva += PAGE_SIZE) { 1799 if (!pte_test(pte, PTE_V)) { 1800 if (va != va_next) { 1801 pmap_invalidate_range(pmap, va, sva); 1802 va = va_next; 1803 } 1804 continue; 1805 } 1806 if (va == va_next) 1807 va = sva; 1808 if (pmap_remove_pte(pmap, pte, sva, *pde)) { 1809 sva += PAGE_SIZE; 1810 break; 1811 } 1812 } 1813 if (va != va_next) 1814 pmap_invalidate_range(pmap, va, sva); 1815 } 1816out: 1817 rw_wunlock(&pvh_global_lock); 1818 PMAP_UNLOCK(pmap); 1819} 1820 1821/* 1822 * Routine: pmap_remove_all 1823 * Function: 1824 * Removes this physical page from 1825 * all physical maps in which it resides. 1826 * Reflects back modify bits to the pager. 1827 * 1828 * Notes: 1829 * Original versions of this routine were very 1830 * inefficient because they iteratively called 1831 * pmap_remove (slow...) 1832 */ 1833 1834void 1835pmap_remove_all(vm_page_t m) 1836{ 1837 pv_entry_t pv; 1838 pmap_t pmap; 1839 pd_entry_t *pde; 1840 pt_entry_t *pte, tpte; 1841 1842 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 1843 ("pmap_remove_all: page %p is not managed", m)); 1844 rw_wlock(&pvh_global_lock); 1845 1846 if (m->md.pv_flags & PV_TABLE_REF) 1847 vm_page_aflag_set(m, PGA_REFERENCED); 1848 1849 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1850 pmap = PV_PMAP(pv); 1851 PMAP_LOCK(pmap); 1852 1853 /* 1854 * If it's last mapping writeback all caches from 1855 * the page being destroyed 1856 */ 1857 if (TAILQ_NEXT(pv, pv_list) == NULL) 1858 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1859 1860 pmap->pm_stats.resident_count--; 1861 1862 pde = pmap_pde(pmap, pv->pv_va); 1863 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde")); 1864 pte = pmap_pde_to_pte(pde, pv->pv_va); 1865 1866 tpte = *pte; 1867 if (is_kernel_pmap(pmap)) 1868 *pte = PTE_G; 1869 else 1870 *pte = 0; 1871 1872 if (pte_test(&tpte, PTE_W)) 1873 pmap->pm_stats.wired_count--; 1874 1875 /* 1876 * Update the vm_page_t clean and reference bits. 1877 */ 1878 if (pte_test(&tpte, PTE_D)) { 1879 KASSERT(!pte_test(&tpte, PTE_RO), 1880 ("%s: modified page not writable: va: %p, pte: %#jx", 1881 __func__, (void *)pv->pv_va, (uintmax_t)tpte)); 1882 vm_page_dirty(m); 1883 } 1884 pmap_invalidate_page(pmap, pv->pv_va); 1885 1886 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1887 pmap_unuse_pt(pmap, pv->pv_va, *pde); 1888 free_pv_entry(pmap, pv); 1889 PMAP_UNLOCK(pmap); 1890 } 1891 1892 vm_page_aflag_clear(m, PGA_WRITEABLE); 1893 m->md.pv_flags &= ~PV_TABLE_REF; 1894 rw_wunlock(&pvh_global_lock); 1895} 1896 1897/* 1898 * Set the physical protection on the 1899 * specified range of this map as requested. 1900 */ 1901void 1902pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1903{ 1904 pt_entry_t pbits, *pte; 1905 pd_entry_t *pde, *pdpe; 1906 vm_offset_t va, va_next; 1907 vm_paddr_t pa; 1908 vm_page_t m; 1909 1910 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1911 pmap_remove(pmap, sva, eva); 1912 return; 1913 } 1914 if (prot & VM_PROT_WRITE) 1915 return; 1916 1917 PMAP_LOCK(pmap); 1918 for (; sva < eva; sva = va_next) { 1919 pdpe = pmap_segmap(pmap, sva); 1920#ifdef __mips_n64 1921 if (*pdpe == 0) { 1922 va_next = (sva + NBSEG) & ~SEGMASK; 1923 if (va_next < sva) 1924 va_next = eva; 1925 continue; 1926 } 1927#endif 1928 va_next = (sva + NBPDR) & ~PDRMASK; 1929 if (va_next < sva) 1930 va_next = eva; 1931 1932 pde = pmap_pdpe_to_pde(pdpe, sva); 1933 if (*pde == NULL) 1934 continue; 1935 1936 /* 1937 * Limit our scan to either the end of the va represented 1938 * by the current page table page, or to the end of the 1939 * range being write protected. 1940 */ 1941 if (va_next > eva) 1942 va_next = eva; 1943 1944 va = va_next; 1945 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 1946 sva += PAGE_SIZE) { 1947 pbits = *pte; 1948 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits, 1949 PTE_RO)) { 1950 if (va != va_next) { 1951 pmap_invalidate_range(pmap, va, sva); 1952 va = va_next; 1953 } 1954 continue; 1955 } 1956 pte_set(&pbits, PTE_RO); 1957 if (pte_test(&pbits, PTE_D)) { 1958 pte_clear(&pbits, PTE_D); 1959 if (pte_test(&pbits, PTE_MANAGED)) { 1960 pa = TLBLO_PTE_TO_PA(pbits); 1961 m = PHYS_TO_VM_PAGE(pa); 1962 vm_page_dirty(m); 1963 } 1964 if (va == va_next) 1965 va = sva; 1966 } else { 1967 /* 1968 * Unless PTE_D is set, any TLB entries 1969 * mapping "sva" don't allow write access, so 1970 * they needn't be invalidated. 1971 */ 1972 if (va != va_next) { 1973 pmap_invalidate_range(pmap, va, sva); 1974 va = va_next; 1975 } 1976 } 1977 *pte = pbits; 1978 } 1979 if (va != va_next) 1980 pmap_invalidate_range(pmap, va, sva); 1981 } 1982 PMAP_UNLOCK(pmap); 1983} 1984 1985/* 1986 * Insert the given physical page (p) at 1987 * the specified virtual address (v) in the 1988 * target physical map with the protection requested. 1989 * 1990 * If specified, the page will be wired down, meaning 1991 * that the related pte can not be reclaimed. 1992 * 1993 * NB: This is the only routine which MAY NOT lazy-evaluate 1994 * or lose information. That is, this routine must actually 1995 * insert this page into the given map NOW. 1996 */ 1997void 1998pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1999 vm_prot_t prot, boolean_t wired) 2000{ 2001 vm_paddr_t pa, opa; 2002 pt_entry_t *pte; 2003 pt_entry_t origpte, newpte; 2004 pv_entry_t pv; 2005 vm_page_t mpte, om; 2006 2007 va &= ~PAGE_MASK; 2008 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 2009 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva || 2010 va >= kmi.clean_eva, 2011 ("pmap_enter: managed mapping within the clean submap")); 2012 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || vm_page_xbusied(m), 2013 ("pmap_enter: page %p is not busy", m)); 2014 pa = VM_PAGE_TO_PHYS(m); 2015 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, access, prot); 2016 if (wired) 2017 newpte |= PTE_W; 2018 if (is_kernel_pmap(pmap)) 2019 newpte |= PTE_G; 2020 if (is_cacheable_mem(pa)) 2021 newpte |= PTE_C_CACHE; 2022 else 2023 newpte |= PTE_C_UNCACHED; 2024 2025 mpte = NULL; 2026 2027 rw_wlock(&pvh_global_lock); 2028 PMAP_LOCK(pmap); 2029 2030 /* 2031 * In the case that a page table page is not resident, we are 2032 * creating it here. 2033 */ 2034 if (va < VM_MAXUSER_ADDRESS) { 2035 mpte = pmap_allocpte(pmap, va, M_WAITOK); 2036 } 2037 pte = pmap_pte(pmap, va); 2038 2039 /* 2040 * Page Directory table entry not valid, we need a new PT page 2041 */ 2042 if (pte == NULL) { 2043 panic("pmap_enter: invalid page directory, pdir=%p, va=%p", 2044 (void *)pmap->pm_segtab, (void *)va); 2045 } 2046 om = NULL; 2047 origpte = *pte; 2048 opa = TLBLO_PTE_TO_PA(origpte); 2049 2050 /* 2051 * Mapping has not changed, must be protection or wiring change. 2052 */ 2053 if (pte_test(&origpte, PTE_V) && opa == pa) { 2054 /* 2055 * Wiring change, just update stats. We don't worry about 2056 * wiring PT pages as they remain resident as long as there 2057 * are valid mappings in them. Hence, if a user page is 2058 * wired, the PT page will be also. 2059 */ 2060 if (wired && !pte_test(&origpte, PTE_W)) 2061 pmap->pm_stats.wired_count++; 2062 else if (!wired && pte_test(&origpte, PTE_W)) 2063 pmap->pm_stats.wired_count--; 2064 2065 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO), 2066 ("%s: modified page not writable: va: %p, pte: %#jx", 2067 __func__, (void *)va, (uintmax_t)origpte)); 2068 2069 /* 2070 * Remove extra pte reference 2071 */ 2072 if (mpte) 2073 mpte->wire_count--; 2074 2075 if (pte_test(&origpte, PTE_MANAGED)) { 2076 m->md.pv_flags |= PV_TABLE_REF; 2077 om = m; 2078 newpte |= PTE_MANAGED; 2079 if (!pte_test(&newpte, PTE_RO)) 2080 vm_page_aflag_set(m, PGA_WRITEABLE); 2081 } 2082 goto validate; 2083 } 2084 2085 pv = NULL; 2086 2087 /* 2088 * Mapping has changed, invalidate old range and fall through to 2089 * handle validating new mapping. 2090 */ 2091 if (opa) { 2092 if (pte_test(&origpte, PTE_W)) 2093 pmap->pm_stats.wired_count--; 2094 2095 if (pte_test(&origpte, PTE_MANAGED)) { 2096 om = PHYS_TO_VM_PAGE(opa); 2097 pv = pmap_pvh_remove(&om->md, pmap, va); 2098 } 2099 if (mpte != NULL) { 2100 mpte->wire_count--; 2101 KASSERT(mpte->wire_count > 0, 2102 ("pmap_enter: missing reference to page table page," 2103 " va: %p", (void *)va)); 2104 } 2105 } else 2106 pmap->pm_stats.resident_count++; 2107 2108 /* 2109 * Enter on the PV list if part of our managed memory. 2110 */ 2111 if ((m->oflags & VPO_UNMANAGED) == 0) { 2112 m->md.pv_flags |= PV_TABLE_REF; 2113 if (pv == NULL) 2114 pv = get_pv_entry(pmap, FALSE); 2115 pv->pv_va = va; 2116 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 2117 newpte |= PTE_MANAGED; 2118 if (!pte_test(&newpte, PTE_RO)) 2119 vm_page_aflag_set(m, PGA_WRITEABLE); 2120 } else if (pv != NULL) 2121 free_pv_entry(pmap, pv); 2122 2123 /* 2124 * Increment counters 2125 */ 2126 if (wired) 2127 pmap->pm_stats.wired_count++; 2128 2129validate: 2130 2131#ifdef PMAP_DEBUG 2132 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa); 2133#endif 2134 2135 /* 2136 * if the mapping or permission bits are different, we need to 2137 * update the pte. 2138 */ 2139 if (origpte != newpte) { 2140 *pte = newpte; 2141 if (pte_test(&origpte, PTE_V)) { 2142 if (pte_test(&origpte, PTE_MANAGED) && opa != pa) { 2143 if (om->md.pv_flags & PV_TABLE_REF) 2144 vm_page_aflag_set(om, PGA_REFERENCED); 2145 om->md.pv_flags &= ~PV_TABLE_REF; 2146 } 2147 if (pte_test(&origpte, PTE_D)) { 2148 KASSERT(!pte_test(&origpte, PTE_RO), 2149 ("pmap_enter: modified page not writable:" 2150 " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte)); 2151 if (pte_test(&origpte, PTE_MANAGED)) 2152 vm_page_dirty(om); 2153 } 2154 if (pte_test(&origpte, PTE_MANAGED) && 2155 TAILQ_EMPTY(&om->md.pv_list)) 2156 vm_page_aflag_clear(om, PGA_WRITEABLE); 2157 pmap_update_page(pmap, va, newpte); 2158 } 2159 } 2160 2161 /* 2162 * Sync I & D caches for executable pages. Do this only if the 2163 * target pmap belongs to the current process. Otherwise, an 2164 * unresolvable TLB miss may occur. 2165 */ 2166 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 2167 (prot & VM_PROT_EXECUTE)) { 2168 mips_icache_sync_range(va, PAGE_SIZE); 2169 mips_dcache_wbinv_range(va, PAGE_SIZE); 2170 } 2171 rw_wunlock(&pvh_global_lock); 2172 PMAP_UNLOCK(pmap); 2173} 2174 2175/* 2176 * this code makes some *MAJOR* assumptions: 2177 * 1. Current pmap & pmap exists. 2178 * 2. Not wired. 2179 * 3. Read access. 2180 * 4. No page table pages. 2181 * but is *MUCH* faster than pmap_enter... 2182 */ 2183 2184void 2185pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2186{ 2187 2188 rw_wlock(&pvh_global_lock); 2189 PMAP_LOCK(pmap); 2190 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 2191 rw_wunlock(&pvh_global_lock); 2192 PMAP_UNLOCK(pmap); 2193} 2194 2195static vm_page_t 2196pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 2197 vm_prot_t prot, vm_page_t mpte) 2198{ 2199 pt_entry_t *pte; 2200 vm_paddr_t pa; 2201 2202 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2203 (m->oflags & VPO_UNMANAGED) != 0, 2204 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2205 rw_assert(&pvh_global_lock, RA_WLOCKED); 2206 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2207 2208 /* 2209 * In the case that a page table page is not resident, we are 2210 * creating it here. 2211 */ 2212 if (va < VM_MAXUSER_ADDRESS) { 2213 pd_entry_t *pde; 2214 unsigned ptepindex; 2215 2216 /* 2217 * Calculate pagetable page index 2218 */ 2219 ptepindex = pmap_pde_pindex(va); 2220 if (mpte && (mpte->pindex == ptepindex)) { 2221 mpte->wire_count++; 2222 } else { 2223 /* 2224 * Get the page directory entry 2225 */ 2226 pde = pmap_pde(pmap, va); 2227 2228 /* 2229 * If the page table page is mapped, we just 2230 * increment the hold count, and activate it. 2231 */ 2232 if (pde && *pde != 0) { 2233 mpte = PHYS_TO_VM_PAGE( 2234 MIPS_DIRECT_TO_PHYS(*pde)); 2235 mpte->wire_count++; 2236 } else { 2237 mpte = _pmap_allocpte(pmap, ptepindex, 2238 M_NOWAIT); 2239 if (mpte == NULL) 2240 return (mpte); 2241 } 2242 } 2243 } else { 2244 mpte = NULL; 2245 } 2246 2247 pte = pmap_pte(pmap, va); 2248 if (pte_test(pte, PTE_V)) { 2249 if (mpte != NULL) { 2250 mpte->wire_count--; 2251 mpte = NULL; 2252 } 2253 return (mpte); 2254 } 2255 2256 /* 2257 * Enter on the PV list if part of our managed memory. 2258 */ 2259 if ((m->oflags & VPO_UNMANAGED) == 0 && 2260 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2261 if (mpte != NULL) { 2262 pmap_unwire_ptp(pmap, va, mpte); 2263 mpte = NULL; 2264 } 2265 return (mpte); 2266 } 2267 2268 /* 2269 * Increment counters 2270 */ 2271 pmap->pm_stats.resident_count++; 2272 2273 pa = VM_PAGE_TO_PHYS(m); 2274 2275 /* 2276 * Now validate mapping with RO protection 2277 */ 2278 *pte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V; 2279 if ((m->oflags & VPO_UNMANAGED) == 0) 2280 *pte |= PTE_MANAGED; 2281 2282 if (is_cacheable_mem(pa)) 2283 *pte |= PTE_C_CACHE; 2284 else 2285 *pte |= PTE_C_UNCACHED; 2286 2287 if (is_kernel_pmap(pmap)) 2288 *pte |= PTE_G; 2289 else { 2290 /* 2291 * Sync I & D caches. Do this only if the target pmap 2292 * belongs to the current process. Otherwise, an 2293 * unresolvable TLB miss may occur. */ 2294 if (pmap == &curproc->p_vmspace->vm_pmap) { 2295 va &= ~PAGE_MASK; 2296 mips_icache_sync_range(va, PAGE_SIZE); 2297 mips_dcache_wbinv_range(va, PAGE_SIZE); 2298 } 2299 } 2300 return (mpte); 2301} 2302 2303/* 2304 * Make a temporary mapping for a physical address. This is only intended 2305 * to be used for panic dumps. 2306 * 2307 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2308 */ 2309void * 2310pmap_kenter_temporary(vm_paddr_t pa, int i) 2311{ 2312 vm_offset_t va; 2313 2314 if (i != 0) 2315 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2316 __func__); 2317 2318 if (MIPS_DIRECT_MAPPABLE(pa)) { 2319 va = MIPS_PHYS_TO_DIRECT(pa); 2320 } else { 2321#ifndef __mips_n64 /* XXX : to be converted to new style */ 2322 int cpu; 2323 register_t intr; 2324 struct local_sysmaps *sysm; 2325 pt_entry_t *pte, npte; 2326 2327 /* If this is used other than for dumps, we may need to leave 2328 * interrupts disasbled on return. If crash dumps don't work when 2329 * we get to this point, we might want to consider this (leaving things 2330 * disabled as a starting point ;-) 2331 */ 2332 intr = intr_disable(); 2333 cpu = PCPU_GET(cpuid); 2334 sysm = &sysmap_lmem[cpu]; 2335 /* Since this is for the debugger, no locks or any other fun */ 2336 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V | 2337 PTE_G; 2338 pte = pmap_pte(kernel_pmap, sysm->base); 2339 *pte = npte; 2340 sysm->valid1 = 1; 2341 pmap_update_page(kernel_pmap, sysm->base, npte); 2342 va = sysm->base; 2343 intr_restore(intr); 2344#endif 2345 } 2346 return ((void *)va); 2347} 2348 2349void 2350pmap_kenter_temporary_free(vm_paddr_t pa) 2351{ 2352#ifndef __mips_n64 /* XXX : to be converted to new style */ 2353 int cpu; 2354 register_t intr; 2355 struct local_sysmaps *sysm; 2356#endif 2357 2358 if (MIPS_DIRECT_MAPPABLE(pa)) { 2359 /* nothing to do for this case */ 2360 return; 2361 } 2362#ifndef __mips_n64 /* XXX : to be converted to new style */ 2363 cpu = PCPU_GET(cpuid); 2364 sysm = &sysmap_lmem[cpu]; 2365 if (sysm->valid1) { 2366 pt_entry_t *pte; 2367 2368 intr = intr_disable(); 2369 pte = pmap_pte(kernel_pmap, sysm->base); 2370 *pte = PTE_G; 2371 pmap_invalidate_page(kernel_pmap, sysm->base); 2372 intr_restore(intr); 2373 sysm->valid1 = 0; 2374 } 2375#endif 2376} 2377 2378/* 2379 * Maps a sequence of resident pages belonging to the same object. 2380 * The sequence begins with the given page m_start. This page is 2381 * mapped at the given virtual address start. Each subsequent page is 2382 * mapped at a virtual address that is offset from start by the same 2383 * amount as the page is offset from m_start within the object. The 2384 * last page in the sequence is the page with the largest offset from 2385 * m_start that can be mapped at a virtual address less than the given 2386 * virtual address end. Not every virtual page between start and end 2387 * is mapped; only those for which a resident page exists with the 2388 * corresponding offset from m_start are mapped. 2389 */ 2390void 2391pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2392 vm_page_t m_start, vm_prot_t prot) 2393{ 2394 vm_page_t m, mpte; 2395 vm_pindex_t diff, psize; 2396 2397 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2398 2399 psize = atop(end - start); 2400 mpte = NULL; 2401 m = m_start; 2402 rw_wlock(&pvh_global_lock); 2403 PMAP_LOCK(pmap); 2404 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2405 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2406 prot, mpte); 2407 m = TAILQ_NEXT(m, listq); 2408 } 2409 rw_wunlock(&pvh_global_lock); 2410 PMAP_UNLOCK(pmap); 2411} 2412 2413/* 2414 * pmap_object_init_pt preloads the ptes for a given object 2415 * into the specified pmap. This eliminates the blast of soft 2416 * faults on process startup and immediately after an mmap. 2417 */ 2418void 2419pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2420 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2421{ 2422 VM_OBJECT_ASSERT_WLOCKED(object); 2423 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2424 ("pmap_object_init_pt: non-device object")); 2425} 2426 2427/* 2428 * Routine: pmap_change_wiring 2429 * Function: Change the wiring attribute for a map/virtual-address 2430 * pair. 2431 * In/out conditions: 2432 * The mapping must already exist in the pmap. 2433 */ 2434void 2435pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2436{ 2437 pt_entry_t *pte; 2438 2439 PMAP_LOCK(pmap); 2440 pte = pmap_pte(pmap, va); 2441 2442 if (wired && !pte_test(pte, PTE_W)) 2443 pmap->pm_stats.wired_count++; 2444 else if (!wired && pte_test(pte, PTE_W)) 2445 pmap->pm_stats.wired_count--; 2446 2447 /* 2448 * Wiring is not a hardware characteristic so there is no need to 2449 * invalidate TLB. 2450 */ 2451 if (wired) 2452 pte_set(pte, PTE_W); 2453 else 2454 pte_clear(pte, PTE_W); 2455 PMAP_UNLOCK(pmap); 2456} 2457 2458/* 2459 * Copy the range specified by src_addr/len 2460 * from the source map to the range dst_addr/len 2461 * in the destination map. 2462 * 2463 * This routine is only advisory and need not do anything. 2464 */ 2465 2466void 2467pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2468 vm_size_t len, vm_offset_t src_addr) 2469{ 2470} 2471 2472/* 2473 * pmap_zero_page zeros the specified hardware page by mapping 2474 * the page into KVM and using bzero to clear its contents. 2475 * 2476 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2477 */ 2478void 2479pmap_zero_page(vm_page_t m) 2480{ 2481 vm_offset_t va; 2482 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2483 2484 if (MIPS_DIRECT_MAPPABLE(phys)) { 2485 va = MIPS_PHYS_TO_DIRECT(phys); 2486 bzero((caddr_t)va, PAGE_SIZE); 2487 mips_dcache_wbinv_range(va, PAGE_SIZE); 2488 } else { 2489 va = pmap_lmem_map1(phys); 2490 bzero((caddr_t)va, PAGE_SIZE); 2491 mips_dcache_wbinv_range(va, PAGE_SIZE); 2492 pmap_lmem_unmap(); 2493 } 2494} 2495 2496/* 2497 * pmap_zero_page_area zeros the specified hardware page by mapping 2498 * the page into KVM and using bzero to clear its contents. 2499 * 2500 * off and size may not cover an area beyond a single hardware page. 2501 */ 2502void 2503pmap_zero_page_area(vm_page_t m, int off, int size) 2504{ 2505 vm_offset_t va; 2506 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2507 2508 if (MIPS_DIRECT_MAPPABLE(phys)) { 2509 va = MIPS_PHYS_TO_DIRECT(phys); 2510 bzero((char *)(caddr_t)va + off, size); 2511 mips_dcache_wbinv_range(va + off, size); 2512 } else { 2513 va = pmap_lmem_map1(phys); 2514 bzero((char *)va + off, size); 2515 mips_dcache_wbinv_range(va + off, size); 2516 pmap_lmem_unmap(); 2517 } 2518} 2519 2520void 2521pmap_zero_page_idle(vm_page_t m) 2522{ 2523 vm_offset_t va; 2524 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2525 2526 if (MIPS_DIRECT_MAPPABLE(phys)) { 2527 va = MIPS_PHYS_TO_DIRECT(phys); 2528 bzero((caddr_t)va, PAGE_SIZE); 2529 mips_dcache_wbinv_range(va, PAGE_SIZE); 2530 } else { 2531 va = pmap_lmem_map1(phys); 2532 bzero((caddr_t)va, PAGE_SIZE); 2533 mips_dcache_wbinv_range(va, PAGE_SIZE); 2534 pmap_lmem_unmap(); 2535 } 2536} 2537 2538/* 2539 * pmap_copy_page copies the specified (machine independent) 2540 * page by mapping the page into virtual memory and using 2541 * bcopy to copy the page, one machine dependent page at a 2542 * time. 2543 * 2544 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. 2545 */ 2546void 2547pmap_copy_page(vm_page_t src, vm_page_t dst) 2548{ 2549 vm_offset_t va_src, va_dst; 2550 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src); 2551 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst); 2552 2553 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) { 2554 /* easy case, all can be accessed via KSEG0 */ 2555 /* 2556 * Flush all caches for VA that are mapped to this page 2557 * to make sure that data in SDRAM is up to date 2558 */ 2559 pmap_flush_pvcache(src); 2560 mips_dcache_wbinv_range_index( 2561 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE); 2562 va_src = MIPS_PHYS_TO_DIRECT(phys_src); 2563 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst); 2564 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2565 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2566 } else { 2567 va_src = pmap_lmem_map2(phys_src, phys_dst); 2568 va_dst = va_src + PAGE_SIZE; 2569 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2570 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2571 pmap_lmem_unmap(); 2572 } 2573} 2574 2575int unmapped_buf_allowed; 2576 2577void 2578pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 2579 vm_offset_t b_offset, int xfersize) 2580{ 2581 char *a_cp, *b_cp; 2582 vm_page_t a_m, b_m; 2583 vm_offset_t a_pg_offset, b_pg_offset; 2584 vm_paddr_t a_phys, b_phys; 2585 int cnt; 2586 2587 while (xfersize > 0) { 2588 a_pg_offset = a_offset & PAGE_MASK; 2589 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 2590 a_m = ma[a_offset >> PAGE_SHIFT]; 2591 a_phys = VM_PAGE_TO_PHYS(a_m); 2592 b_pg_offset = b_offset & PAGE_MASK; 2593 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 2594 b_m = mb[b_offset >> PAGE_SHIFT]; 2595 b_phys = VM_PAGE_TO_PHYS(b_m); 2596 if (MIPS_DIRECT_MAPPABLE(a_phys) && 2597 MIPS_DIRECT_MAPPABLE(b_phys)) { 2598 pmap_flush_pvcache(a_m); 2599 mips_dcache_wbinv_range_index( 2600 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE); 2601 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) + 2602 a_pg_offset; 2603 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) + 2604 b_pg_offset; 2605 bcopy(a_cp, b_cp, cnt); 2606 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt); 2607 } else { 2608 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys); 2609 b_cp = (char *)a_cp + PAGE_SIZE; 2610 a_cp += a_pg_offset; 2611 b_cp += b_pg_offset; 2612 bcopy(a_cp, b_cp, cnt); 2613 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt); 2614 pmap_lmem_unmap(); 2615 } 2616 a_offset += cnt; 2617 b_offset += cnt; 2618 xfersize -= cnt; 2619 } 2620} 2621 2622/* 2623 * Returns true if the pmap's pv is one of the first 2624 * 16 pvs linked to from this page. This count may 2625 * be changed upwards or downwards in the future; it 2626 * is only necessary that true be returned for a small 2627 * subset of pmaps for proper page aging. 2628 */ 2629boolean_t 2630pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2631{ 2632 pv_entry_t pv; 2633 int loops = 0; 2634 boolean_t rv; 2635 2636 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2637 ("pmap_page_exists_quick: page %p is not managed", m)); 2638 rv = FALSE; 2639 rw_wlock(&pvh_global_lock); 2640 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2641 if (PV_PMAP(pv) == pmap) { 2642 rv = TRUE; 2643 break; 2644 } 2645 loops++; 2646 if (loops >= 16) 2647 break; 2648 } 2649 rw_wunlock(&pvh_global_lock); 2650 return (rv); 2651} 2652 2653/* 2654 * Remove all pages from specified address space 2655 * this aids process exit speeds. Also, this code 2656 * is special cased for current process only, but 2657 * can have the more generic (and slightly slower) 2658 * mode enabled. This is much faster than pmap_remove 2659 * in the case of running down an entire address space. 2660 */ 2661void 2662pmap_remove_pages(pmap_t pmap) 2663{ 2664 pd_entry_t *pde; 2665 pt_entry_t *pte, tpte; 2666 pv_entry_t pv; 2667 vm_page_t m; 2668 struct pv_chunk *pc, *npc; 2669 u_long inuse, bitmask; 2670 int allfree, bit, field, idx; 2671 2672 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2673 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2674 return; 2675 } 2676 rw_wlock(&pvh_global_lock); 2677 PMAP_LOCK(pmap); 2678 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 2679 allfree = 1; 2680 for (field = 0; field < _NPCM; field++) { 2681 inuse = ~pc->pc_map[field] & pc_freemask[field]; 2682 while (inuse != 0) { 2683 bit = ffsl(inuse) - 1; 2684 bitmask = 1UL << bit; 2685 idx = field * sizeof(inuse) * NBBY + bit; 2686 pv = &pc->pc_pventry[idx]; 2687 inuse &= ~bitmask; 2688 2689 pde = pmap_pde(pmap, pv->pv_va); 2690 KASSERT(pde != NULL && *pde != 0, 2691 ("pmap_remove_pages: pde")); 2692 pte = pmap_pde_to_pte(pde, pv->pv_va); 2693 if (!pte_test(pte, PTE_V)) 2694 panic("pmap_remove_pages: bad pte"); 2695 tpte = *pte; 2696 2697/* 2698 * We cannot remove wired pages from a process' mapping at this time 2699 */ 2700 if (pte_test(&tpte, PTE_W)) { 2701 allfree = 0; 2702 continue; 2703 } 2704 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2705 2706 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); 2707 KASSERT(m != NULL, 2708 ("pmap_remove_pages: bad tpte %#jx", 2709 (uintmax_t)tpte)); 2710 2711 /* 2712 * Update the vm_page_t clean and reference bits. 2713 */ 2714 if (pte_test(&tpte, PTE_D)) 2715 vm_page_dirty(m); 2716 2717 /* Mark free */ 2718 PV_STAT(pv_entry_frees++); 2719 PV_STAT(pv_entry_spare++); 2720 pv_entry_count--; 2721 pc->pc_map[field] |= bitmask; 2722 pmap->pm_stats.resident_count--; 2723 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2724 if (TAILQ_EMPTY(&m->md.pv_list)) 2725 vm_page_aflag_clear(m, PGA_WRITEABLE); 2726 pmap_unuse_pt(pmap, pv->pv_va, *pde); 2727 } 2728 } 2729 if (allfree) { 2730 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2731 free_pv_chunk(pc); 2732 } 2733 } 2734 pmap_invalidate_all(pmap); 2735 PMAP_UNLOCK(pmap); 2736 rw_wunlock(&pvh_global_lock); 2737} 2738 2739/* 2740 * pmap_testbit tests bits in pte's 2741 */ 2742static boolean_t 2743pmap_testbit(vm_page_t m, int bit) 2744{ 2745 pv_entry_t pv; 2746 pmap_t pmap; 2747 pt_entry_t *pte; 2748 boolean_t rv = FALSE; 2749 2750 if (m->oflags & VPO_UNMANAGED) 2751 return (rv); 2752 2753 rw_assert(&pvh_global_lock, RA_WLOCKED); 2754 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2755 pmap = PV_PMAP(pv); 2756 PMAP_LOCK(pmap); 2757 pte = pmap_pte(pmap, pv->pv_va); 2758 rv = pte_test(pte, bit); 2759 PMAP_UNLOCK(pmap); 2760 if (rv) 2761 break; 2762 } 2763 return (rv); 2764} 2765 2766/* 2767 * pmap_page_wired_mappings: 2768 * 2769 * Return the number of managed mappings to the given physical page 2770 * that are wired. 2771 */ 2772int 2773pmap_page_wired_mappings(vm_page_t m) 2774{ 2775 pv_entry_t pv; 2776 pmap_t pmap; 2777 pt_entry_t *pte; 2778 int count; 2779 2780 count = 0; 2781 if ((m->oflags & VPO_UNMANAGED) != 0) 2782 return (count); 2783 rw_wlock(&pvh_global_lock); 2784 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2785 pmap = PV_PMAP(pv); 2786 PMAP_LOCK(pmap); 2787 pte = pmap_pte(pmap, pv->pv_va); 2788 if (pte_test(pte, PTE_W)) 2789 count++; 2790 PMAP_UNLOCK(pmap); 2791 } 2792 rw_wunlock(&pvh_global_lock); 2793 return (count); 2794} 2795 2796/* 2797 * Clear the write and modified bits in each of the given page's mappings. 2798 */ 2799void 2800pmap_remove_write(vm_page_t m) 2801{ 2802 pmap_t pmap; 2803 pt_entry_t pbits, *pte; 2804 pv_entry_t pv; 2805 2806 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2807 ("pmap_remove_write: page %p is not managed", m)); 2808 2809 /* 2810 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2811 * set by another thread while the object is locked. Thus, 2812 * if PGA_WRITEABLE is clear, no page table entries need updating. 2813 */ 2814 VM_OBJECT_ASSERT_WLOCKED(m->object); 2815 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2816 return; 2817 rw_wlock(&pvh_global_lock); 2818 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2819 pmap = PV_PMAP(pv); 2820 PMAP_LOCK(pmap); 2821 pte = pmap_pte(pmap, pv->pv_va); 2822 KASSERT(pte != NULL && pte_test(pte, PTE_V), 2823 ("page on pv_list has no pte")); 2824 pbits = *pte; 2825 if (pte_test(&pbits, PTE_D)) { 2826 pte_clear(&pbits, PTE_D); 2827 vm_page_dirty(m); 2828 } 2829 pte_set(&pbits, PTE_RO); 2830 if (pbits != *pte) { 2831 *pte = pbits; 2832 pmap_update_page(pmap, pv->pv_va, pbits); 2833 } 2834 PMAP_UNLOCK(pmap); 2835 } 2836 vm_page_aflag_clear(m, PGA_WRITEABLE); 2837 rw_wunlock(&pvh_global_lock); 2838} 2839 2840/* 2841 * pmap_ts_referenced: 2842 * 2843 * Return the count of reference bits for a page, clearing all of them. 2844 */ 2845int 2846pmap_ts_referenced(vm_page_t m) 2847{ 2848 2849 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2850 ("pmap_ts_referenced: page %p is not managed", m)); 2851 if (m->md.pv_flags & PV_TABLE_REF) { 2852 rw_wlock(&pvh_global_lock); 2853 m->md.pv_flags &= ~PV_TABLE_REF; 2854 rw_wunlock(&pvh_global_lock); 2855 return (1); 2856 } 2857 return (0); 2858} 2859 2860/* 2861 * pmap_is_modified: 2862 * 2863 * Return whether or not the specified physical page was modified 2864 * in any physical maps. 2865 */ 2866boolean_t 2867pmap_is_modified(vm_page_t m) 2868{ 2869 boolean_t rv; 2870 2871 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2872 ("pmap_is_modified: page %p is not managed", m)); 2873 2874 /* 2875 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 2876 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 2877 * is clear, no PTEs can have PTE_D set. 2878 */ 2879 VM_OBJECT_ASSERT_WLOCKED(m->object); 2880 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 2881 return (FALSE); 2882 rw_wlock(&pvh_global_lock); 2883 rv = pmap_testbit(m, PTE_D); 2884 rw_wunlock(&pvh_global_lock); 2885 return (rv); 2886} 2887 2888/* N/C */ 2889 2890/* 2891 * pmap_is_prefaultable: 2892 * 2893 * Return whether or not the specified virtual address is elgible 2894 * for prefault. 2895 */ 2896boolean_t 2897pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2898{ 2899 pd_entry_t *pde; 2900 pt_entry_t *pte; 2901 boolean_t rv; 2902 2903 rv = FALSE; 2904 PMAP_LOCK(pmap); 2905 pde = pmap_pde(pmap, addr); 2906 if (pde != NULL && *pde != 0) { 2907 pte = pmap_pde_to_pte(pde, addr); 2908 rv = (*pte == 0); 2909 } 2910 PMAP_UNLOCK(pmap); 2911 return (rv); 2912} 2913 2914/* 2915 * Apply the given advice to the specified range of addresses within the 2916 * given pmap. Depending on the advice, clear the referenced and/or 2917 * modified flags in each mapping and set the mapped page's dirty field. 2918 */ 2919void 2920pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 2921{ 2922 pd_entry_t *pde, *pdpe; 2923 pt_entry_t *pte; 2924 vm_offset_t va, va_next; 2925 vm_paddr_t pa; 2926 vm_page_t m; 2927 2928 if (advice != MADV_DONTNEED && advice != MADV_FREE) 2929 return; 2930 rw_wlock(&pvh_global_lock); 2931 PMAP_LOCK(pmap); 2932 for (; sva < eva; sva = va_next) { 2933 pdpe = pmap_segmap(pmap, sva); 2934#ifdef __mips_n64 2935 if (*pdpe == 0) { 2936 va_next = (sva + NBSEG) & ~SEGMASK; 2937 if (va_next < sva) 2938 va_next = eva; 2939 continue; 2940 } 2941#endif 2942 va_next = (sva + NBPDR) & ~PDRMASK; 2943 if (va_next < sva) 2944 va_next = eva; 2945 2946 pde = pmap_pdpe_to_pde(pdpe, sva); 2947 if (*pde == NULL) 2948 continue; 2949 2950 /* 2951 * Limit our scan to either the end of the va represented 2952 * by the current page table page, or to the end of the 2953 * range being write protected. 2954 */ 2955 if (va_next > eva) 2956 va_next = eva; 2957 2958 va = va_next; 2959 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++, 2960 sva += PAGE_SIZE) { 2961 if (!pte_test(pte, PTE_MANAGED | PTE_V)) { 2962 if (va != va_next) { 2963 pmap_invalidate_range(pmap, va, sva); 2964 va = va_next; 2965 } 2966 continue; 2967 } 2968 pa = TLBLO_PTE_TO_PA(*pte); 2969 m = PHYS_TO_VM_PAGE(pa); 2970 m->md.pv_flags &= ~PV_TABLE_REF; 2971 if (pte_test(pte, PTE_D)) { 2972 if (advice == MADV_DONTNEED) { 2973 /* 2974 * Future calls to pmap_is_modified() 2975 * can be avoided by making the page 2976 * dirty now. 2977 */ 2978 vm_page_dirty(m); 2979 } else { 2980 pte_clear(pte, PTE_D); 2981 if (va == va_next) 2982 va = sva; 2983 } 2984 } else { 2985 /* 2986 * Unless PTE_D is set, any TLB entries 2987 * mapping "sva" don't allow write access, so 2988 * they needn't be invalidated. 2989 */ 2990 if (va != va_next) { 2991 pmap_invalidate_range(pmap, va, sva); 2992 va = va_next; 2993 } 2994 } 2995 } 2996 if (va != va_next) 2997 pmap_invalidate_range(pmap, va, sva); 2998 } 2999 rw_wunlock(&pvh_global_lock); 3000 PMAP_UNLOCK(pmap); 3001} 3002 3003/* 3004 * Clear the modify bits on the specified physical page. 3005 */ 3006void 3007pmap_clear_modify(vm_page_t m) 3008{ 3009 pmap_t pmap; 3010 pt_entry_t *pte; 3011 pv_entry_t pv; 3012 3013 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3014 ("pmap_clear_modify: page %p is not managed", m)); 3015 VM_OBJECT_ASSERT_WLOCKED(m->object); 3016 KASSERT(!vm_page_xbusied(m), 3017 ("pmap_clear_modify: page %p is exclusive busied", m)); 3018 3019 /* 3020 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set. 3021 * If the object containing the page is locked and the page is not 3022 * write busied, then PGA_WRITEABLE cannot be concurrently set. 3023 */ 3024 if ((m->aflags & PGA_WRITEABLE) == 0) 3025 return; 3026 rw_wlock(&pvh_global_lock); 3027 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 3028 pmap = PV_PMAP(pv); 3029 PMAP_LOCK(pmap); 3030 pte = pmap_pte(pmap, pv->pv_va); 3031 if (pte_test(pte, PTE_D)) { 3032 pte_clear(pte, PTE_D); 3033 pmap_update_page(pmap, pv->pv_va, *pte); 3034 } 3035 PMAP_UNLOCK(pmap); 3036 } 3037 rw_wunlock(&pvh_global_lock); 3038} 3039 3040/* 3041 * pmap_is_referenced: 3042 * 3043 * Return whether or not the specified physical page was referenced 3044 * in any physical maps. 3045 */ 3046boolean_t 3047pmap_is_referenced(vm_page_t m) 3048{ 3049 3050 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3051 ("pmap_is_referenced: page %p is not managed", m)); 3052 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 3053} 3054 3055/* 3056 * Miscellaneous support routines follow 3057 */ 3058 3059/* 3060 * Map a set of physical memory pages into the kernel virtual 3061 * address space. Return a pointer to where it is mapped. This 3062 * routine is intended to be used for mapping device memory, 3063 * NOT real memory. 3064 * 3065 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit. 3066 */ 3067void * 3068pmap_mapdev(vm_paddr_t pa, vm_size_t size) 3069{ 3070 vm_offset_t va, tmpva, offset; 3071 3072 /* 3073 * KSEG1 maps only first 512M of phys address space. For 3074 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 3075 */ 3076 if (MIPS_DIRECT_MAPPABLE(pa + size - 1)) 3077 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa)); 3078 else { 3079 offset = pa & PAGE_MASK; 3080 size = roundup(size + offset, PAGE_SIZE); 3081 3082 va = kva_alloc(size); 3083 if (!va) 3084 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 3085 pa = trunc_page(pa); 3086 for (tmpva = va; size > 0;) { 3087 pmap_kenter_attr(tmpva, pa, PTE_C_UNCACHED); 3088 size -= PAGE_SIZE; 3089 tmpva += PAGE_SIZE; 3090 pa += PAGE_SIZE; 3091 } 3092 } 3093 3094 return ((void *)(va + offset)); 3095} 3096 3097void 3098pmap_unmapdev(vm_offset_t va, vm_size_t size) 3099{ 3100#ifndef __mips_n64 3101 vm_offset_t base, offset; 3102 3103 /* If the address is within KSEG1 then there is nothing to do */ 3104 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 3105 return; 3106 3107 base = trunc_page(va); 3108 offset = va & PAGE_MASK; 3109 size = roundup(size + offset, PAGE_SIZE); 3110 kva_free(base, size); 3111#endif 3112} 3113 3114/* 3115 * perform the pmap work for mincore 3116 */ 3117int 3118pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 3119{ 3120 pt_entry_t *ptep, pte; 3121 vm_paddr_t pa; 3122 vm_page_t m; 3123 int val; 3124 3125 PMAP_LOCK(pmap); 3126retry: 3127 ptep = pmap_pte(pmap, addr); 3128 pte = (ptep != NULL) ? *ptep : 0; 3129 if (!pte_test(&pte, PTE_V)) { 3130 val = 0; 3131 goto out; 3132 } 3133 val = MINCORE_INCORE; 3134 if (pte_test(&pte, PTE_D)) 3135 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 3136 pa = TLBLO_PTE_TO_PA(pte); 3137 if (pte_test(&pte, PTE_MANAGED)) { 3138 /* 3139 * This may falsely report the given address as 3140 * MINCORE_REFERENCED. Unfortunately, due to the lack of 3141 * per-PTE reference information, it is impossible to 3142 * determine if the address is MINCORE_REFERENCED. 3143 */ 3144 m = PHYS_TO_VM_PAGE(pa); 3145 if ((m->aflags & PGA_REFERENCED) != 0) 3146 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 3147 } 3148 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 3149 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 3150 pte_test(&pte, PTE_MANAGED)) { 3151 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 3152 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 3153 goto retry; 3154 } else 3155out: 3156 PA_UNLOCK_COND(*locked_pa); 3157 PMAP_UNLOCK(pmap); 3158 return (val); 3159} 3160 3161void 3162pmap_activate(struct thread *td) 3163{ 3164 pmap_t pmap, oldpmap; 3165 struct proc *p = td->td_proc; 3166 u_int cpuid; 3167 3168 critical_enter(); 3169 3170 pmap = vmspace_pmap(p->p_vmspace); 3171 oldpmap = PCPU_GET(curpmap); 3172 cpuid = PCPU_GET(cpuid); 3173 3174 if (oldpmap) 3175 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 3176 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 3177 pmap_asid_alloc(pmap); 3178 if (td == curthread) { 3179 PCPU_SET(segbase, pmap->pm_segtab); 3180 mips_wr_entryhi(pmap->pm_asid[cpuid].asid); 3181 } 3182 3183 PCPU_SET(curpmap, pmap); 3184 critical_exit(); 3185} 3186 3187void 3188pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3189{ 3190} 3191 3192/* 3193 * Increase the starting virtual address of the given mapping if a 3194 * different alignment might result in more superpage mappings. 3195 */ 3196void 3197pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 3198 vm_offset_t *addr, vm_size_t size) 3199{ 3200 vm_offset_t superpage_offset; 3201 3202 if (size < NBSEG) 3203 return; 3204 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3205 offset += ptoa(object->pg_color); 3206 superpage_offset = offset & SEGMASK; 3207 if (size - ((NBSEG - superpage_offset) & SEGMASK) < NBSEG || 3208 (*addr & SEGMASK) == superpage_offset) 3209 return; 3210 if ((*addr & SEGMASK) < superpage_offset) 3211 *addr = (*addr & ~SEGMASK) + superpage_offset; 3212 else 3213 *addr = ((*addr + SEGMASK) & ~SEGMASK) + superpage_offset; 3214} 3215 3216#ifdef DDB 3217DB_SHOW_COMMAND(ptable, ddb_pid_dump) 3218{ 3219 pmap_t pmap; 3220 struct thread *td = NULL; 3221 struct proc *p; 3222 int i, j, k; 3223 vm_paddr_t pa; 3224 vm_offset_t va; 3225 3226 if (have_addr) { 3227 td = db_lookup_thread(addr, TRUE); 3228 if (td == NULL) { 3229 db_printf("Invalid pid or tid"); 3230 return; 3231 } 3232 p = td->td_proc; 3233 if (p->p_vmspace == NULL) { 3234 db_printf("No vmspace for process"); 3235 return; 3236 } 3237 pmap = vmspace_pmap(p->p_vmspace); 3238 } else 3239 pmap = kernel_pmap; 3240 3241 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n", 3242 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid, 3243 pmap->pm_asid[0].gen); 3244 for (i = 0; i < NPDEPG; i++) { 3245 pd_entry_t *pdpe; 3246 pt_entry_t *pde; 3247 pt_entry_t pte; 3248 3249 pdpe = (pd_entry_t *)pmap->pm_segtab[i]; 3250 if (pdpe == NULL) 3251 continue; 3252 db_printf("[%4d] %p\n", i, pdpe); 3253#ifdef __mips_n64 3254 for (j = 0; j < NPDEPG; j++) { 3255 pde = (pt_entry_t *)pdpe[j]; 3256 if (pde == NULL) 3257 continue; 3258 db_printf("\t[%4d] %p\n", j, pde); 3259#else 3260 { 3261 j = 0; 3262 pde = (pt_entry_t *)pdpe; 3263#endif 3264 for (k = 0; k < NPTEPG; k++) { 3265 pte = pde[k]; 3266 if (pte == 0 || !pte_test(&pte, PTE_V)) 3267 continue; 3268 pa = TLBLO_PTE_TO_PA(pte); 3269 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT); 3270 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n", 3271 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa); 3272 } 3273 } 3274 } 3275} 3276#endif 3277 3278#if defined(DEBUG) 3279 3280static void pads(pmap_t pm); 3281void pmap_pvdump(vm_offset_t pa); 3282 3283/* print address space of pmap*/ 3284static void 3285pads(pmap_t pm) 3286{ 3287 unsigned va, i, j; 3288 pt_entry_t *ptep; 3289 3290 if (pm == kernel_pmap) 3291 return; 3292 for (i = 0; i < NPTEPG; i++) 3293 if (pm->pm_segtab[i]) 3294 for (j = 0; j < NPTEPG; j++) { 3295 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 3296 if (pm == kernel_pmap && va < KERNBASE) 3297 continue; 3298 if (pm != kernel_pmap && 3299 va >= VM_MAXUSER_ADDRESS) 3300 continue; 3301 ptep = pmap_pte(pm, va); 3302 if (pte_test(ptep, PTE_V)) 3303 printf("%x:%x ", va, *(int *)ptep); 3304 } 3305 3306} 3307 3308void 3309pmap_pvdump(vm_offset_t pa) 3310{ 3311 register pv_entry_t pv; 3312 vm_page_t m; 3313 3314 printf("pa %x", pa); 3315 m = PHYS_TO_VM_PAGE(pa); 3316 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3317 pv = TAILQ_NEXT(pv, pv_list)) { 3318 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 3319 pads(pv->pv_pmap); 3320 } 3321 printf(" "); 3322} 3323 3324/* N/C */ 3325#endif 3326 3327 3328/* 3329 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3330 * It takes almost as much or more time to search the TLB for a 3331 * specific ASID and flush those entries as it does to flush the entire TLB. 3332 * Therefore, when we allocate a new ASID, we just take the next number. When 3333 * we run out of numbers, we flush the TLB, increment the generation count 3334 * and start over. ASID zero is reserved for kernel use. 3335 */ 3336static void 3337pmap_asid_alloc(pmap) 3338 pmap_t pmap; 3339{ 3340 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3341 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3342 else { 3343 if (PCPU_GET(next_asid) == pmap_max_asid) { 3344 tlb_invalidate_all_user(NULL); 3345 PCPU_SET(asid_generation, 3346 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3347 if (PCPU_GET(asid_generation) == 0) { 3348 PCPU_SET(asid_generation, 1); 3349 } 3350 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3351 } 3352 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3353 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3354 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3355 } 3356} 3357 3358static pt_entry_t 3359init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot) 3360{ 3361 pt_entry_t rw; 3362 3363 if (!(prot & VM_PROT_WRITE)) 3364 rw = PTE_V | PTE_RO; 3365 else if ((m->oflags & VPO_UNMANAGED) == 0) { 3366 if ((access & VM_PROT_WRITE) != 0) 3367 rw = PTE_V | PTE_D; 3368 else 3369 rw = PTE_V; 3370 } else 3371 /* Needn't emulate a modified bit for unmanaged pages. */ 3372 rw = PTE_V | PTE_D; 3373 return (rw); 3374} 3375 3376/* 3377 * pmap_emulate_modified : do dirty bit emulation 3378 * 3379 * On SMP, update just the local TLB, other CPUs will update their 3380 * TLBs from PTE lazily, if they get the exception. 3381 * Returns 0 in case of sucess, 1 if the page is read only and we 3382 * need to fault. 3383 */ 3384int 3385pmap_emulate_modified(pmap_t pmap, vm_offset_t va) 3386{ 3387 pt_entry_t *pte; 3388 3389 PMAP_LOCK(pmap); 3390 pte = pmap_pte(pmap, va); 3391 if (pte == NULL) 3392 panic("pmap_emulate_modified: can't find PTE"); 3393#ifdef SMP 3394 /* It is possible that some other CPU changed m-bit */ 3395 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) { 3396 tlb_update(pmap, va, *pte); 3397 PMAP_UNLOCK(pmap); 3398 return (0); 3399 } 3400#else 3401 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) 3402 panic("pmap_emulate_modified: invalid pte"); 3403#endif 3404 if (pte_test(pte, PTE_RO)) { 3405 PMAP_UNLOCK(pmap); 3406 return (1); 3407 } 3408 pte_set(pte, PTE_D); 3409 tlb_update(pmap, va, *pte); 3410 if (!pte_test(pte, PTE_MANAGED)) 3411 panic("pmap_emulate_modified: unmanaged page"); 3412 PMAP_UNLOCK(pmap); 3413 return (0); 3414} 3415 3416/* 3417 * Routine: pmap_kextract 3418 * Function: 3419 * Extract the physical page address associated 3420 * virtual address. 3421 */ 3422vm_paddr_t 3423pmap_kextract(vm_offset_t va) 3424{ 3425 int mapped; 3426 3427 /* 3428 * First, the direct-mapped regions. 3429 */ 3430#if defined(__mips_n64) 3431 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END) 3432 return (MIPS_XKPHYS_TO_PHYS(va)); 3433#endif 3434 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END) 3435 return (MIPS_KSEG0_TO_PHYS(va)); 3436 3437 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END) 3438 return (MIPS_KSEG1_TO_PHYS(va)); 3439 3440 /* 3441 * User virtual addresses. 3442 */ 3443 if (va < VM_MAXUSER_ADDRESS) { 3444 pt_entry_t *ptep; 3445 3446 if (curproc && curproc->p_vmspace) { 3447 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3448 if (ptep) { 3449 return (TLBLO_PTE_TO_PA(*ptep) | 3450 (va & PAGE_MASK)); 3451 } 3452 return (0); 3453 } 3454 } 3455 3456 /* 3457 * Should be kernel virtual here, otherwise fail 3458 */ 3459 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END); 3460#if defined(__mips_n64) 3461 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END); 3462#endif 3463 /* 3464 * Kernel virtual. 3465 */ 3466 3467 if (mapped) { 3468 pt_entry_t *ptep; 3469 3470 /* Is the kernel pmap initialized? */ 3471 if (!CPU_EMPTY(&kernel_pmap->pm_active)) { 3472 /* It's inside the virtual address range */ 3473 ptep = pmap_pte(kernel_pmap, va); 3474 if (ptep) { 3475 return (TLBLO_PTE_TO_PA(*ptep) | 3476 (va & PAGE_MASK)); 3477 } 3478 } 3479 return (0); 3480 } 3481 3482 panic("%s for unknown address space %p.", __func__, (void *)va); 3483} 3484 3485 3486void 3487pmap_flush_pvcache(vm_page_t m) 3488{ 3489 pv_entry_t pv; 3490 3491 if (m != NULL) { 3492 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3493 pv = TAILQ_NEXT(pv, pv_list)) { 3494 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3495 } 3496 } 3497} 3498